Kilopass Technology, Inc. v. Sidense Corporation

Filing 147

ORDER RE: CLAIM CONSTRUCTION (SI, COURT STAFF) (Filed on 8/31/2011)

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1 2 3 4 5 IN THE UNITED STATES DISTRICT COURT 6 FOR THE NORTHERN DISTRICT OF CALIFORNIA 7 8 KILOPASS TECHNOLOGY INC., 9 United States District Court For the Northern District of California 10 11 12 No. C 10-02066 SI Plaintiff, ORDER RE: CLAIM CONSTRUCTION v. SIDENSE CORP., Defendant. / 13 14 On August 1 and 2, 2011, the Court held a tutorial and a claim construction hearing. After 15 consideration of the parties’ papers and presentations, the Court construes the claims at issue as follows. 16 BACKGROUND 17 18 Plaintiff Kilopass Technology, Inc., is a company that markets “a novel way of storing data 19 permanently inside integrated circuits . . . by creating a breakdown in the transistor, safely and reliably.” 20 Second Am. Compl. 8. Plaintiff alleges that defendant Sidense Corporation “has knowingly copied 21 Kilopass’ patented technology and has been selling and offering for sale Kilopass’ patented technology 22 without authorization from Kilopass.” Id. at 18. In particular, plaintiff alleges that defendant infringed 23 U.S. Patent Nos. 6,940,751 (“'751 Patent”), 6,777,757 (“'757 Patent”), and 6,856,540 (“'540 Patent”). 24 Id. at 10, 17. Plaintiff also alleges that defendant has been “sowing deceit in the marketplace” by 25 “falsely alleg[ing] in the marketplace statements to the effect that Kilopass has no intellectual property 26 issues with Sidense.” Id. at 24. 27 Plaintiff originally filed suit in this Court on May 14, 2010. Plaintiff filed its second amended 28 complaint on October 14,. 2010. On December 13, 2010, the Court granted in part and denied in part 1 a motion to dismiss, leaving six causes of action in the case: three patent infringement claims, one false 2 advertisement and disparagement claim, one intentional interference with prospective economic 3 relations claim, and one unfair competition claim. 4 5 LEGAL STANDARD Claim construction is a matter of law. Markman v. Westview Instr., Inc., 517 U.S. 370, 372 7 (1996). Terms contained in claims are “generally given their ordinary and customary meaning.” 8 Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005). “[T]he ordinary and customary meaning 9 of a claim term is the meaning that the term would have to a person of ordinary skill in the art in 10 United States District Court For the Northern District of California 6 question at the time of the invention.” Id. at 1312. In determining the proper construction of a claim, 11 a court begins with the intrinsic evidence of record, consisting of the claim language, the patent 12 specification, and, if in evidence, the prosecution history. Id. at 1313; see also Vitronics Corp. v. 13 Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). “The appropriate starting point . . . is always 14 with the language of the asserted claim itself.” Comark Communications, Inc. v. Harris Corp., 156 F.3d 15 1182, 1186 (Fed. Cir. 1998); see also Abtox, Inc. v. Exitron Corp., 122 F.3d 1019, 1023 (Fed. Cir. 16 1997). 17 Accordingly, although claims speak to those skilled in the art, in construing a claim, claim terms 18 are given their ordinary and accustomed meaning unless examination of the specification, prosecution 19 history, and other claims indicates that the inventor intended otherwise. See Electro Medical Systems, 20 S.A. v. Cooper Life Sciences, Inc., 34 F.3d 1048, 1053 (Fed. Cir. 1994). The written description can 21 provide guidance as to the meaning of the claims, thereby dictating the manner in which the claims are 22 to be construed, even if the guidance is not provided in explicit definitional format. SciMed Life 23 Systems, Inc. v. Advanced Cardiovascular Systems, Inc., 242 F.3d 1337, 1344 (Fed. Cir. 2001). In other 24 words, the specification may define claim terms “by implication” such that the meaning may be “found 25 in or ascertained by a reading of the patent documents.” Vitronics, 90 F.3d at 1584 n.6. 26 The claims must be read in view of the specification. Markman, 52 F.3d at 978. Although 27 claims are interpreted in light of the specification, this “does not mean that everything expressed in the 28 specification must be read into all the claims.” Raytheon Co. v. Roper Corp., 724 F.2d 951, 957 (Fed. 2 1 Cir. 1983). For instance, limitations from a preferred embodiment described in the specification 2 generally should not be read into the claim language. See Comark, 156 F.3d at 1187. However, it is 3 a fundamental rule that “claims must be construed so as to be consistent with the specification.” 4 Phillips, 415 F.3d at 1316. Therefore, if the specification reveals an intentional disclaimer or disavowal 5 of claim scope, the claims must be read consistent with that limitation. Id. Finally, the Court may consider the prosecution history of the patent, if in evidence. The 7 prosecution history limits the interpretation of claim terms so as to exclude any interpretation that was 8 disclaimed during prosecution. See Southwall Technologies, Inc. v. Cardinal IG Co., 54 F.3d 1570, 9 1576 (Fed. Cir. 1995). In most situations, analysis of this intrinsic evidence alone will resolve claim 10 United States District Court For the Northern District of California 6 construction disputes. See Vitronics, 90 F.3d at 1583. Courts should not rely on extrinsic evidence in 11 claim construction to contradict the meaning of claims discernable from examination of the claims, the 12 written description, and the prosecution history. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 13 F.3d 1298, 1308 (Fed. Cir. 1999) (citing Vitronics, 90 F.3d at 1583). However, it is entirely appropriate 14 “for a court to consult trustworthy extrinsic evidence to ensure that the claim construction it is tending 15 to from the patent file is not inconsistent with clearly expressed, plainly apposite, and widely held 16 understandings in the pertinent technical field.” Id. Extrinsic evidence “consists of all evidence external 17 to the patent and prosecution history, including expert and inventor testimony, dictionaries, and learned 18 treatises.” Phillips, 415 F.3d at 1317. All extrinsic evidence should be evaluated in light of the intrinsic 19 evidence. Id. at 1319. 20 21 22 DISCUSSION I. Agreements 23 The parties agree that each term that they have identified, though appearing in multiple 24 independent claims in as many as three different patents, always means the same thing whenever it is 25 used in the patents. 26 The parties agree on the following definitions for terms: 27 • 28 Memory array: “a grid of memory cells that are organized in rows and columns” 3 1 • Floating: “not electrically connected to a voltage source” 2 • Programmable memory array: “a memory array comprised of programmable memory cells” • Memory cell which has been programmed: “a programmable memory cell which, during programming, has been physically changed” • Breakdown: “physically changing the electrical insulating characteristics of a gate dielectric under voltage induced stress” 3 4 5 6 See Pl. Br. at 21. 7 At the claim construction hearing, it became clear that the parties also agree on the following 8 9 United States District Court For the Northern District of California 10 11 12 13 definitions: • Spaced apart relationship: “not in physical contact”1 • Gate dielectric: “a gate insulating film” • Programmed: [having had] “a physical conducting link between the gate and the channel formed by breaking down the gate dielectric” • Laterally separated by a distance D: “no overlap in the vertical direction between the gate and the second doped region” 14 15 16 17 18 19 20 21 22 23 The parties agreed that a slightly edited combination of their two definitions of semiconductor2 was accurate, and the Court adopts that definition: “a material, like silicon, whose conductivity is in the range between that of metals and insulators, and whose conductivity can be altered by the introduction of an impurity.”3 Finally, the parties agree that a person of ordinary skill in the art is “a person with at least a bachelor’s degree in electrical engineering, chemical engineering, mechanical engineering, materials sciences, computer sciences, or equivalent, with at least two years of graduate or related work experience in the semiconductor field.” Expert Decl. of Dean Niekirk (Doc. 114), ¶ 5 (Kilopass); Expert Decl. of Milton Gosney (Doc. 127), ¶ 5 (Sidense). 24 1 25 26 27 Plaintiff agreed to this definition, which had been proposed by defendant, upon defendant’s assurances that “not in physical contact” does not mean not in electrical contact. 2 The term semiconductor never appears in the patent claims outside of the phrase doped semiconductor region. 3 28 The parties also agreed that their proposed definitions for programmable memory cell were nearly indistinguishable, though each insisted that its definition was preferable. 4 1 II. Disagreements 2 The remaining constructions about which the parties disagree are of the terms: bitline/column 3 bitline; wordline/row wordline; transistor; memory cell; programmed doped region; doped 4 semiconductor region; gate; channel region; substrate; lightly doped region; conductive material; 5 and row wordline segment. The parties included in their list of the ten claim terms whose constructions 6 they believed to be most significant to the resolution of this case, and to be case- or claim-dispositive, 7 the terms bitline/column bitline; wordline/row wordline; transistor; memory cell; programmed 8 doped region; doped semiconductor region; gate; and channel region. These terms are used 9 throughout the three patents, and, as explained above, the parties agree that each term need only be United States District Court For the Northern District of California 10 defined once. 11 12 A. 13 In its infringement contentions, plaintiff alleges that defendant is infringing, contributing to the 14 infringement of, and inducing the infringement of: (1) claims 1, 2, 7, 8, 12, and 14 of the '757 Patent; 15 (2) claims 1, 3, 5, and 6 of the '540 Patent; and (3) claims 1, 2, 3, 5, 6, 9, 10, 12, and 14 of the '751 16 Patent. See Infringement Contentions (Doc. 97). Those claims are listed below. Nearly every word or 17 phrase was identified in the parties’ joint claim construction statement as disputed. The eight remaining 18 disputed, significant, and potentially dispositive terms are highlighted in bold. Infringement contentions 19 20 21 22 23 24 25 26 27 28 1. The ‘757 patent: claims 1, 2, 7, 8, 12, and 14 1. A programmable memory cell useful in memory array having column bitlines and row wordlines, the memory cell comprising: a transistor having a gate, a gate dielectric between the gate and over a substrate, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines; a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines; and a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. 5 1 2. The memory cell of claim 1 wherein said column bitlines are connected to said gate by a column bitline segment. 2 [. . .] 3 4 5 6 7 8 9 United States District Court For the Northern District of California 10 11 12 7. The memory cell of claim 1 wherein said first doped semiconductor region is floating. 8. A programmable memory array comprising a plurality of row wordlines, a plurality of column bitlines, and a plurality of memory cells at respective crosspoints of the row wordlines and column bitlines, each of the memory cells comprising: a transistor having a gate, a gate dielectric between the gate and over a substrate, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines; a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines; and 13 wherein said memory cells further including a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. 14 [...] 15 16 17 18 19 12. The memory array of claim 8 wherein said transistors have their gate and said second doped semiconductor region is laterally separated by a distance D. [...] 14. The memory array of claim 8 wherein the transistors have their first doped semiconductor regions floating. '757 Patent, Col. 10 ln. 36–Col. 12 ln. 21. 20 21 22 23 24 25 26 27 28 2. The '540 Patent: claims 1, 3, 5, and 6 1. A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising: a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines; a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines; and 6 1 a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. 2 [...] 3 4 5 6 3. The memory cell of claim 1 wherein the gate and said second doped semiconductor region is laterally separated by a distance D. [...] 5. The memory cell of claim 1 wherein said first doped semiconductor region is floating. 7 8 9 6. The memory cell of claim 1 further including a lightly doped region formed in said substrate in said channel region. '540 Patent, Col. 10 ln. 61–Col. 12 ln. 31. United States District Court For the Northern District of California 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3. The '751 Patent: claims 1, 2, 3, 5, 6, 9, 10, 12, and 14 1. A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising: a transistor have a gate, a gate dielectric between the gate and over a substrate, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate; and wherein the second doped semiconductor region of the transistor is connected to one of said row wordlines, and where in said gate dielectric is formed such that the gate dielectric is more susceptible to breakdown near the first doped semiconductor region than said second doped semiconductor region. 2. The memory cell of claim 1 wherein said row wordlines are formed from a buried N+ layer. 3. The memory cell of claim 1 wherein the gate dielectric of the transistor is thicker proximal to the second doped semiconductor region than to the first doped semiconductor region. [...] 5. The memory cell of claim 1 wherein said gate is formed from one of said column bitlines. 6. The memory cell of claim 1 wherein said memory cells further including a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. [...] 9. A programmable memory array comprising a plurality of row wordlines, a plurality of column bitlines, and a plurality of memory cells at respective crosspoints of 7 1 the row wordlines and column bitlines, each of the memory cells comprising: 2 a transistor having a gate, a gate dielectric between the gate and over a substrate, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines; and 3 4 5 wherein the second doped semiconductor region of the transistor is connected to one of said row wordlines, said gate dielectric is formed such that the gate dielectric is more susceptible to breakdown near the first doped semiconductor region than said second doped semiconductor region. 6 7 8 10. The memory array of claim 9 wherein said row wordlines are formed from a buried N+ layer. 9 United States District Court For the Northern District of California 10 11 [...] 12. The memory array of claim 9 wherein the gate dielectric of the transistor is thicker proximal to the second doped semiconductor region than to the first doped semiconductor region. 12 13 14 15 [...] 14. The memory array of claim 9 wherein said memory cells further including a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. '751 Patent, Col. 14 ln. 29–Col. 16 ln. 27. 16 17 B. 18 Disputed terms 1. Bitline/column bitline and wordline/row wordline 19 The parties agree that bitline and column bitline are interchangeable terms, and that wordline 20 and row wordline are interchangeable as well.4 Plaintiff argues that all four terms mean the same 21 thing: “a line that connects to one terminal of each memory cell in a memory array.” Defendant argues 22 that bitline and column bitline should be defined as “the line that connects the memory cell to the 23 sensing circuit during the read operation”; and that wordline and column wordline should be defined 24 differently, as “the line connected to the memory cell, which is selected by the row addresses.” 25 Plaintiff argues that “[a]s long as the wordlines and bitlines are arranged so that all memory cells 26 connected to such wordlines and bitlines can be addressed, the wordlines and bitlines are 27 4 28 The term bitline never appears in the patent claims outside of the phrase column bitline and the term wordline never appears in the patent claims outside of the phrase row wordline. 8 1 interchangeable.” Joint Appendix (Doc. 103-1), at 9. However, in briefing and at the claim construction 2 hearing, plaintiff repeatedly acknowledges that wordlines and bitlines are distinguishable within a 3 memory array because they are orthogonal. The Court will not define two different terms to mean 4 precisely the same thing when they are not identical. 5 Defendant argues that plaintiff’s patent claims are limited to memory cells where the bitline is 6 connected to the gate and the wordline is connected to the source. However, defendant’s proposed 7 definitions do not merely relate to where the wordlines and bitlines are connected to each memory cell, 8 but more specifically places them within an external structure and operating procedure. Defendant is 9 contended to have infringed claims regarding the internal workings of memory cells and the memory United States District Court For the Northern District of California 10 arrays containing such cells, not external structures and operating procedures.5 11 The meaning of the terms contained in the patents in suit are as follows: 12 • 13 14 Bitline and column bitline are defined identically as: “a line orthogonal to the row wordline that connects to a terminal of each memory cell in a memory array.” • 15 Wordline and row wordline are defined identically as: “a line orthogonal to the column bitline that connects to a terminal of each memory cell in a memory array.” 16 17 2. Transistor 18 Plaintiff argues that the term transistor should be given its ordinary and customary meaning, 19 and provides a definition from an internet source: “a solid-state semiconductor device that can regulate 20 electric 21 http://www.businessdictionary.com/definition/transistor.html). Defendant argues that transistor should 22 be defined as “a MOS transistor structure.”6 Defendant argues that each time the term is used in the 23 patent claims, it is described as having a particular structure, and that only MOS transistors have that current flowing through it.” See Joint Appendix at 15 (citing 24 25 26 27 28 5 The patentee for the '540 Patent and the '751 Patent makes certain claims for “method[s] of operating a programmable memory array,” but plaintiff does not make infringement allegations with regard to those claims. It will be of little assistance to the adjudication of this case to adopt definitions containing highly technical terms such as “sensing circuit” that themselves are nowhere defined and are, at most, tangentially related to the claims at issue in this suit. 6 Previously, defendant proposed the definition “a MOS transistor.” Joint Appendix at 15. 9 1 structure. Defendant argues there is no indication that the patentee contemplated any alternative to the 2 MOS transistor structure. Plaintiff argues that defendant’s definition is tautological and artificially 3 limited, and that it would limit the invention to a single embodiment. 4 The parties do not merely disagree over whether transistor, as used in the patent claims, refers 5 only to a MOS transistor. They have an identical disagreement with regard to the memory cell, doped 6 semiconductor region, gate, channel region, and substrate, as defendant wishes the Court to construe 7 each as limited to how the element appears in or in relation to a MOS transistor or MOS transistor 8 structure. Of particular import appears to be the question of whether the claims are limited to memory 9 cells containing transistors that have both source and drain regions. United States District Court For the Northern District of California 10 The parties agree that the transistors in the memory cells claimed in plaintiff's patents are not 11 traditional MOS transistors. For example, certain claims are for memory cells in which one doped 12 semiconductor region is left “floating,” e.g. '757 Patent, claims 7 & 13 (which the parties agree means 13 “not electrically connected to a voltage source”), which is different from a traditional MOS transistor. 14 Plaintiff argues that it is incorrect, therefore, to limit its claims to memory cells with MOS transistor 15 structures. Defendant argues that the differences between the transistors in the claimed memory cells 16 and traditional MOS transistors all relate to the way the transistors are connected and operate, not to 17 how they are structured, and therefore the claims are limited to memory cells containing MOS transistor 18 structures. 19 Defendant’s distinction between the structure of a transistor on the one hand, and the operation 20 and connectivity of a transistor on the other, is artificial and confusing. The patentee discusses 21 “floating” drains as both a structural requirement of certain claimed memory cells, see '757 Patent, claim 22 7 (memory cell); '540 Patent, claim 5 (memory cell); '757 Patent, claim 14 (memory cells in a memory 23 array), and as an attribute of a claimed method of operation, see '540 Patent, claim 8.7 To the extent that 24 defendant is concerned about restricting the claims to transistors with certain components, claim 1 in 25 each patent lists specific transistor components, as do claim 8 of the '757 Patent and claim 9 of the '751 26 7 27 28 In the '757 Patent, claims 1-7 are for particular “programmable memory cell[s] useful in memory array,” and claims 8-14 are for particular “programmable memory array[s].” In the '540 Patent, claims 1-6 are for memory cells, and claims 7-11 are for “method[s] of operating a programmable memory array.” 10 1 Patent, and each infringement contention alleges infringement of either one of those claims, or of 2 another claim that incorporates by reference those claimed memory cells or memory arrays. See Hynix 3 Semiconductor Inc. v. Toshiba Corp., No. C–04–04708 VRW, 2006 WL 2547463, * 10 (N.D. Cal. Sept. 4 1, 2006) (declining to construe a term “as necessarily including . . . limitations” that are themselves 5 specified in the claim containing the term, because “it makes little sense” and is “redundant”). For these reasons, the term transistor does not mean “a MOS transistor structure.” And for 7 these same reasons, the terms memory cell, doped semiconductor region, gate, channel region, and 8 substrate, do not mean those components or units only as they are contained in or otherwise a part of 9 a MOS transistor or MOS transistor structure, or comprised of a MOS transistor, as urged by defendant 10 United States District Court For the Northern District of California 6 and discussed in more detail below. Rather, transistor should be given its ordinary and customary 11 meaning: “An active component of an electronic circuit consisting of a small block of semiconducting 12 material to which electrical contacts are made, and which may be used as an amplifier, detector, or 13 switch to control the flow of current.” See Transistor, McGraw-Hill Dictionary of Scientific and 14 Technical Terms 2176 (6th ed. 2003); Transistor, The Authoritative Dictionary of IEEE Standards 15 Terms (7th ed. 2000). 16 17 3. Memory cell 18 Plaintiff argues that memory cell should be defined as “a basic unit of memory.” At one point, 19 defendant argued that memory cell should be defined as “a semiconductor memory device comprised 20 of a single MOS transistor that stores data.” Defendant now argues that the terms means “a single MOS 21 transistor that stores data.” 22 It appears that defendant is now arguing that the memory cell is the transistor that it comprises. 23 Defendant does not explain then why two different terms are used, and defendant’s expert does not make 24 any assertions in support of this definition or any other definition of memory cell. Additionally, 25 defendant proposes that the transistors in the memory cells are MOS transistors, and the Court has 26 already rejected defendant’s more limited contention that the transistors in the patent claims are 27 structured—but not connected or operated—as MOS transistors. 28 Each patent claims a particular memory cell in claim 1, and variations of that memory cell in 11 1 subsequent claims. To define memory cell with reference only to a number of transistors is incorrect 2 as a matter of law. To define memory cell differently for each claim is cumbersome; the parties agree 3 that it is unnecessary; and to do so accurately essentially would involve transcribing the patent. 4 The Court determines that the term memory cell does not require construction. See Phillips, 415 5 F.3d at 1314 (“In some cases, the ordinary meaning of claim language as understood by a person of skill 6 in the art may be readily apparent even to lay judges, and claim construction in such cases involves little 7 more than the application of the widely accepted meaning of commonly understood words.”). 8 9 4. Programmed doped region United States District Court For the Northern District of California 10 Plaintiff argues that programmed doped region should be defined as “a doped region in a 11 channel region of a substrate under the gate caused by breaking down the gate dielectric.” Defendant 12 argues that programmed doped region should be defined as “a highly doped n+ (or p+) region formed 13 in the channel region of the oppositely doped substrate of a [programmed] memory cell as a result of 14 programming.” Previously, defendant argues that programmed doped region should be defined as “a 15 highly doped (n+ or p+) region formed in the substrate of a programmed memory cell as a result of 16 programming.”8 17 The main disagreements between the parties are whether the term programmed doped region 18 is limited to “highly doped n+ (or p+) region,” and whether it is limited to being formed in the channel 19 region of the “oppositely doped substrate.” In support of its argument, defendant derives limitations 20 from the specifications, but the specifications do not disclaim or disavow the ordinary and customary 21 meaning of the term. See Phillips, 415 F.3d at 1316; Raytheon, 724 F.2d at 957. 22 The parties have already agreed to the definition of the term programmed. Both parties use the 23 phrase “doped region” to define the term programmed doped region. And, below, the Court defines 24 doped semiconductor region by reference to the parties’ agreed upon definition for semiconductor, 25 and according to the ordinary and customary definition of programmed . . . region. 26 27 28 8 Defendant noted in the joint claim construction filings that part of its argument was based on similarities of crosshatching in figures included in the '757 Patent. Defendant appears to have abandoned this argument before briefing. 12 1 2 Accordingly, the Court defines programmed doped region as “a doped region formed in the channel region of the substrate of a memory cell as a result of programming.” 3 4 5. Doped semiconductor region Plaintiff argues that doped semiconductor region means “a semiconductor region that contains 6 a level of impurity.” Defendant argues that it means “the source or drain structure of a MOS transistor 7 structure.” Defendant previously argued that it means “a region of semiconductor material, to which 8 impurities are added to create one side of a p-n junction.” Plaintiff does not object to defendant’s prior 9 definition, except to the extent that it believes that inclusion of the phrase “p-n junction” is confusing, 10 United States District Court For the Northern District of California 5 and that the claims also leave room for the impurities to create p-p junctions and n-n junctions. The 11 Court agrees. 12 The Court has already rejected defendant’s argument that parts of the claimed transistors should 13 be limited to being parts of MOS transistors or MOS transistor structures. The Court defines doped 14 semiconductor region as “a region of semiconductor material to which impurities are added to modify 15 the electron or hole concentration in that semiconductor.” 16 17 6. Gate and channel region 18 Plaintiff argues that a gate is “an electrode region that is above the channel region,” and that 19 a channel region is “a region under the gate in the substrate where the channel is located.” Defendant 20 argues that the gate is “the MOS transistor electrode which controls conductivity of the channel region,” 21 and that the channel region is “in a MOS transistor, a region of the substrate beneath the gate defined 22 by the space between first and second doped semiconductor regions, whose electrical conductivity is 23 controlled by the gate.” Previously, defendant defined channel region without the phrase “in a MOS 24 transistor.” 25 The Court has already rejected defendant’s argument that parts of the claimed transistors should 26 be limited to being parts of MOS transistors or MOS transistor structures. The Court has also rejected 27 defendant’s argument that terms should be defined in relation to methods of operation. The Court 28 defines gate as “an electrode region that is above the channel region,” and channel region as “a region 13 1 of the substrate beneath the gate defined by the space between the first and second doped semiconductor 2 regions.” 3 4 CONCLUSION 5 The Court hereby adopts the following constructions, with respect to every claim in each patent in which the word or phrase appears. Based on the agreement of the parties: 7 • Memory array: “a grid of memory cells that are organized in rows and columns” 8 • Floating: “not electrically connected to a voltage source” 9 • Programmable memory array: “a memory array comprised of programmable memory cells” 10 United States District Court For the Northern District of California 6 • Memory cell which has been programmed: “a programmable memory cell which, during 11 12 programming, has been physically changed” • 13 Breakdown: “physically changing the electrical insulating characteristics of a gate dielectric under voltage induced stress” 14 • Spaced apart relationship: “not in physical contact”9 15 • Gate dielectric: “a gate insulating film” 16 • Programmed: [having had] “a physical conducting link between the gate and the channel 17 18 formed by breaking down the gate dielectric” • 19 20 Laterally separated by a distance D: “no overlap in the vertical direction between the gate and the second doped region” • 21 Semiconductor: “a material, like silicon, whose conductivity is in the range between that of metals and insulators, and whose conductivity can be altered by the introduction of an impurity.” 22 23 For the reasons stated above: 24 • 25 26 Bitline and column bitline: “a line orthogonal to the row wordline that connects to a terminal of each memory cell in a memory array.” • Wordline and row wordline: “a line orthogonal to the column bitline that connects to a 27 9 28 Plaintiff agreed to this definition, which had been proposed by defendant, upon defendant’s assurances that “not in physical contact” does not mean not in electrical contact. 14 1 2 terminal of each memory cell in a memory array.” • Transistor: “An active component of an electronic circuit consisting of a small block of 3 semiconducting material to which electrical contacts are made, and which may be used as an 4 amplifier, detector, or switch to control the flow of current.” 5 • 6 Doped semiconductor region: “a region of semiconductor material to which impurities are added to modify the electron or hole concentration in that semiconductor.” 7 • Gate: “an electrode region that is above the channel region” 8 • Channel region: “a region of the substrate beneath the gate defined by the space between the 9 first and second doped semiconductor regions.” United States District Court For the Northern District of California 10 11 Also, for the reasons stated above, the Court declines to construe the terms memory cell and 12 programmed doped region. And the Court declines to construe the terms the usage of which the 13 parties continue to dispute that are not listed by the parties as most significant to the resolution of this 14 case. 15 16 IT IS SO ORDERED. 17 18 Dated: August 31, 2011 SUSAN ILLSTON United States District Judge 19 20 21 22 23 24 25 26 27 28 15

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