Synopsys, Inc. v. Mentor Graphics Corporation

Filing 100

ORDER CONSTRUING CLAIMS. Signed by Judge Maxine M. Chesney on November 7, 2013. (mmclc2, COURT STAFF) (Filed on 11/7/2013)

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IN THE UNITED STATES DISTRICT COURT
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FOR THE NORTHERN DISTRICT OF CALIFORNIA

For the Northern District of California

United States District Court

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SYNOPSYS, INC.,
No. C 12-6467 MMC
Plaintiff,

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ORDER CONSTRUING CLAIMS
v.
MENTOR GRAPHICS CORPORATION,
Defendant.

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Before the Court is the parties’ dispute regarding the proper construction of eleven
terms in U.S. Patents 5,530,841 (“‘841 patent”), 5,680,318 (“‘318 patent”), 5,748,488 (“‘488
patent”), and 6,836,420 (“‘420 patent”). Plaintiff Synopsys, Inc. (“Synopsys”) and
defendant Mentor Graphics Corporation (“Mentor”) have submitted briefing and evidence in
support of their respective positions. The matter came on regularly for hearing on October
28, 2013. M. Patricia Thayer, Philip Woo, Aseem S. Gupta, Sue Wang, and Cynthia Chen
of Sidley Austin LLP and Vickie Feeman of Orrick, Herrington & Sutcliffe LLP appeared on
behalf of Synopsys. Jeffrey S. Love, John D. Vandenberg, and Andrew M. Mason of
Klarquist Sparkman, LLP and Mark E. Miller of O’Melveny & Myers LLP appeared on behalf
of Mentor.
Having considered the parties’ respective written submissions and the arguments of
counsel, the Court rules as follows.

LEGAL STANDARD

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In construing disputed claims, a district court’s primary source is the intrinsic

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evidence of the patent. See Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582-83

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(Fed. Cir. 1996). Intrinsic evidence includes “the claims, the specification and, if in

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evidence, the prosecution history,” see id., 90 F.3d at 1982, as well as the abstract, see

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Hill-Rom Co. v. Kinetic Concepts, Inc., 209 F.3d 1337, 1341 (Fed. Cir. 2000). Language

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used in the patent is given its ordinary meaning, unless it is clear that the inventor intended

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the terms to have a different meaning. See Vitronics, 90 F.3d at 1582. The patent

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specification “may act as a sort of dictionary, which explains the invention and may define

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terms used in the claims.” See Markman v. Westview Instruments, Inc., 52 F.3d 967, 979

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(Fed. Cir. 1995), aff’d, 517 U.S. 370 (1996). Although a district court considers the

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specification in determining the meaning of a disputed claim, it generally is improper to limit

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the scope of the claim to the examples set forth in the specification “absent a clear

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indication in the instrinsic record that the patentee intended the claims to be so limited.”

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See Dealertrack, Inc. v. Huber, 674 F.3d 1315, 1327 (Fed. Cir. 2012). The claims of the

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patent, not the specification, “measure the invention.” See SRI Int’l v. Matsushita Elec.

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Corp. of America, 775 F.2d 1107, 1121 (Fed. Cir. 1985). As noted, the district court also

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reviews the prosecution history, which “can often inform the meaning of the claim language

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by demonstrating how the inventor understood the invention and whether the inventor

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limited the invention in the course of prosecution, making the claim scope narrower than it

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would otherwise be.” See Phillips v. AWH Corp., 415 F.3d 1303, 1317 (Fed. Cir. 2005) (en

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banc).

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Further, in addition to intrinsic evidence, the court may consider extrinsic evidence,

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which “consists of all evidence external to the patent and prosecution history, including

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expert and inventor testimony, dictionaries, and learned treatises.” See id. Extrinsic

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evidence “can help educate the court regarding the field of the invention and can help the

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court determine what a person of ordinary skill in the art would understand claim terms to

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mean.” See id. at 1319. Nevertheless, “while extrinsic evidence can shed useful light on

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the relevant art, . . . it is less significant than the intrinsic record in determining the legally

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operative meaning of claim language.” See id. at 1317 (internal quotations and citation

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omitted).
DISCUSSION

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The four patents at issue relate generally to the field of electronic circuit design. See

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‘420 patent, col. 1:7; see also ‘841 patent, col. 1:37-40. Specifically, the ‘841 patent, the

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‘488 patent, and the ‘318 patent (collectively, the “Gregory patents”) describe “[a] method

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and system . . . for generating a logic network using a hardware independent description

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means.” See ‘841 patent, Abstract. The ‘420 patent (the “Seshadri patent”) describes “a

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method and apparatus for a resetable memory and a design approach for the same.” See

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‘420 patent, col. 1:8-10. The parties dispute the proper construction of a number of terms

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contained in the claims of the subject patents. Representative claims in which the disputed

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terms appear are as follows:

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1. A method for converting a hardware independent user description of a logic
circuit, that includes flow control statements including an IF statement and a GOTO
statement, and directive statements that define levels of logic signals, into logic
circuit hardware components comprising:

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converting the flow control statements and directive statements in the
user description for a logic signal Q into an assignment
condition AL(Q) for an asynchronous load function AL( )
and an assignment condition AD(Q) for an asynchronous
data function AD ( ); and

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generating a level sensitive latch when both said assignment condition
AL(Q) and said assignment condition AD(Q) are non-constant;
wherein said assignment condition AD(Q) is a signal on a data input
line of said flow through latch;

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said assignment condition AL(Q) is a signal on a latch gate line of
said flow through latch; and

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an output signal of said flow through latch is said logic signal Q.

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See ‘841 patent, col. 62:61-63:12 (emphasis added to designate disputed terms).
2. A method for converting a hardware independent user description of a logic
circuit, that includes flow control statements, and directive statements that define

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levels of logic signals, into logic circuit hardware components as in claim 1 [of the
‘488 patent] wherein said plurality of functions further comprises a synchronous
load function SL( ), and a synchronous data function SD( ).

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See ‘488 patent, col. 62:53-59 (emphasis added to designate disputed terms).
25. A method for generating a logic network comprising the steps of:
generating a structure having a plurality of nodes interconnected by edges
using only operational characteristics of said logic network as
input signals;
wherein each of selected edges include an edge condition; and
variables are assigned values in said nodes; and
generating a logic network using said structure and edge conditions.

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See ‘318 patent, col. 65:52-61 (emphasis added to designate disputed terms).
40. The method of claim 39 [of the ‘318 patent] wherein said logic circuit creating
step further comprises:
generating a level sensitive latch in response to predetermined assignment
conditions.

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See ‘318 patent, col. 66:64-65.
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1. A method, comprising:
a) inferring the existence of a resetable memory from a behavioral or RTL
level description of a semiconductor circuit; and
b) incorporating a resetable memory design into a design for said
semiconductor circuit.

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See ‘420 patent, col. 9:48-53 (emphasis added to designate disputed terms).
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Pursuant to Markman v. Westview Instruments, Inc., 517 U.S. 370, 384-91 (1996),
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the Court next construes the disputed claims.1

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1.

“Assignment Condition” (‘841 Patent, Claim 1; ‘488 Patent, Claims 1 and 8;

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‘318 Patent, Claims 30-32, 35, 36, 39, 40, and 42-45)
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The parties dispute the proper construction of “assignment condition” as found, for
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example, in Claim 1 of the ‘841 patent. See ‘841 patent, col. 63:1-2, 4-5, 7, and 9.
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Synopsys proposes the term be construed as “the condition under which the hardware
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description function (e.g., ‘AL’ or ‘AD’) is true for a particular variable (e.g., ‘Q’) in the user
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description.” Mentor proposes the term be construed as “a condition used to create or
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select a hardware element, by determining the logic OR of all the conditions under which a
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Where the Court has adopted a party’s proposed construction as to a term, the
adopted construction is set forth below without further discussion.
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hardware description function is true for a particular variable.”2
The Court, for the reasons stated by Synopsys, hereby construes “assignment

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condition” as “the condition under which the hardware description function is true for a

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particular variable in the user description.”3

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2.

“Predetermined Assignment Conditions” (‘318 Patent, Claims 40 and 42-45)

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The parties dispute the proper construction of “predetermined assignment

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conditions” as found, for example, in Claim 40 of the ‘318 patent. See ‘318 patent, col.

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66:64-65. Synopsys proposes the term be construed by using Synopsys’s above-

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referenced construction for “assignment condition,” along with the plain and ordinary

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meaning of “predetermined,” which, according to Synopsys, is “determined beforehand.”

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Mentor proposes the term be construed as “an assignment condition that is set in the user

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description.” At the hearing, the Court suggested the term be construed as “an assignment

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condition that is determined before the logic element is generated,” which construction was

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accepted by Synopsys.4
Accordingly, the Court, for the reasons stated by Synopsys, hereby construes

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“predetermined assignment condition” as “an assignment condition that is determined

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before the logic element is generated.”

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3.

“Asynchronous/Synchronous Data Function” (‘841 Patent, Claim 1; ‘318

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Patent, Claims 32 and 36; ‘488 Patent, Claims 1, 2, 8, and 9)

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The parties dispute the proper construction of “asynchronous/synchronous data

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The parties’ respective constructions as set forth herein are taken from their
“Revised Exhibit A to the Parties’ Joint Claim Construction Statement,” filed September 24,
2013, with the exception of Mentor’s proposed constructions for “assignment condition,”
“hardware independent user description,” “GOTO statement,” and “operational
characteristics of said logic network,” which are set forth as amended by Mentor in its
Responsive Claim Construction Brief, filed October 3, 2013.
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The Court’s construction omits the parenthetical examples, which are not contained
in the definition on which Synopsys relies, specifically the definition provided by the
applicant in the specification. See, e.g., ‘841 patent, col. 16:7-9.
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It is not clear whether Mentor likewise accepted the Court’s suggested construction
or only indicated it preferred such construction to “determined beforehand.”
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function” as found, for example, in Claim 1 of the ‘841 patent (“asynchronous”) and Claim 2

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of the ‘488 patent (“synchronous”). See ‘841 patent, col. 63:3; ‘488 patent, col. 62:58-59.

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Synopsys proposes the term be construed as “a hardware description function for data

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specifying the condition or conditions under which the variable is [asynchronously/

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synchronously] assigned a value.” Mentor proposes the term be construed as “a hardware

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description function specifying the condition or conditions under which the variable is

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[asynchronously/synchronously] assigned a logic one value.”
The Court, for the reasons stated by Synopsys, hereby construes “asynchronous/

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synchronous data function” as “a hardware description function for data specifying the

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condition or conditions under which the variable is [asynchronously/synchronously]

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assigned a value.”

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4.

“Asynchronous/Synchronous Load Function” (‘841 Patent, Claim 1; ‘318

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Patent, Claims 32 and 36; ‘488 Patent, Claims 1, 2, 8, and 9)

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The parties dispute the proper construction of “asynchronous/synchronous load

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function” as found, for example, in Claim 1 of the ‘841 patent (“asynchronous”) and Claim 2

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of the ‘488 patent (“synchronous”). See ‘841 patent, col. 63:1-2; ‘488 patent, col. 62:58.

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Synopsys proposes the term be construed as “a hardware description function for load

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specifying the condition or conditions under which the variable is [asynchronously/

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synchronously] assigned a value.” Mentor proposes the term be construed as “a hardware

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description function specifying the condition or conditions under which the variable is

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[asynchronously/synchronously] assigned a value.”

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The Court, for the reasons stated by Synopsys, hereby construes “asynchronous/

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synchronous load function” as “a hardware description function for load specifying the

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condition or conditions under which the variable is [asynchronously/synchronously]

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assigned a value.”

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“Synchronous”; “Asynchronous” (‘841 Patent, Claim 1; ‘318 Patent, Claims 32

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and 36; ‘488 Patent, Claims 1, 2, 8, and 9)

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The parties dispute the proper construction of “synchronous” and “asynchronous” as

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found, for example, in Claim 2 of the ‘488 patent (“synchronous”) and Claim 1 of the ‘841

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patent (“asynchronous”). See ‘488 patent, col. 62:58; ‘841 patent, col. 63:1, 3. Synopsys

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contends the terms should be given their plain and ordinary meanings, and that the plain

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and ordinary meaning of “synchronous” is “triggered by a timing signal” and the plain and

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ordinary meaning of “asynchronous” is “not synchronous.” Mentor proposes “synchronous”

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be construed as “occurring on a clock edge” and “asynchronous” be construed as “not

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controlled by a clock edge.”
The Court, for the reasons stated by Mentor, hereby construes “synchronous” as

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“triggered by a clock signal” and “asynchronous” as “not triggered by a clock signal.”5

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6.

“Hardware Independent User Description of a Logic Circuit” (‘841 Patent,

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Claim 1; ‘488 Patent, Claims 1, 2, 8, and 9)

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At the outset, the parties dispute whether the term “hardware independent user

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description of a logic circuit” is limiting, in that it is found only in the preambles of the

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subject claims. See Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808

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(Fed. Cir. 2002) (“In general, a preamble limits the invention if it recites essential structure

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or steps, or if it is necessary to give life, meaning, and vitality to the claim[;] [c]onversely, a

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preamble is not limiting where a patentee defines a structurally complete invention in the

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claim body and uses the preamble only to state a purpose or intended use for the

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invention.”) (internal quotations and citation omitted). Synopsys contends the term is not

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limiting. Mentor contends the term is limiting. If the term is limiting, the parties dispute its

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proper construction as found, for example, in Claim 1 of the ‘841 patent. See ‘841 patent,

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col. 62:61-62.

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At the hearing, Mentor stated it would accept “triggered by,” which prompted the
Court’s additional change from “clock edge” to “clock signal.”
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For the reasons stated by Synopsys, the Court finds “hardware independent user

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description” is not a limitation, and, accordingly, said term is not construed herein.

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“GOTO Statement” (‘841 Patent, Claim 1)
Similarly, the parties dispute whether the term “GOTO statement,” which likewise

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only appears in the preamble, is limiting and, if so, its proper construction as found in Claim

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1 of the ‘841 patent. See ‘841 patent, col. 62:63.
For the reasons stated by Synopsys, the Court finds “GOTO statement” is not a

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limitation, and, accordingly, said term is not construed herein.

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“Operational Characteristics of Said Logic Network” (‘318 Patent, Claim 25)
The parties dispute the proper construction of “operational characteristics of said

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logic network” as found in Claim 25 of the ‘318 patent. See ‘318 patent, col. 65:55-56.

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Synopsys contends the term should be given its plain and ordinary meaning, which,

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according to Synopsys, is “a user description of the desired operation of the logic network,

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independent of the specific hardware for implementing the logic network.” Mentor proposes

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the term be construed as “a user description of the desired operation of a logic circuit

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containing only signal levels in a logic network and the conditions under which those signal

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levels are generated, without describing the logical elements, design entities, components

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or other structures for implementing the logic circuit.”

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The Court, for the reasons stated by Mentor, hereby construes “operational

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characteristics of said logic network” as “a user description of the desired operation of a

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logic circuit containing only signals in a logic network and the conditions under which those

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signals are generated.”6

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“Inferring” (‘420 Patent, Claims 1, 10, 11, and 20)
The parties dispute the proper construction of “inferring” as found, for example, in

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The Court’s construction substitutes “signals” for “signal levels,” consistent with the
Summary of the Invention, on which Mentor relies, see ‘318 patent, col. 2:25-29, and the
balance of Mentor’s construction does not address what “operational characteristics” are,
but, rather, what Mentor contends they are not.
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Claim 1 of the ‘420 patent. See ‘420 patent, col. 9:49. Synopsys contends “inferring”

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should be given its plain and ordinary meaning, which, according to Synopsys, is “deducing

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[e.g., the existence of a resetable memory from a behavioral or RTL level description of a

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semiconductor circuit].” Mentor proposes the term be construed as “recognizing that a

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portion of circuit design corresponds to a specific hardware structure or class of structures.”

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The Court, for the reasons stated by Synopsys, hereby construes “inferring” in

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accordance with its plain and ordinary meaning, which is “deducing.”

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“Resetable Memory” (‘420 Patent, Claims 1-3, 10-13, and 20)
The parties dispute the proper construction of “resetable memory” as found, for

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example, in Claim 1 of the ‘420 patent. See ‘420 patent, col. 9:49. Synopsys contends

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“resetable memory” should be construed as “a memory unit with a plurality of cells, each

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cell associated with a unique address that provides access to that storage cell, where the

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memory unit can be reset to a particular value.” Mentor proposes the term be construed as

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“a unit comprising one or more storage cells that can set the read value of each storage

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cell in the unit to ‘0' in a single step.”
The Court, for the reasons stated by Synopsys, hereby construes “resetable

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memory” as “a memory unit with a plurality of cells, each cell associated with a unique

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address that provides access to that storage cell, where the memory unit can be reset to a

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particular value.”

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“Level Sensitive Latch” (‘841 Patent, Claim 1)
The parties do not dispute that Synopsys, as set forth in the prosecution history of

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the ‘841 patent, requested Claim 1 be amended to substitute “flow through latch” for “level

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sensitive latch,” and it is the Court’s understanding that both parties, at the hearing, were in

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agreement that, although the patent was issued without the requested amendment,

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acceptance thereof by the Patent and Trademark Office is ministerial in nature. Under

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such circumstances, the Court finds “level sensitive latch” as it appears in Claim 1 of the

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‘841 patent is, in actuality, “flow through latch,” a term neither party requested be

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construed. Moreover, even if a dispute exists as to the proper construction of “flow through

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latch,” the parties were limited to “a maximum of 10” terms to be construed in connection to

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the above-referenced briefing and hearing. See Patent L.R. 4-3(c).7

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IT IS SO ORDERED.

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Dated: November 7, 2013
MAXINE M. CHESNEY
United States District Judge

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Recently, on November 6, 2013, Synopsys filed a “Motion for Leave to File a
Proposed Construction for ‘Flow Through Latch,’” in which Synopsys states the parties
have not been able to agree on a construction for “flow through latch,” and submits a
proposed construction to be used “[i]f the Court decides that a construction is desirable.”
(See Motion 2.) Said motion is not addressed herein.
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