Synopsys, Inc. v. Atoptech, Inc

Filing 929

PERMANENT INJUNCTION AND DISPOSITION ORDER. Signed by Judge Maxine M. Chesney on 12/19/16. (Attachments: # 1 Appendix Part One, # 2 Appendix Part Two, # 3 Appendix Part Three, # 4 Appendix Part Four, # 5 Appendix Part Five) (mmclc2, COURT STAFF) (Filed on 12/19/2016)

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APPENDIX Part Three Trial Exhibit 1440, pages 116-167 Trial Exhibit 1441, pages 1-70 rc_receiver_model_mode rc_receiver_model_mode Specifies which receiver model type to use for RC delay calculation . Persistent parameter that controls whether the basic or the advanced CCS model is used for input pins driven by nets. I TYPE string Syntax: rc_receiver_ model mode basic advanced DEFAULT where the values have the following meaning : advanced basic Use the simplified CCS model for selected net receivers if the ccsd_auto_switch parameter is enabled ; Otherwise , use no CCS model. advanced Use the advanced CCS model for all net receivers regardless of the ccsd_auto_switch parameter setting . DESCRIPTION PrimeTime supports two types of receiver models for RC delay calculation, basic and advanced. The basic model is a single capacitance dependent only on the rise, fall, min, or max arc condition. The advanced mode l is a vo l tage-dependent capacitance additionally dependent on input-slew and output capacitance . The advanced model has many advantages, one of which is that the accuracy of both delays and slews is improved. Another advantage is that nonlinearities such as the Miller effect are addressed. The advanced receiver model is part of the Synopsys Composite CurrentSource (CCS) mode l . The default value is basic. The advanced rece iver mode l will only be used when the network is driven by the advanced driver model; please see the man page on the rc_ driver_ model_ mode shell variable for more information . When the shell variable rc _ receiver_model_ mode is set to basic, RC delay calculation will always use t he pin capacitances specified in the design libraries . When set to advanced, RC delay calculation wi l l use the advanced receiver model if data for it is present and if the network is driven by the advanced driver model. The report_ delay_ calculation command u sed on a network arc will show the message "Advanced receiver-modeling u sed " as appropriate . To de t ermine t he current va lue of this variable, enter the following command: pt_shell printvar rc_ receiver_ model mode 116 7 si_enable_analysis si_enable_analysis Enables or disables PrimeTime-SI , which provi des crosstalk analysis . TYPE Persistent parameter that controls whether to calculate the noise, and the impact of noise on timing . Syntax: Boolean si_ enable_analysi s true false DEFAULT where the values have the following meaning : false true DESCRIPTION When true, enables PrimeTime-Sl, so that the crosstalk-aware timing calculation mode is used by update_timing and report_timing. By default, PrimeTime-Si is disabled; this variable is set to false. If you set this variabl e to true and enable PrirneTime-Sl, you must also do the following: Perform a noise analysis and take the impact noise has on timing into account during timing analysis. false Ignore the effects of noise during timing analysis . The default value is false. 1 . Obtain a PrirneTime-SI license . You cannot use PrimeTime-SI without a license. 2. Use read_parasitics -keep_ capacitive_ coupling to read in the coupling parasitics for your design. PrimeTime-Sl is useful only if the design bas coupling parasitics data. For complete information about PrimeTime-SI, see the PrimeTime Signal Integrity User Guide . To determine the current value of this variable, type printvar si_ enable_ analysis . 117 8 filter_accum_aggr_noise_peak_ratio si_filter_accu m_agg r_noise_peak_ratio Specifies the threshold for the accumulated voltage bumps i ntroduced by aggressors at a victim node, divided by Vee, below which aggressor nets can be filtered out during e l ectrical filtering. TYPE float Persistent parameter that specifies the aggregated noise peak voltage threshold below which all aggressors on a net are ignored . The aggregated noise peak contains the contributions of all aggressors. The threshold is specified as a fraction of the supply voltage . Syntax: filte r_accum_aggr _ n oise_peak_ratio ratio DEFAULT 0 . 03 where ratio is the minimum aggregated noise peak value as a fraction of the supply voltage below which the noise from all aggressors on a net are ignored. DESCRIPTION Specifies the threshold for the accumulated voltage bumps introduced by aggressors at a victim node; the default is 0 . 03. This variable, a long with si_ filter_per_ aggr_ noise_peak_ ratio , makes up a pair of variables used by PrimeTimeSI during the electrical filtering phase, to determine whether an aggressor net can be filtered. The default value is 0.030. An aggressor net, along with its coupli ng capacitors , is filtered when either of the following are t r ue: 1 . The peak voltage of the vol tage bump induced on the victim net divided by Vee is less tha n the value of si_ filter_per_ aggr_ noise_peak_ ratio. 2 . The accumulated peak voltage of voltage bumps induced on the victim by a gg ressor to the victim net divided by Vee is less than the va lue of si_ filter_ accum_ aggr_ noise_peak_ ratio. To determine the current value of this variable, si_ filter_ accum_ aggr_ noise_peak_ ratio. type printvar 118 9 si_filter_per_aggr_noise_peak_ratio filter_per_aggr_noise_peak_ratio Specifies the threshold for the voltage bump introduced by an aggressor at a victim node, divided by Vee, be l ow which the aggressor net can be filtered out d u ring electr i cal filtering . Persistent parameter that specifies the noise peak voltage threshold below which an aggressor is ignored. The threshold is specified as a fraction of the supply voltage . TYPE Syntax: float DEFAULT fi l t e r_per_aggr_noise_peak_ratio ratio where ratio is the minimum noise peak value as a fraction of the supply voltage below which the noise peak is ignored. 0 . 01 The default value is 1.000e-02. DESCRIPTION Specif i es the threshold for the voltage bump introduced by an aggressor at a victim node; the default is 0 . 01. This variable, along with si_ filter_ accum_ aggr_ noise_peak_ ratio, makes up a pair of variables used by P rimeT i me - SI during the electrical filtering phase, to determine whether an aggressor net can be filtered. An aggressor net, along with its coupling capac itors , is filtered when either of the follow i ng are true : 1 . The peak voltage of the voltage bump i nduced on the victim net divided by Vee is less than the value of si_ filter_per_ aggr_ noise_peak_ ratio. 2 . The accumulated peak voltag e of voltage bumps induced on the victim by aggressors to the victim ne t d i vided by Vee is less t han the value of si_ filter_ accum_ aggr_ noise_peak_ ratio. Parasitic filtering criteria previously checked are contro l led by the variables si_ filter_per_ aggr_ xcap , si_ filter_per_ aggr_ xcap_ to_ gcap_ ratio , and fi _ filter_ single_ to_ average_ all_ xcap_ ratio . To de termi ne the current value of this vari able, type printvar si_ filter_per_ aggr_ noise_peak_ ratio . 119 10 si_noise_composite_aggr_mode noise_composite_aggr_mode Specifies the composite aggressor mode for noise analysis . TYPE String Persistent parameter that controls whether a composite aggressor is used to model the combined noise of all small aggressors, including the filtered ones, when performing noise analysis using the PTSI model. Syntax: noise_composite_aggr_mode d i sabl ed DEFAULT I normal I stat i st i ca l disabled where the values have the following meaning: DESCRIPTION disabled Do not use a composite aggressor to model the combined effect of all weak aggressors . normal Use a composite aggressor to model the combined effect of all weak aggressors and assume the worst possible aggressor alignment. statistical Use a composite aggressor to model the combined effect of all weak aggressors, and use a statistical model. Compared to the normal mode, this reduces the pessimism. This variable specifies which composite aggressor mode is used in PrimeTime SI noise ana l ysis . Al lowed values a re disabled (the default), which turns off the composite aggressor feature. normal, causes PrimeTime SI to calculate noise by uti l izing the non -sta tistical composite aggressor feature. Selecting statistical causes Pr imeTime SI to calculate noise by using t he statistical composite aggressor f low . In disabled composite aggresso r mode, PrimeT ime SI uses its original flow with composite aggressor comp le tely off to analyze the noise. In normal composite aggressor mode , PrimeTime SI aggregates the effect of mul tiple small aggressors into a single compos i te aggressor, t hereby reducing the computational complexity and improving t he performance . The default value is disabled. statistical composite aggressor mode reduces the pessimism for no i se analysis by reducing the effect of composite aggressor. For the current value of this variable, type printvar si_ noise_ composite_ aggr_ mode . 120 11 si_use_driving_cell_derate_for_delta_delay Allows crosstalk de l ta del ay for one net to be derated using the relevant derate factor for the cell drivi n g that net . TYPE si_use_driving_cell_derate_for_delta_delay Persistent parameter that controls whether crosstalk delta delay on a victim net will be derated using the same derate factor for the cell driving that net. Syntax: boolean DEFAULT s i _ u se_d r i v i n g_c ell_de r ate_ f o r _ del ta_de l ay true I f alse where the values have the following meaning : FALSE true Use the derating factor for the delay on a victim net also as a derating factor when calculating the delta delay on a victim net caused by any aggressor net. false Do not use the derating fa cto r on a victim net when calculating the delta delay that an aggressor causes on a victim net. GROUP si_variables DESCRIPTION When this variable is set to true the crosstalk de l ta delays for each net will be derated using the derate factors from the cell driving that net. The default value is false . The relevant derate factor to be appl ied will adhere to the same preceden ce r ules as the driving cell itse l f . For example, if no i n stance-specific derate factor was set o n the driving cell then the hierarchical cell, the library ce l l a n d f i nally the g l oba l derate f actors wil l be checked fo r a relevant derate fac t or. To see what derate factors a r e to be applied to the net in q u estion , first obtain the driving cell ($driving_ cel l ) and u se : pt_ shell report_ timing_ derate [get_ c e lls $driving_ cell] If the command r eport_ timing is invoked with the - derate option then the un- derated c r oss t alk delta de l ay wil l be reported as before . In addit i on the derate column will report the net derate factor used to derate the de l ta-free n et delay. To determine the current value of this variable, enter the fo l lowing comman d : pt_ she l l printvar si_use_driving_cell_derate_for_delta_delay or pt_ shell echo $si_ u s e _ driving_ cell_ derate_ for_ delta_ delay 121 12 si_xtal k_ composite_aggr_mode xtal k_com posite _aggr_mode Specifies the composite aggressor mode for crosstalk delay . Persistent parameter that controls whether a composite aggressor is used to model the combined impact of all small aggressors, including the filtered ones, when performing crosstalk delay analysis using the PTSI model. TYPE String Syntax: DEFAULT x t al k_c ornpos ite_aggr_ rnode d i sabl e d d is ab led I n o r mal s tati st i c al where the values have the following meaning: DESCRIPTION disabled This variabl e spec i fi e s which composit e aggressor mode is used in Prime Time SI c r oss t alk delay ana lysis . Allowed values are disabled (the default), wh i ch turns o ff the composite aggressor feature . normal, causes Pr imeTime SI to calcul ate crossta l k delay by utilizing the non- statistical composite aggressor feature . Se l ect i ng statistical causes PrimeTime SI to calculate crosstal k by using the statistical composi t e aggr essor flow . Do not use a composite aggressor to model the combined effect of all weak aggressors. normal Use a composite aggressor to model the combined effect of all weak aggressors and assume the worst possible aggressor alignment. In d i sabled composite aggressor mode, PrimeTime SI uses its orig i na l f l ow with composite aggressor completely of f to calcul ate the xta lk delay . statistical Use a composite aggressor to model the combined effect of all weak aggressors , and use a statistical model. Compared to the normal mode , this reduces the pessimism. I n normal composite aggressor mode, PrimeTime SI aggregates the effect of some small aggressors ( inc l uding filtered ones) i nto a single composite aggressor , thereby reducing the computational compl e xity and improving the pe r forman ce . statistical compos i te aggressor mode reduces the pessimism for xtal k delay analysis by reducing the effect of composite aggressor . For the c urrent va lue of th i s variable, The default value is disabled. type printvar si_ xtalk_ composite_ aggr_mode . 122 13 si_xtalk_composite_aggr_noise_peak_ratio Used t o control t he composi t e aggressor selection f or x t a l k analys i s . TYPE fl oat DEFAULT 0 . 01 DESCRIPTION Specifies the threshold value in crossta l k b u mp to Vdd ratio, below which aggressors are selected into composite aggressor group. The defaul t value is 0.0 1 , which means all the aggressor nets with crosstalk bump to Vdd ratio less t han 0.01 wi l l be selected i n t o compos i te aggressor group . It works together wi t h other fi l terin g thresholds si_ filter_per_ aggr_ noise_peak_ ratio and si_ filter_ accum_ aggr_ noise_peak_ ratio to determine which aggressors can be selected in t o composite aggressor group . xtalk_com posite_agg r_noise_peak_ratio Persistent parameter that specifies the noise peak threshold of an individual aggressor. If the noise peak is above the threshold , the noise impact of the aggressor is calculated individually. If the noise peak is below the threshold, the aggressor is considered weak and its noise impact is modeled by the composite aggressor. Syntax: xta lk_compos it e_aggr_n o i s e_pea k_ ra tio ratio where rati o is the threshold noise voltage as a fraction of the supply below which the impact of the aggressor is modeled as part of the composite aggressor. The default value is 1.000e-02. To de t ermine t he current value of thi s variable, t ype printvar si_ xtalk_ composite_ aggr_ noise_peak_ ratio at the PT she l l prompt . 123 14 si_xtalk_composite_aggr_quantile_high_pct xtalk_composite_aggr_quantile_high_pct Used to control the composite aggressor creation for statistical analysis . TYPE Persistent parameter that specifies the required confidence level to use for the statistical model of the composite aggressor. The value is the probability in percentage that a real noise bump will be smaller than the calculated bump. float Syntax: DEFAULT xta l k_composite_aggr_quanti l e_high_pct percentage 99.73 DESCRIPTION This variable is set to the desired probabi li ty in percentage format that any given real combined bump height will be less than or equal to the computed composite aggressor bump height. Given the desired probability, the resulting quantile value for the composite aggresso r bump height will be calculated. where percentage is the likelihood that a real bump is smaller than or equal to the calculated composite bump. The default value is 99.73%, which corresponds to a 3-sigma probability. The default value of this variable is 99.73, which corresponds to a 3 -s igrna probability that the real bump height from any randomly-chosen combination of aggressors will be covered by the composite aggressor bump height . To determine the current value of this variable, type printvar si_ xtalk_ composite_ aggr_ quantile_ high_pct at the PT shell prompt . 124 15 si_xtalk_delay_analysis_mode Specifies the arrival window a li gnment mode for crosstalk delay . xtal k_delay _analysis_mode Persistent parameter that specifies the alignment that is assumed between victim and aggressors during crosstalk delay analysis. TYPE String DEFAULT Syntax: xtal k_ delay_ analysis_mode all_paths I al l _ violating_paths \ I wor st_path a ll_pa ths where the values have the following meaning : DESCRIPTION all_paths Calculate crosstalk for all paths through the victim net. This is the most conservative approach . all_ violating_paths Calculate crosstalk only for paths with a negative slack. worst_path Calculate crosstalk only for the worst paths through the net, that is, the earliest and latest path . This var i ab l e specifies how the a l ignment between victim & aggressors is performed i n cross ta l k delay ana l ys is Pr i meTime SI. Al lowed v alues a re all_paths (the defau lt ). which causes PrimeTime SI to calculate crosstalk for all pa t hs through the vic tim net. worst_path , causes PrimeTime S I to calcula te crosstalk for all the worst paths(the e ar lies t /la test path! through the victim net . Se l ecting all_violating_paths causes PrimeTime SI to calculate crosstalk for all worst paths and p aths with the neg ative slack. I n all_paths alignment mode , PrimeTime SI con siders the largest possible c ro sstalk delta de l ay f or the given v ictim & aggresso r arrival windows . This gurantees that all p aths going throu gh the v ictim net with different arrival times are conservative . This i s de fa u lt and tradational way PTSI calculated de lta delay. The li mi ta tion of th is approach i s worst c rosstalk delta delay applied to all paths i ncluding the worst path which causes slack of the design to be pessimistic . When the path based analysis is d one on a path using get_recalcul ated_timing_paths the above pe ss imism i s removed for the specific p ath. However i t is too expensive do path based analysis ana lys i s on a ll the paths of the design . The default value is all_paths. I n worst_path al i gnment mode, PrimeTime SI aligns aggressors for the the earlist/ lates t paths on t he vict im, so only cross t alk affecting to these wors t pa th is con sidered. So only the cr os stalk affect t hat makes th e slowest (earliest ) path any slower( f aster) is calculated . If the slowest / earli est path is a se t_false_path, the t r ue pa t h is considerd . Considering the worst p a th i n stead of a ll paths, typically generates smaller delta delays and the wors t paths and the design slack becomes less pessimistic. This approach makes sure t hat design slack & worst path are conservative . There is a cav eat to worst_path a l ignment mode, the crosstalk delay is app li cabl e to worst pa t h only, so the sub-critical path de l ay may be i naccura t e. The side af f ect of this li mitation report_timing - nworst N, Nl could r eport paths with optimistic slacks. Also rep ort_ constraint - al l _ violators -max_ delay -min_delay will report less number of violations than r eally exis t on t h e design. Also as violating c r itical paths is fi xed , t he optimistic sub-critical path s will be critical and start viola t ing. Also bottleneck commands l i ke report_timing_bottleneck and report_si_bottleneck wil l be less ef fe ct ive . For some design flows the s ub- critical pa t h opt i mism is less of an iss ue if the design meets t he timing constraints, i.e. al l endp o ints in t he design show posit ive slacks. However , when the des ign has not met the t iming yet , getting conservative crosstalk deltas for a ll the violating paths (whose slack is n egative) is essential fo r the fix i ng flo w . The alignment mode all_violating_paths addre sses this by 125 aligning the aggressors for al l the violating and the worst path through any pin in the design. This means, a ll paths with negative slacks and also a ll the critica l paths thro ugh any pi n in the design (even if the slack for that worst path is posit i ve) have a co n servat i ve slack . This mode may show more pess i mi sm on worst paths than the worst_path mode and also the r untime mi ght get slightly higher t han worst_path . To reduce pessimism furth u r, in the new mode s worst_pa th a nd all_violating_path, another feature is enabled , where in the clock n / w seperate de l ay ca l culation i s 126 17 si_xtalk_exit_on_max_iteration_count Specifies a maximum number of incremen tal timing iterations, after which PrimeTime SI exits the analysis loop . TYPE xtalk_exit_on_max_iteration_count Persistent parameter that specifies the maximum number of iterations allowed between total delay calculation and crosstalk-induced delay calculation . If there is no convergence after the specified maximum number of iterations , Aprisa fa ils and issues an error. integer Syntax: DEFAULT x t al k_exit_ o n_max_ i t e r at i on_ count maxcount 2 where maxcoun t is the maximum number of iterations allowed . DESCRIPTION The default value is 2. Specifies a maximum number of incremen tal timing iterat ions . PrimeTime-SI exits the analysis loop after performing this number of iterations . The default value of this variable is 2, meaning that PrimeTime-SI exits the analysis loop after performing two iterations . You can override this default by setting the variable to another integer; the minimum allowed value is 1. This variable is one of a set of six variables that determine exit criteria; PrimeTime-SI exits the analysis loop after completing the current iteration if one or more of the following is true: 1. The number of iterations performed equals the value of the xtalk_max_ iteration_ count variable. 2. All delta delays fall between the values of the si_xtalk_ exit_ on_min_ delta_ delay and si_xtalk_ exit_ on_max_ delta_ delay variables . 3. The number of nets selected for reevaluation in the next iteration is less than t he value of t he si_xtalk_ exit_ on_number_ of_ reevaluated_ nets variable . 4. The percentage o f nets (relative to the total number of nets) selected for reeval ua tion is less than the value of the si_ xtalk_ exit _on_ reevaluated_ nets_pct variable. 5. The percentage of nets (relative to the number of cross-coupled nets) selected for reevaluation is less than the value of the si_ xtalk_ exit_ on_ coupled_ reevaluated_ nets_pct variable . 6 . You manually exit the analysis loop by p ressi ng Control-C to sen d an interrupt signal to the PrimeTime process. The interrupt is handled as any other exit criteria , at the end of the current iteration of the crosstalk analysis. You cannot i n terrupt iteration immediately without e xit ing PrimeTime . To determi ne the current val u e of this variabl e, type printvar si_ xtalk_ exit_ on_max_ iteration_ count. 127 18 si _xtal k_reselect_delta_delay Specifies the th r eshold o f net de l ay change caused by cross t a l k analysis, above which PrimeTime - SI reselects the net for subsequent delay calculations . xtalk_reselect_delta_delay TYPE Persistent parameter that specifies the threshold delta delay in ns above which the net is reselected for window filtering , provided reselection is enabled with the xtalk_reselect_delta_and_slack parameter. float Syntax: xtalk_reselec t _de l ta_delay deltaT DEFAULT where de/taT is the threshold delta delay above which the net is reselected. 5 The default value is 5.000. DESCRIPTION This var i able specifies a r ese l ection threshold in terms o f absolute delta delay. Nets that have at least on e n et arc with a crosstalk-annotated delta delay above this threshold are se l ected for the next iteration of PrimeTime -SI delay calculat i ons . Note that del t a delays are anno t ated on net arcs, but they capt ur e the change of stage delay (cell plus net) because of cross t alk . Th is variable is one of a set of fo ur variables that determine net resel ection criteria. The other three variabl es are as follows: si_ xtalk_ reselect_ delta_ delay_ ratio si_ xtalk _ reselect_ max_ mode_ slack si_ xtalk_ reselect_ min_mode_ slack All four variables are ignored if the va riable si_xtalk_ reselect_ critical_path is t r ue . To determine the current value of this variable, type printvar si_xtalk_ reselect_ delta_ delay . 128 19 xtal k_reselect_delta_delay_ratio si_xtalk_reselect_delta_delay_ratio Specifies the th reshold of the ratio of net delay change caused by crosstalk ana lys is to the total stage delay, above which PrimeTime-SI reselects a net for subsequent delay calculations . TYPE Persistent parameter that specifies the threshold delta delay as a fraction of the stage delay above which the net is reselected for window filtering , pro vided reselection is enabled with the xtalk_reselect_delta_and_slack parameter. Syntax: float x talk_reselect_delta_ de lay_ratio deltaT DEFAULT where del taT is the fraction of stage delay above which the net is reselected . 0 . 95 The default value is 0.950. DESCRIPTION This va r iable specifies a reselection threshold in terms of the delta delay ratio . Nets that have at least one net arc with a crosstalk-annotated del ta delay , where the ratio of the annotated delta to the stage delay is above this threshold, are selected for the next iteration of PrimeTime - SI delay calculations. If a net has multiple stage delays (because o f a net fanout greater than one or multiple cell arcs ) , PrimeTime-SI considers the stage delta de lay and stage delay that resul t in higher delta to stage delay ratio , thus making reselection conservative. This variable is o ne of a s et of four variables t hat determine net rese lection criteria . The other three variables are as follows : si_ xtalk_ reselect_delta_delay si_xtalk_reselect_max_mode slack s i _ xtalk_ reselect_min_mode_ slac k All fo u r variables are ignor e d if the variable si_ xtalk_ reselect_ critica l _path is true . To determine the current value of this variable, si_ xtalk_ reselect_ delta_ delay_ ratio . type printvar 129 20 si_xtalk_reselect_max_mode_slack Specifies the max mode pin slack threshold, below which PrimeTime - SI reselects a net for subsequent delay calculations . TYPE float xtalk_reselect_max_mode_slack Persistent parameter that specifies the threshold delta delay as a fraction of the stage delay above which the net is reselected for window filtering, provided reselection is enabled with the xtalk_reselect_delta_and_slack parameter. Syntax: xta l k reselect_max_mode slack setupSlack DEFAULT 0 where setupSlack is the threshold slack below which a net is reselected . DESCRIPTION The default value is 0.000. This variabl e specifies the pin s l ack t h reshold in the max mode. Nets that have at leas t one pin with a max mode slack below this threshol d are selected for the next iteration o f PrimeTime-SI delay cal cul ations. Max-mode pin sl a ck is the slack of t he worst max- mode (setup) path through the pin. This variable is one of a set of four variabl es that de t ermi ne ne t reselection criteria. The other three variables are as follows: si_xtalk_r ese l ect_ delta_delay si_xtalk_rese l ect_delta_delay_ratio si_xtalk_ reselect_ min_ mode_ slack All four variables are ignored if the variabl e si_xtalk_ reselect_ c ritical_path is true. To determine the current value of this variable, type p rintvar si_ x talk_ reselect_max_ mode_ slack . 130 21 si_xtalk_reselect_min_mode_slack Specifies t he mi n mod e pi n s l ack t h reshold , below which Pr imeTime - S I reselects a net for s u bsequent delay calculat ion s . TYPE float xtalk_reselect_min mode slack Persistent parameter that specifies the threshold delta delay as a fraction of the stage delay above wh ich the net is reselected for window filtering, provided reselection is enabled with the xtalk._reselect_delta_and_slack parameter. Syntax: xtalk_reselect_min_rnode s l ack holdSlack DEFAULT 0 where holdslack is the threshold slack below which a net is reselected . DESCRIPTION The default value is 0.000. This var i a ble specifies the pin slack thres h old i n the min mode. Nets that have at l east one pin with a min mode slack be l ow thi s threshold are selected for the next iteration of PrimeTime-SI delay calculat ions. Min - mode pin slack is t he slack of the worst mi n -mo d e (ho l d) pa t h through the pin. This var i ab le is one of a set of four variabl es t ha t de t ermine net reselection criteria . The other t hree variables are as f ollows: si_ xtalk_ reaelect_ delta_ delay si_ xtalk_ reaelect_ delta_ delay_ ratio si_ xtalk_ reselect_max_ mode_ slack All four variables are ignored if the variable si_ xtalk_ reselect _ critical_path is true. To determine the current value of this variable, type printvar si_ xtalk_ reselect_ min_ mode_ slack. 131 22 timing_aocvm_enable_analysis timing_aocvm_enable_analysis Enable PrimeTime's graph-based AOCVM analysis . Persistent parameter that controls whether to enable advanced on-chip variation analysis. This advanced analysis uses knowledge about geographical distance and logic depth to better calculate the impact of systematic and random variations within one chip. TYPE Boolean DEFAULT false GROUP Use the read_aocvm Tel command to specify the two-dimensional distance- and logic-depth-dependent derating models. Use the set_ timing_ derate -aocvm_guardband Tel command to specify an additional guardband derating factor to use for either early or late paths. timing_variables Use the timing_aocvm_ana/ysis_mode Tel variable to control how to combine these early and late guard bands with the advanced OCV derating factor. DESCRIPTION • When false (default) the graph-based AOCVM timing update is not performed . A pathbased aocvm analysis can be performed in this mode using the -pba_mode option on the report_ timing and get_ timing_paths commands. In this mode constant timing derates specified u sing the set_ timing_ derate command are required to pessimistically bound the analysis. You should specify constant derates that do not clip the range of the path-based AOCVM derates to avoid optimism. If this variable is not set, then these derating factors are considered independent, and the total effect of these derating factors is the square root of the sum of the squares of the effects of derating. • If the variable is set with the value correlated_components, then the derating factors are considered fully correlated and the total effect of deration is the sum of the effects of each derating factor. When true the graph-based aocvm timing update is performed as part of the update_ timing command . A path-based aocvm analysis can also be performed in this mode . In this mode constant timing derates are not required and, in Eact, constant derates for static delays are ignored . Graph- based AOCVM derates computed during update_ timing tightly bound the path - based AOCVM derates withou t clipping their range . Note that setting this variable to true will automatically switch the design into on_ chip_ variation analysis mode using the set_ operating_ conditions command. Use the report_timing Tel command with the -aocvm argument to see the resulting derating factors that were applied to net and cell delay models in the reported timing paths. Syntax: timing_ aocvm_ e nable_ analysis true I false where the values have the following meaning : true Enable advanced on-chip variation analysis. false Disable advanced on-chip variation analysis . The default value is false. 132 23 timing_clock_reconvergence_pessimism Select signal transition sense matching for comput ing clock reconvergence pessimism removal . timing_clock_reconvergence_pessimism Persistent parameter that controls the clock transitions that are used to reduce reconvergence pessimism. TYPE Syntax: string DEFAULT timi ng_ c l ock_reconv ergence_pessimi sm \ normal I same_transition normal where the values have the following meaning: DESCRIPTION normal Determines h ow the value o f t h e clock reconvergence pessimism removal (crpr ) is computed with r espect to transition sense. Allowed values are normal (the defau l t) and same_transition. Use both same and inverse transition conditions to reduce reconvergence pessimism . same_transition Only use same transition conditions to reduce reconvergence pessimism. When set to normal, t he crpr value is computed even if the clock transitions to the source and desti na t i on la t ches are in different d irect i o n s on the common clock path . It is computed separately for rise and f a l l transition s and the value with smaller absol u te va l ue is used. The default value is normal. W hen set to same_ transition , t h e crpr value is computed only when the clock tran sit i o n to the sou rce and d estination latch es have a common path and the t ransi t ion is in t h e same d irection on each pin of the common pa th. Thus if the source and dest i nat i on la tches are tr i ggered by differen t e dge types, crpr has a value of zero . To determine the current value of t h is variable, t ype printvar timing_ clock_ reconvergence_pessimism or echo $timing_ clock_ reconvergence_pessimdsm . 133 24 timing_crpr_remove_clock_to_ data_ crp timing_crpr_remove_clock_to_data_crp Al lows the removal of Clock Reconvergence Pessimism (CRP) from paths that fan out directly from clock source to the data pin s of sequential devices . Persistent parameter that controls whether to remove Clock-to-data Reconvergence Pessimism (CRP) during timing analysis . TYPE By default, arrival time uncertainty of the clock signal and data signal are handled independent of each other. This approach may be overly pessimistic for cases where the clock path and data path share some logic. To reduce that pessimism , and to obtain a more accurate analysis , you may want to enable this parameter. boolean DEFAULT Syntax: FALSE timing_crpr_remove_clock_to_data_crp true DESCRIPTION I false where the values have the following meaning: When this variable is set to true then CRP will be removed for all paths that fan out directly from clock source pins to the data pins of sequential devices. true It should be noted that when this var i able is set to true all sequential devices that reside in the fanout of clock source pins must be handled seperately in the s ubsequen t timing update . This may cause a severe performance degradation t o the timing update . Remove clock-to-data CRP. This setting causes Aprisa to consume a lot more memory, and to run for a much longer time. false Do not remove clock-to-data CRP. This is much more efficient, but may be overly pessimistic. pt_ shel l echo $timing_ crpr_remove_ clock_to_data_ crp or pt_ shel l printvar timing_crpr_remove_clock_to_data_crp The default value is false. 134 25 timing_crpr_threshold_ps Specifies amount of pessimism that clock reconve rgence pessimism removal (CRPR) allowed to leave in the report . timing_crpr_threshold_ps is TYPE Persistent parameter that specifies the amount of pessimism that clock reconvergence pessimism removal (CRPR) is allowed to leave in the report . So, th is parameter effectively controls how much effort CRPR should spend on a reconvergent path. float Syntax: DEFAULT timing_crpr_ threshold_ps threshold 20 DESCRIPTION Specif i es amount of pessimism t hat clock reconvergence pessimism removal (CRPR) is a llowed to leave in the report. The unit is in picoseconds (ps), regardless of the units of t he main library. where threshold is a rea l number greater than 1.0, defining the maximum amount of pessimism that can be left in a reconvergent path after CRPR. The default value is 20.000. The threshold is per reported slack : setting the this variable to the TH1 value means that reported slack is no worse t han S- THl, where Sis the reported slack when timing_ crpr_ threshold_ps is set close to zero (the minimum allowed value is 1 p i cosecond) . The variable has no effect if CRPR is not active (timing_ remove_ clock_ reconvergence_pessimism is false) . The larger the value of timing_ crpr_ threshold_ps , the faster the runtime when CRPR is active . The recommended setting is about one half o f the stage (gate plus net) delay of a typ i ca l stage in the clock network. It provides a reasonable trade-of f between acc u racy and runtime in most cases. You may want to use different set tings throughout the design cycle : l arger during the des ign phase, smaller for sign-off . You mi ght have to experiment and set a d i fferent value when moving to a diffe ren t technology . To determine the current value of this variable, type printvar timing_ crpr_ threshold_ps . 135 26 timing_disable_bus_contention_check Disable checking for timing v io lation s resulting from trans ien t co ntention on design b u sses . timing_disable_bus_contention_check Persistent parameter that controls whether the timing analyzer should perform bus contention checks. TYPE Syntax: Boolean timing _d i s a bl e_b u s _c ontenti on_check true DEFAULT f a lse where the values have the following meaning : false true Do not perform bus contention checks. false Perform bus contention checks. DESCRIPTION Appl i es only to bus design s that h ave mul t i ple three-sta te drivers . When true, PrimeTime ign ores timing setup and hold (ma x a n d min ) vio l ations tha t occur as a result of transient bus contention. When false (the defau lt), P r i me Time reports these timing vio la tion s . The default value is false. Bus contention occurs when more than one driver is enabled at the same time . By defau lt , PrimeTime treats the bus as if it is in an unkn oom state duri n g this region o f cont e n tion , and reports a timi ng violation if the setup and ho l d regions extend i n to the contention region. No t e that checkin g is done only for t imi ng violations, and n ot for logical a nd excessive power dissi p ation violations, which a r e outside the scope of static timing analysis tools. Set this variable to true only if you are certain that tra nsient bus c on tent ion r eg ions wi ll neve r occur. By setting the value to true, you guarantee that on a mu lt i -driven three -st ate bu s , the drivers in the previous clock cycle a r e disa bled before the drivers in the current clock cycle are enabled. If you set this var iabl e to true, you must ensure that the variable timing_ disable_ bus_contention_ check is false . The variables timing_ disable_ bus_ contention_check and timing_disable_ floating_ bus_ check cann ot b oth be true at the same time . During t he swit ching between the hi gh-impedan ce (Z) s t ate a n d the high/low state, the timing behavior ( for example, in tr in sic delay) o f three - state buffers is captured in the Synopsys library using the timing arc types th ree_sta t e_disable and three_ state_ enable . These timing arcs connect the e n able pin t o the output pin of the three-state buff ers . For detai l s, see the Library Compiler Referen ce Manual. To determine the current value of th is var i able, type printvar timing_disable_bus_contention_checks or echo $timing_disable_bus_contention_checks. 136 27 timing_disable_clock_gating_checks timing_disable_clock_gating_checks Disable checking for setup and hold clock gating violations. TYPE Boolean Persistent parameter that controls whether to perform clock-gating setup and hold checks. Syntax: timing_disable_clock_gating_checks true I false DEFAULT where the values have the following meaning : fa l se true Do not perform clock gating setup and hold checks. false Perform clock gating setup and hold checks . DESCRIPTION When true, disables clock - gating setup and hold checks. W hen false (the defa u lt), PrimeTime automatical l y determines clock-gating and performs clock - gating setup and hold chec k s. The default value is false. To determine the curr ent value o f this variabl e, t ype printvar timing_ disable_ clock_ gating_ checks or echo $timing_ disable _clock_ gating_ checks. 137 28 timing_disable_cond_default_arcs timing_disable_cond_default_arcs Disa bl e the de faul t, n on-conditiona l t iming arc between pins t hat do have conditional arcs. Persistent parameter that controls whether the default condition of any conditional timing arc should be ignored . TYPE Syntax: Boolean timing_disable_cond_defau l t _arcs true I fa l se DEFAULT where the values have the following meaning: false true Do not examine the default condition of conditional timing arcs. false Do consider the default condition as any other condition of conditional timing arcs . DESCRIPTION When true, disab l es noncondi tional t i ming arcs between any pair of pins that have at least one conditional arc . When false (the d efault), t hese n oncondi t ional timi ng arcs are not disabled. This variable is primarily intended to deal with the s ituat ion between two pins that have conditiona l arcs, where t here is always a default timi ng arc with no condition. The default value is false . Set this variable to true when the specified conditions cover all possible statedependent delays , so that the default arc is use l ess. For example , consider a 2inpu t XOR gate with inputs as A and 8 and with output as Z. IE the delays between A and Z are specified with 2 arcs with respective c ond i tions '8' and '8- ", t he default arc between A and Z is useless and shou ld be disabled. To determine the current value oE th i s variable, type printvar timing_disa~le_cond_default_ arcs or echo $timing_disa~le_cond_default _arcs . 138 29 timing_disable_floating_bus_check timing_disable_floating_bus_check Disable che cking for timing violations resulting from transient floati ng design buses. Persistent parameter that controls whether to check for floating busses . TYPE Syntax: timing_disab l e_floating_bus_check true Boolean DEFAULT where the va lues have the following meaning : false true Do not check for floating busses . DESCRIPTION false Check for floating busses. Applies only to bus designs that have multiple three-state drivers. false The default value is false . When true, PrimeTime ignores timing setup and hold (max and min) violations that occur as a result of transient floating buses. When false ( the default), PrimeTime reports these timing vio l ations. Floating bus condition occurs when no driver controls the bus at a given time . By default, PrimeTime treats the bus as if it is i n an unkno'm state during this region of contention , and reports a timing violation if the se t up and ho l d regions extend i nto the floating region. Note tha t checking is done only for timing violations, and not for logi cal violations, which are outside the scope o f static timi ng analysis tools. Set this va l ue to true only if you are certain that transient floating bus regions will never occur . By setting the value to true, you guarantee that on a multi - driven three- state bus, the drivers in the previou s clock cycle are disabled before the new drivers i n the current c l ock cycle are enabled. If you set this variable to true, you must ensure that the variable timing_ disable_ bus_ contention_ check is false . The variables timing_ disable_ floating_ bus_ check and timing_ disable_ bus_ contention_ check cannot both be true at the same time. Du ring the switching between the high-impedance (Z) sta t e and the high/low state, the timing behavior (for example, intrinsic delay) of three - state buffers is captured in the Synopsys library using the timing arc types three_state_disable and three_state_enable. These timing arcs connect the enable p i n t o the output pin of the three - state buffers . For details, see the Library Compiler Reference Manual. To determine the current value of this variable, type printvar timing_disable_floating_bus_check or echo $timing_disable_floating_bus_check. 139 30 timing_disable_internal_inout_cell_paths timing_disable_internal_inout_cell_paths Enable bidirectiona l fe edback pa ths within a cell . Persistent parameter that controls whether to analyze feedback paths inside a cell through a bidirectional pin of that cell. TYPE Syntax: Boolean DEFAULT true timing_ d i sable_ internal_i nout_ cell_paths true I false where the values have the following meaning : true Do not analyze timing paths inside a cell through a bidirectional pin of that cell. false Also analyze timing paths inside a cell through a bidirectional pin of that cell. DESCRIPTION When true (the default), PrimeTime automat ically disables bidirec t iona l feedback pa ths i n a c ell . W hen false, bidi rectional feedback paths i n cells are enabled . This variable has no effect on t i mi ng of bidirec t iona l feedback pa th s that involve more t han one cell (that is, i f nets are involved) ; t hese feedbac k paths are controlled by the variable timing_disable_ internal _ inout _net_arcs. The default value is true. To de t ermine the current value of this variabl e, type printvar timing_disable_ internal_ inout_cell_paths or echo $timing_disable_ internal_ inout_ce1l_paths . 140 31 timing_disable_internal_inout_net_arcs timing_disable_internal_inout_net_arcs Controls whether bidirectiona l feedback paths across nets are disabled or not. TYPE Boolean Persistent parameter that controls whether to analyze feedback paths through a bidirectional pin. Syntax: timing_ d i sab l e_int ernal_inou t _ net_ arc s tru e DEFAULT I f al se true where the values have the following meaning : DESCRIPTION true Ignore feedback paths through bidirectional pins. false Analyze feedback paths through bidirectional pins. When true (the default), PrimeTime automatically disables bidirectional feedback paths that i nvo l ve more than one ce ll ; no path segmentation is required . When false , these b idirectional feedback paths are enabled. This variable has no effect on timing of bidirectiona l feedback paths that are completely contained in one cel l (tha t is, if nets are not involved ) i these feedback pa t hs are controlled by the variable timing_ disable_ internal_ inout _ cell_paths. The default value is false . To determi ne the current value o f this variable, type printvar timing_ disable_ internal_ inout_ net_ arcs or echo $t~ing_disable_ internal _ inout_net _arcs. 141 32 timing_disable_recovery_removal_checks timing_disable_recovery_removal_checks Di sab l e or enable the t i mi ng analysis o f r ecover y and r emoval checks i n the design. TYPE Persistent parameter that controls whether to perform recovery and removal timing checks. Recovery and removal checks are similar to setup and hold checks , but are intended for asynchronous signals, such as set and reset signals . Boolean Syntax: DEFAULT timing_disable_ recovery_ removal_ checks t rue I false false where the values have the following meaning: DESCRIPTION When true, disables recovery and removal timing analysis. When false (the default ) , PrimeTime performs recovery and r emoval checks; for descriptions of these checks, see the man page for the report_ constraint command . true Do not perform recovery and removal checks. false Perform recovery and removal checks . To determine the current va l ue o f th is var iabl e, type printvar timing_ disab l e _ recovery_ removal_ checks or echo The default value is false. $timing_disable_recovery_removal_checks . 142 33 timing_early_launch_at_borrowing_latches Removes clock l a tency pess i mism from the launch times for pa ths which beg i n a t the data pins of transparent latches . timing_early_launch_at_borrowing_latches Persistent pa rameter that controls the clock latency to use for latches in paths requ iring time borrowing . TYPE Boolean Syntax: timing_ early_ launch_ at_ borrowing_ latches true f a l se DEFAULT true DESCRIPTION I n the foll owing descri p tio n we a ssume that t he data paths of interest ar e setup paths since we refer specifical ly to time borrowing scenarios . However, i f timing_ allow_ short_path_ borrowing is enabled then the same discussion applies to borrowing hold paths too . where the values have the following meaning : true Use the early clock latency for the latch cell. false Use the late clock latency for the latch cell. The default valu e is true. W hen a latch is i n it s tra nspa r en t phase, da t a arr i ving at the 0-pin passes through the element as though i t were combinational . To model this scenario, whenever Pri meTime determines that time borrowing occ urs a t such a 0-pin, paths which originate at the 0 -pin are created. Sometimes there i s a dif fe renc e between the launching and cap t u ri n g latch latenc i es, due either to reconvergent paths in the clock network or different min and max delays of cells i n the clock networ k. For setup paths, Pr i meTime uses the late value to launch and the early va l ue to capture. This achieves the tightest constraint and avoids o ptimism. However, f or paths star ting from l atch 0-pins t hi s is pessimistic since data simply passes t hrough and thus does not even "see " the cloc k edg e at the latch. W hen this timing variable is se t t o true (the default), such pessimism is e liminate d by us i ng the early l atch l a t ency to l aunch s uc h paths. Note that onl y pa ths whi ch originate from a latch 0 - pin are affected . When the variab l e i s se t to false, late clock latency is used to launch a l l setup pa t hs in the design . It is recommended that the user avai l o f this form of p essimism removal since it does not cause the run-time o f the anal y si s t o i nc rea se . However, it is also advised that the user disab le i t when c l ock reconvergence pessimism removal (CRPR) is enabled (i . e. when timing_ remove_ clock_ reconvergence_pessimism is true). CRP R may no t be appl i ed to paths which have been launched using an ear l y latency or t h e resu lts may be optimistic . Since CRPR is a more sophisticated and accurate means o f pessimism r emoval, the user should disable timing_ early_ launch_ at_ borrowing_ latches when CRPR is enabled so t ha t CRPR applies to all paths in the design. In this mode, note tha t the 0 - pin l aunc h time is not modif i ed by t he open edge CRP - s i nce late launch la t ency is used a t the path startpoin t , to additionally add CRP would be pessimistic, represent i ng a "doub l e-counting " of early- l ate differences. To de t ermine the current v a l ue of thi s variable, type printvar timing_ early_ launch_ at_ borrowing_ latches or echo $timing_ early_ launch_ at_ borrowing_ latches . 143 34 timing_enable_preset_clear_arcs timing_enable_preset_clear_arcs Controls whethe r PrimeTime enables or disables preset and clear arcs . TYPE Boolean Persistent parameter that controls whether to ana lyze preset and clear timing constraints. Syntax: t iming_enabl e_preset_clear_arcs tr u e DEFAULT false DESCRIPTION When true, permanently enables asynchronous preset and clear timing arcs , so that you u se t hem to analyze timing paths. When false (the default), PrirneT ime disables a ll preset and clear t iming arcs . J fa l s e where the values have the fo llowing meaning : true Take into account preset and clear timing constraints. false Ignore preset and clear timing constra ints . The default value is false . Note that if there are a n y mini mum pu ls e width checks defined on asynchronous preset and clear pins they are performed regardless of the val ue of this variable. Also no t e the the -true and the -justify options of report_timing cannot be us ed unless this variable is at its default va l ue . To determine t he current value of this var iable, type printvar t iming_ enable_preset_ clear_ arcs . 144 35 ti ming_i n put_port_ d efau It_ clock Determines whether a defaul t clock is assumed at input ports for which the user has not defined a clock with set_ input_ delay. TYPE timing_input_port_default_clock Persistent parameter that controls whether to assign a default clock. to an input port if no input delay is specified on that port . Syntax: Boolean DEFAULT true DESCRIPTION This Boo lean variable affects t he behavior of PrirneTime when t he user sets an input delay without a clock on an input port. When true (the default va l ue), the input delay on th e port is set wi th respect to one imaginary clock so that the inputs are constrained. Thi s a l so causes the clocks along the pa ths driven by these input ports to become r elated. When false, no such imaginary clock is assumed. timing_ input_port_de f aul t_c l ock true I false where the values have the following meaning : true Assign a default clock. if no input delay is specified. false Do not assign a default clock. if no input delay is specified. The default value is false. To determine the current va l ue of this variable , type printvar timing_ input_port_ default_ clock . 145 36 timing_remove_clock_reconvergence_pessimism timing_remove_clock_reconvergence_pessimism Enables or disables clock reconve rgence pessimism remova l Persistent parameter that controls whether the timing analyzer will remove clock reconvergence pessimism. This pessimism arises in the default timing analysis when , in presence of on-chip-variation (OCV) and reconvergent clocks , overly conservative clock skew is calcu lated because one clock path uses minimum delay and another path uses maximum delay for the same cell. This pessimism can be removed but at a significant run time penalty. TYPE Boolean DEFAULT false Syntax: timing_ r e move_ clock_ recon vergence_pessimi sm true DESCRIPTION When this variable is set to true, PrimeTirne removes clock reconvergence pessimism from slack calcu lation and minimum pulse width checks. This variable replaces the following discontinued options : false where the values have the following meaning : true of the report _timing ~ report _ constraint , Remove clock reconvergence pessimism. false -report_ clock_ reconvergence_pessimism -remove_ c1ock_ reconvergence_pes simism Do not remove clock reconvergence pessimism. and get _ timing_p aths commands . C l ock reconvergence pessimism ( CRP) is a difference i n delay along the common part of the launching and capturing clock paths . T he most common causes of CRP are reconvergent paths in the clock network, and different min and ma x delay of cells in the clock network. The defauH value is false . CRP is independently calculated for rise and fal l clock paths . You can use the variable t~ing_c1ock_reconvergence_pessimism to contro l CRP calcu lat ion with res pect t o transition sen se. I n the case of the capturin g device being a levelsensi t ive latch two CRP values wil l be cacula ted: • crp_ open , which is the CRP correspon ding to t he openin g edge of the latch • crp_close , which is the CRP corres ponding to the closing edge of the latch The required time at the latch wi l l be increased by the val u e of crp_ open and hence reduce the amount of borrowing (if any) at the latch . Meanwhile, the maximum time borrow a l lowed at the latch is affected by shifting t h e closing edge by crp_close . For more details , see the PrimeTime User Guide : Fundamentals. For a more detailed descrip t ion of a CRP calulation, use the report_ crpr command. CRP is calculated differently for minimum pulse-width checks. It i s given as the min i mum of (maximum rise arrival time - minimum rise arriva l time) a n d (maximum fall arrival time ~ minimum fall arrival time ) at the pin where the check is being made . If the variable si_enab1e analysis is set t o true delays i n the clock network may a l so inc l ude delta delays result ing from crossta l k interaction. Such delays are dynamic in nature, that i s, they may vary from o n e clock c y cle to the n ext, causin g d i fferent de l ay variations (either speed - up or s l ow- down) on the same network, but dur ing d if ferent clock cycles . Starting with U-2003 _03 releas e PrimeT ime o n ly con side rs SI delta delays as par t of the CRP ca l cu lation if the type of timing check deployed de rives its da ta from t he same clock cycle. In transparent- la tch b ased designs , i t is recommended t h at the variable should be set to false when CRP removal (CRPR) is enabled_ I n t hi s case, CRPR will apply even to pa t hs whose startpoints are bo rr owing , leading to better pessimism reduction overall. timing_ ear~y- ~aunch_at _borrowing_ ~atches Any effective change in the value of the timing_remove _c~ock_reconvergence_pessimism variable causes ful l u pda te_ t i ming . You cannot p er f orm one repor t _ timing ope r at ion that considers CRP and one that does not without full update_timing in between. 146 For bac kwa rd compatibility, the discontinued options will app ear for the first few releases after they are obsole ted . However, if the design i s not u p to date at t he time they are executed , they wil l only set timing _remove_c l ock_reconve r gen ce_pess i mism to true If the design is up to date, then t he comma n d with t he discon tinue d option fails . Since the discontin u ed command options on ly set timing_rernove_clock_reconvergence_pessimism to true , the report_ c1ock_ reconvergence_pessimism option b ehavior is not backward compa t ible . I t causes slack to be removed pr io r t o s elect i ng the worst path In other words, i t behaves the same as the d iscon ti nu ed -remov e _ c1ock_ recon ver gance_pessimism option of the report _ timing , reyport_ constraint , and get_ timing_paths commands . As soon as possible , update your scripts t o set the timing_remove_c~ock_reconvergence_pessimism v ar iable to true instead of usi ng the disco n tinued options . L imita Lions : CRPR does not sup port pa t hs Lhat f a n ouL directly from c l ock so ur ce pins to the data pins of sequentia l devices. To enable support for such paths the variable t~ing_crpr_remove _c1ock_ to_data_crp must b e set to TRUE . CRPR does not s upport ideal clock l a tency set o n pins or ports. CRPR does not s u pport propaga ted clocks set on pin s or por ts as opposed to clock o bj ects . To turn CRP removal on : pt_ shel l set tim1ng_ remove_ c1ock_ reconvergence_pessimism TRUE TRUE pt_ shell report _ timing 147 38 si_noise_nmos_threshold_ratio Specifies the technology threshold voltage for NMOS devices divided by the Vee . set_param sil noise_nmos_threshold_ratio 0.200 Type float Usage NMOS threshold for SI noise analysis # # TYPE float DEFAULT 0.2 DESCRIPTION Specifies the technology threshold voltage for NMOS devices divided by Vee; the default i s 0.2. This va r iable, along with si_ noise_pmos _ threshold_ r a tio , makes up a pa ir of variables used by PrimeTime-SI during the noise analysis phase, to determine the steady state resistance value of the d rivers in absence of a noise library. When noise libr ary is not present for a ce l l or for a design, this activates the PrimeTirne-SI steady state resistance es timation mode. In this mode, steady state resistance gets estimated based on the value of t he PMOS and NMOS threshold voltage val ues as wel l as other information extracted from the delay and slew t ables. 148 39 si_noise_pmos_threshold_ratio Specifies the t echnology threshold voltage for PMOS devices divided by t he Vee. set_param sil noise_pmos_threshold_ratio 0.200 Type float Usage PMOS threshold for SI noise analysis # # TYPE float DEFAULT 0.2 DESCRIPTION Specifies the technology threshold voltage for PMOS devices divided by Vee ; the default is 0.2. Th is variable, a l ong with si_ noise_ nmos_ threshold_ ratio , makes up a pair of variables used by PrimeTime-SI during the noise analysis phase, to determine the steady state resistance value of the drivers in absence of a noise library . When noise l ibrary is not present for a cell or for a design, this activa t es the PrimeTime-SI s t eady state resistance estimation mode . In this mode, steady state resistance g ets estimated based on the value of the PMOS and NMOS th reshold vol t age values as well as other information extracted from the delay and s l ew tables . 149 40 si_xtalk_analysis_effort_level Specifies the level o f ef fo rt for the PrimeTime-SI timing calcu l at i on mode . set_param sil xtalk_analysis_effort_level high # Values: low high # Usage : ptsi xtalk analysis effort level TYPE s tring DEFAULT medium DESCRIPTION Specifies the effort level for the PrimeTime - SI timing calculation mode . Allowed val u es a r e low , medium (the default) and h i gh. In the h igh e ffo rt mode , the most accurate crosstalk delay ca lcu l ation is performed, wh i ch results in the highest run time. In the rne dium ef f or t mode, effic i e nt heu ristics ar e empl oyed i n c ertai n situat ions to enable faste r ca l culation of cross tal k delay . This can result in slightly pe s s imisti c res u lts . I n the low effor t mode , the f astest cros s t alk de l ay calculation is performed, which re s u lts i n the smal l est run time . To determine the current val ue of this var i able, si_ xtalk_analysis_ effort_ level . type printvar 150 41 si_xtalk_exit_on_coupled_reevaluated_nets_pct Specifies a maximum percentage of nets selected for reevaluation relat i ve to the total number of coupl ed nets, bel ow whi ch PrimeTime- SI exits t he ana l ysis loop. set_param sil xtalk_exit_on_coupled_reevaluated_nets_pct 0 .000 Type : float Usage # # TYPE floa t DEFAULT 0 DESCRIPTION Specifies a maximum percentage of nets selected for reevaluation relat i ve t o the total number of coupl ed nets . PrimeTime-SI exits the analysis loop after completing the current iteration, when the percentage of nets sel ected for reevaluation in the next iter ation is l ess than this number . The number of coupled nets is based on detailed parasitics as r ead in by read_parasitics . That is, cross t alk fil t ering does no t impact the count of coupled ne t s for t he purpose o f t his variable. The number of coupled nets counts al l i ndividual net segments in the same way that [get_nets h i erarch ical *] counts all nets i n the design. This variable is one of a set of si x variables t hat determine exi t criteria; PrirneTime-SI exits the analysis loop after completing the current iteration if one or more of t he fo l lowi ng is t rue : 1 . The number of i terations performed equa l s the value of the xtalk_max_ iteration_count var iabl e. 2 . All delta del ays fall between the va lues of t he si_xtalk_exit_on_min_delta_delay and si_xtalk_exit_on_max_delta_delay variables. 3 . The number of ne ts selec t ed for reevaluation i n the next iteration is less than the value of the si_xtal k_exit_on_number_of_reevaluated_nets variable. the analysis loop . 4 . The percentage of nets (relative to the tota l number of ne t s) selected for reeva l uation is les s than the value of the s i _xtalk_exi t _on_r eevaluated_nets_pct variable. 5 . The per centage of nets (relative to the number of cross - coupled nets ) selected f or reevalua tion is less than the value of the si_xtalk_exit_on_coupled_reevaluated_nets_pct vari able . 6 . You manually exit the analysis loop by press i ng Control - C to send an interrupt signal to the PrimeTime process . The interrupt is handled as any other exit criteria, a t the end of the curren t iteration of the crosstal k ana l ysis . You cannot interrupt i t er a t ion immediately without exi ting PrimeTime . To determine the current value of this variable, type printvar si_xtalk_exit_on_coupled_reevaluated_nets_pct . 151 42 si_xtalk_exit_on_number_of_reevaluated_nets Specifies a maximum numbe r o f ne ts sel ected for reevaluation, below which Pr i meT imeSI exits the ana l ys i s loop . set_param sil xtalk_exit_on_number_of_reevaluated_nets 0 Type : uint Usage # # TYPE integer DEFAULT 0 DESCRIPTION Specifies a max imum number of n ets selected for reevalua t ion. Pr irneTime - SI exits the analysis loop after completing the current itera tio n, when the number of n ets selected for reevaluation in the the next i teratio n is less than this number . Thi s variabl e i s one of a set of six variabl es that de term i ne ex i t cr iteria ; P rimeTime-SI exits the analysis l oop after completi n g the current iteration if one or more of t he following is true : 1 . The number of i te rations performed equals the value of the xtalk_ max_ iteration_ count variabl e . 2. All delta delays fall b e t ween the values of the si_ xtalk_ exit_ on_ min_ de l ta_ delay and si_ xtalk_ exit_ on_ max_ delta_delay variables . 3 . The number of nets selected for reevaluation in the next iteration is l ess than the value of the si_ xtalk_ exit_ on_ number_ of_ reevaluated_ nets variable. 4. The percentage of nets (relat i ve to the total number of net s) selec ted f or reeva luation is l ess t han the value of the si_ xtalk_ exit_ on_ reevaluated_ nets_pct variable. 5. The pe rcentag e of n ets (relative to the number of cross-coup l ed net s) selected for reeval ua t ion is less than t he v alue of the si_ xtalk_ exit_ on_ coupled_ reevaluated_ nets_pct variab l e. 6. You manually exit the ana l ysis l oop by pressing Con trol- C t o send an interrupt s i gnal to the PrimeTi1 process. The interr upt is handl ed as any othe r exit ne criteria , at the end o f the current iteration of t he crosstalk analys is. You cannot i n terrupt iteration immediate l y withou t exiting PrimeTirne . To determine the current val ue o f this variable, si_ xtalk_ exit_ on_ number_ of_ reevaluated_ nets . type printvar 152 43 si_xtalk_exit_on_reevaluated_nets_pct Specifies a maximum percentage of nets selected for reeval uation relative to the total number o f nets, below which PrimeTime - SI exits t he ana l ysis loop . set_param sil xtalk_exit_on_reevaluated_nets_pct 0.000 Type : float Usage # # TYPE floa t DEFAULT 0 DESCRIPTION Specifies a maximum percentage of net s reselected for evaluation, relative t o the total number of nets. PrimeTime-SI exits the analysis loop after completing the current iterat i on , when the percentage of nets selected for reevaluation in the next it eration is less than this number. This vari abl e is one o f a set of six variables that determi n e e xit criteria; PrimeTime - SI exits the analysis l oop after comp leting the c u rrent iteration if one or more of t he fol l owing is t r ue : 1 . The number of iterations performed equa l s the value of the xtalk_ max_ iteration_ count variabl e . 2 . All de lta delays fall between the values of the si_ xtalk_ exit_on_min_ delta_ delay and si_ xtalk_ exit_ on_max_ delta_delay var iables. 3 . The number of nets selec ted for reevaluation in the n ext i teration is less than the value of the si_ xtalk_ exit_ on_ number_of reevaluated_ nets var i able, 4. The percentage of nets (relat ive to the tota l number of nets ) selected for reevaluat i on is l ess than the value of the si_ xtal k_ exit_ on_ reevaluated_ nets_pct variable. 5. The percentage of nets (relative to the number of cross-coupled nets) selec ted for r eeval ua t ion is less than t he value of the si_xtalk_ exit_ on_ coupled_ reevaluated_ nets_pct variabl e . 6. You manually exit the analysis loop by pressing Control-C to send an interrupt signal to the PrimeTime process. The interrup t is handled as any other exit c ri teria , at the end of the current iteration of the crosstalk ana l ysis. You cannot interrupt iteration immediately without exiting PrimeTime. To determine the current value o f this variable, si_ xtalk_ exit_ on_ reevaluated_ nets_pct . type printvar 153 44 si_xtalk_reselect_delta_and_slack xtal k_reselect_delta_a nd_slack Reselect nets that satisfy both delta delay a nd slack rese l ection criteria . Persistent parameter that controls whether window filtering is performed on nets based on the reselection criteria xtalk_reselect_delta_delay , xtalk_reselect_delta_delay_ratio, xtalk_reselect_max_mode_slack, and xtalk_reselect_min_mode_slack. TYPE Boolean Syntax: DEFAULT xtalk_rese l ect_de l ta_and_slack tru e [ false false where the values have the following meaning : DESCRIPTION true When true, the intersection of sets of nets reselected by delta delay and slack based criteria is used . For a n et to b e reselected t he following must be true : - The net is reselected by absolute delta delay AND - The net is reselected by relative delta delay AND - The net is reselected by setup OR hold slack OR borrowing AND Critical path rese l ection is not enabled . When tr ue, the nets that sa t isfy only one of the above criteria (e.g., absolute delta) but not others (e.g., slack) are not counted in the report associated wi th Perform window filtering on nets based on the delta delay, max_mode_slack and min_mode_slack criteria . false Do not perform window filtering . The default value is false. XTALK-004. When false , the union o f sets of nets reselected by delta delay and slack based criteria is used . For a net to be reselected the following must be true: - The net is reselected by absolute de l ta del ay OR - The net is reselec ted by relative delta delay OR - The net is reselected by setup OR ho l d slack OR borrowing OR - Critical path reselection is enabled AND the net is on the critical pa t h . To determi ne the current value of this variable, type printvar s i_xtalk_ reselect_ delta_ and_ slack. 154 45 Attributes of the cell Object Class area float The area of a cell. If the cell is hierarchical, this includes net area. area double area base_name string The leaf name of a cell. For example, the base_name of cell U1/U2/U3 is U3. base_name string (read-only) base name dont_touch boolean Identifies cells to be excluded from optimization in Design Compiler. Cells with the dont_touch attribute set to true are not modified or replaced during compilation in Design Compiler. Setting dont_touch on a hierarchical cell sets the attribute on all cells below it. Set with set_dont_touch, and used by characto;ori zo;o_context and create_timing_context. You can set and unset the dont_touch attribute. dont_touch bool dont touch in optimization fu ll_name string The complete name of a cell. For example, the full name cell U3 within cell U2 within cell U1 is U1 /U2/U3. The full_name attribute is not affected by full_name string (read-only) cell instance fullname i s_sequenti al bool (read-only) is sequential cell number_of_pins uint (read-only) number of pins (read-only) current_instance. is_sequential boolean A cell is sequential if it is not combinational. number_of_pins integer Number of pins on the cell. The number of pins can be different before and after linking. For example, if some pins were unconnected in a Verilog instance, after linking to the lower-level design, additional pins can be created on the cell. 155 1 Attributes of the cell Object Class is_clock_gating_check cell boolean A is_clock_gating_check (read-only) bool is an ICG or combinational cell with clock gating check ref_name cell string A ref_name string (read-only) referred lib_cell name 156 2 Attributes of the clock Object Class fu ll_name s tr ing The name of the clock. This is set with create_ clock. It is either the name given with the -name option, or the name of the first object to which the clock is attached . Once set, this attribute is read only. period float The clock period (or cycle time) is the shortest time during which the clock waveform repeats. For a simple waveform with one rising and one falling edge, the period is the difference between successive rising edges . Set with c reate_c l ock -period. propagated_clock boolean Specifies that clock latency (insertion delay) be determined by propagating delays from the clock source to destination register clock pins. lfthis attribute is not present, ideal clocking is assumed. Set with set_propagated_clock. sources string This is a collection of the source pins or ports of the clock. The sources are defined with the create_clock command. full_name string full name period float clock period propagated_clock bool compute propagate delay on clock network for latency sources collection clock source (read-only) (read-only) 157 3 Attributes of the clock Object Class is_generated clock boolean A is_generated bool is generated clock 158 4 Attributes of the /ib_ce/1 Object Type area float A floating-point value representing the area of a library cell. area double cell area (read-only) base_narne string The name of a library cell. For example, the base_name of library cell tech1/AN2 is AN2. base_name string base name (read-only) dont_touch boolean Identifies library cells to be excluded from optimization. Values are true (the default) or false. Library cells with the dont_touch attribute set to true are not modified or replaced during compile. Set in Design Compiler with set_dont_ touch. dont_touch bool do not touch in optimizat ion, equal to (user_dont_touch OR auto_dont_touch) ful l _narne string The fully qualified name of a library cell. This is the name of the library followed by the library cell name. For example, the full_name of library cell AN2 in library tech1 is tech 1/AN2 . full_name string full name i s_sequenti a l bool (read-only) is sequential cell number_of_pins uint (read-only) number of pins is_sequential nurnber_of_pins boolean integer This attribute is true if the library cell is sequential. Number of pins on the library cell. I I (read-only) 159 5 Attributes of the lib_ cell Object Type dont_use lib_cell boolean A dont_use bool do not use in optimization, equal to (user_dont_use OR auto_dont_use) 160 6 Attributes of the lib_pin Object Type base_name fan out_l oad s tr ing fl oa t The leaf name of the library cell pin. For example, the base_name of tech1/AN2/Z is Z. A floating-point value representing the fanout load value of a library pin. This value is used in computing max_fanout design rule cost. base_name string (read-only) base name fanout_ load float (read-only) fanout load full_name string (read-only) full name fu ll_name s t rin g The fully qualified name of a library cell pin. This is the name of the library followed by the library cell name followed by a pin name. For example, the full_name of pin Z on library cell AN2 in library tech1 is tech 1/AN2/Z. max_c apaci tance fl oa t A floating-point value representing the maximum capacitance design rule limit for a library pin . max_capacitance float max capacitance loa max_fa nou t floa t A floating-point value representing the maximum fanout design rule limit for a library pin. max_ fanout (read-only) float max fanout p i n_capac ita nce fl oat A floating-point value representing the capacitance of a library pin. pin_capaci tance float pin cap (read-only) 161 7 Attributes of the lib_pin Object Type pin_direction lib_pin string A pin_direction in out inout internal unknown (read-only) signal direction 162 8 Attributes of the net Object Type base_name s t r ing The leaf name of a net. For example, the base name of net i1/i1z1 is i1z1 . You cannot set this attribute. dent touch boolean Identifies nets to be excluded from optimization in Design Compiler. Values are true (the default) or false. Nets with the dont_touch attribute set to true are not modified or replaced during compile with Design Compiler. Set with set _don t_t ouch. ful l _name string The complete name of a net. For example, the full_name of net i1z1 within cell i1 is i1/i1z1. The f ull_name attribute is not affected by current instance. The f ull_name attribute is read-only. total_ capa ci t anc e_ max f l oat A floating-point value representing the sum of all pin capacitances and the wire capacitance of a net for maximum conditions. You cannot set this attribute. to t al_capacitanc e_min fl oat A floating-point value representing the sum of all pin capacitances and the wire capacitance of a net for minimum conditions. You cannot set this attribute. Cread-only) base_name string base name dont_touch bool dont touch in optimization full_name string full name total_capacitance_max float [range : 0.0000 . . inf] (read-on l y,application) max tota l total_capacitance_min Cread-only) cap : float [range : 0 . 0000 . . inf] (read-only , application) : min total cap 163 9 Attributes of the pin Object Class actual_fall _ tran slt lon_max float A floating-point value representing the largest falling transition time for a pin . actual_fall_transition_max [range: -inf . . inf] float (read-only,application) actual max fall transition actual fall_transition_min float A floating-point value actual fall transition min [range: -inf .. inf] float (read-only,application) actual min fall transition representing the smallest falling transition time for a pin. ac t ual_rise_transition_max float A floating-point value representing the largest rising transition time for a pin. actual_rise_transition_max float [range: -inf .. inf] (read-only,application) actual max rise transition actual_rise_transition_min float A floating-point value representing the smallest rising transition time for a pin . actual_rise_transition_min float [range: - inf .. inf] (read-only,application) actual min rise transition clocks collection (read-only,application) clocks c l ocks string The collection of clock objects which propagate through this pin. It is undefined if no clocks are present. 164 10 d i rec t i on fu ll_name i s _ three_s t a t e str ing string b oolean The direction of a pin . Value can be in, out, inout, or internal. The pin_direc tion attribute is a synonym for direction. Directions can change as a result of linking a design, as references are resolved. The complete name of a pin to the top of the hierarchy. For example, the full name of pin Z on cell U2 within cell U1 is U1/ U2/Z. The setting ofthe current instance has no effect on the full name of a pin. See also the lib_pin_n a me attribute. This attribute is true if a pin is a three-state driver. direction in out inout internal unknown (read-only) signal direction full_name string (read-only) pin full name is_three_state bool (read-only) is tri-state 165 11 Attributes of the pin Object Class is_clock_gating_clock pin boolean A is_clock_gating_enable pin boolean A I is_clock_gating_clock : bool (read-only) is the clock pin of an clock gating cell is_clock_gating_enable (read-only) : bool is the enable pin of an clock gating cell 166 12 Attributes of the port Object Class actual fall transition_max float A floating-point value representing the largest falling transition time for a port. You cannot set this attribute. actual_fall_transition_min float A floating-point value representing the smallest falling transition time for a port. You cannot set this attribute. actual_rise_transition_max float actual fall transition_max : float [range: - inf .. inf] (read-only,application) : actual max fall transition actual fall transition_min float [range: -inf .. inf] (read-only,application) actual min fall transition A floating-point value representing the largest rising transition time for a port. You cannot set this attribute. actual rise transition_max float [range: -inf .. inf] (read-only,application) actual max rise transition actual_rise_transition_min float [range: -inf .. inf] (read-only,application) actual min rise transition clocks collection (read-only,application) clocks direction in out inout internal unknown signal direction full_name string full name actual_rise_transition_min float A floating-point value representing the smallest rising transition time for a port. You cannot set this attribute. clocks string The collection of clock objects which propagate through this port. It is undefined if no clocks are present. direction string The direction of a port. Value can be in, out, inout, or internal. The port _direction attribute is a synonym for direction. You cannot set this attribute. full _name string The name of a port. You cannot set this attribute. (read - only) 167 13 add_to_collection add_to_collection Adds objects to a collection, resulting in a new collection. The base collection remai n s unchanged. Given a collection base_collection and one or more objects, returns a new collection with all objects of the base collection and all the listed objects . In addition, you can choose to filter out all duplicate objects from the new collection. The base collection is not modified . SYNTAX Syntax collection add_ to_ collection base_collection object_spec add to collection \ base collection \ objects \ [- unique] [-unique] col lectionbase_ collection list object_spec ARGUMENTS base_collection Specifies the base collection to which objects are to be added. This collection is copied to the result collection, and objects matching object_spec are added to the result collection. base_collection can be the empty collection (empty string), subject to some constraints, explained in the DESCRIPTION. object_spec Specifies a list of named objects or collections to add. If the base collection is heterogeneous, only collections can be added to it. If the base colleccion is homogeneous, the object class of each element in this list must be the same as in the base collection. If it is not the same class, it is ignored. From heterogeneous collections in the object_spec, only objects of the same class of the base collection are added. If the name matches an existing collection, the collection is used. Otherwise, the objects are searched for in the database using the object class of the base collection. The object_spec has some special rules v1hen the base collection is empty, as explained in the DESCRIPTION . where the arguments have the following meaning : base collection The collection to which you want to add an object. objects The list of objects you want to add . [-unique] Removes duplicate objects from the resulting collection . -unique Indicates that duplicate objects are to be removed from the resulting collection. By default, duplicate objects are not removed. Case No. 3: 13-cv-02965-MMC PLNTF Exhibit No. 1441 Date Entered FEB 2 9 2018 Signature 1 all_connected all connected Creates a collection of objects connected to a net, pin, or port object. You can assign this collection to a variable or pass it into another command. Returns objects connected to a specified set of other objects. For each net, the command retrieves all pins connected to the net, and for each pin , the command returns all nets connected to the pin. Furhtermore, you can limit the returned objects based on their name or based on an Aprisa filter. This Mer accepts logic expressions of attributes. Only objects whose attributes satisfy the filter expression are retained . SYNTAX Syntax col l ec t ion all_ connected object_ s p ec [- l ea f] l i st obj ec t _ s p ec all_connected objects \ [-all functions] \ [-quiet] \ [-regexp] \ [-nocase] \ [-filter string] \ [ - leaf] ARGUMENTS where the argument has the following meaning: object_ spec Specifies the object whose connections are returned. This is a collection oE one e l ement which is a net, pin, or port collection, or the name of a net, objects pin, or port. List of nets for which to return the pins and ports, or list of pins and ports for which to return the net, or a combination of pins , nets, and ports. If the -regexp argument is specified , then objects is a regular expression . The connected objects are returned of all pins, ports , and nets whose names match the regular expression. -leaf Specifies that t he connections of the net t hat are being returned should be globa l or leaf pins. When specified, this gives the leaf pins of a hierarchical net. For non-hierarchical nets , there is no difference in ou tput . [ - all functions] Return the pins of all functions (power, ground , or diode). By default, only connections of type signal are considered. [-quiet] Suppress the messages. 2 2 [ -regexp ] objects is a regular expression . The connected objects of all objects whose names match the regular expression are returned . [-nocase ] objects is case insensitive. This argument is only relevant if the -regexp argument is used . [-filter expression ] Use the logic expression of attributes to only return those objects whose attributes satisfy the expression. [-leaf] Return leaf pins only. 3 3 all_fanin all fanins Creates a co l l ection of pins / ports or cel l s i n the fa n i n of spec if i ed sinks . Retrieves either all pins and ports or cells that belong to the fan-in cone of one or more specified pins. Pins that are referenced in timing constraints , for example, in case-analysis, are also considered part of the fan-in cone. SYNTAX co l l ection all_ fanin -to sink_ li s t [- fl at ] [ - on l y_cells] [- s tartpoints_on l y ] [ - l ev e l s lev e l _ c ount] [-pin_ lev els pin_ count] [- step_into_h i e r a r chy ] list in t s ink_ lis t lev el_ count ARGUMENTS - to sink_ list Specifies a list of sink pin s, ports, or n ets i n the design . Each object is a named pin, port, or net, or a collection of pin s, por t s, o r n e ts . The t i ming f ani n of each sin k i n sink_ list becomes part of the res u lting col l ection . If Syntax all fanins -to collection \ [-only_cells] \ [-flat] \ [-startpoints_only]\ [-level cellLevel] \ [-pin level pinLevel] where the arguments have the following meaning : -startpoi n ts_ only When t h is option is specified, only the timing startpoin ts will be i ncluded in t h e resul t. - only_ cells The res u lt will i ncl ude on ly cells i n the timi ng fan i n of the sink_ list a nd not pin s or ports . Set of pins and ports whose fan-in cone is retrieved . [ -onl y_cel l s] Return the cells of the fan in cone instead of the pins and ports. [-flat] Hierarchical pins, that is, pins that do not exist in a flattened netlist must not be returned. [ -startpoints only ] Only return pins and ports at the start of the fan-in cones . [ - l evel cellLevel] Include pins of all cells that are at a distance up to eel/Level cell arcs from the root pin. [ - pi n_level pinLeve l] a net is specified, t h e effect is the same a s l ist i ng all driver pin s on t h e net. Thi s argument i s required . - to col l e cti on Include all pins that are at a distance up to pinLevel pin arcs from the root pin. - flat Ther e are two major modes i n wh ich a11_ fani n functio n s : h ierarchical {the default) a n d flat . When in hierarchical mode, on ly objects wi t hi n t he same hier archica l level as the c urren t s ink are i n clu ded i n the res u lt . I n f l at mode, t he only non-lea f objects in the resul t will be h ierarchical sink pin s . -level s cell_ count The trave r sal will s t op when reachin g a depth of sear ch of cell _ count hops, where the counting is performed over the l ayers of cells o f same distan ce f rom the sink . -pin_ l e vels pin_ coun t The traversal wi l l stop when reaching a d epth of search of pin_ co unt hops, where the counting is per formed over the layers o f pins of same distance fr om the sin k . -step_ i nto_ hierarchy Th is option may only b e used i n hier a rc hical mode a n d on l y h a s effect wi t h either -levels or -pin_ levels. Wi t hou t t h e swi t ch, a hierarc hical b l ock at t h e s a me l ev e l o f hiera rch y a s the c ur r ent sin k i s c onside r ed to be a cel l; 4 4 all_fanout all fanouts Creates a collection of pins / ports or cells in the fanout of the specified sources. Retrieves either all pins and ports or cells that belong to the fan-out cone of one or more specified pins. Pins that are referenced in timing constraints, such as the effect of disable timing or case-analysis, are also considered part of the fan-out cone. SYNTAX Syntax collection all_ fanout - from source_ list -clock_ tree [- flat] ( -only_ cells] (- endpoints_ only] [ -leve l s level_ count] [ -pin_ l evels pin_ count] ( -step_into_hierarchy] list int source_ list level_ count ARGUMENTS -from source_ list Specifies a list of source pins, ports, or ne ts in the design. Each object is a named pin, port, or net, or a collection of pins, ports, or nets. The timing fanout of each source in source_ list becomes part of the resu lti ng collection . If a net is specified , the effect is the same as listi n g all load pins on the net. This option is exclusive with t he -clock_ tree option. all fanouts -from collection \ -only_cells \ -flat \ -endpoints_only \ [-level cellLevel] \ [-pin level pinLevel] where the arguments have the following meaning : - f rom collection Set of pins and ports whose fan-out cone is retrieved . - on l y_cells Return the cells instead ofthe pins and ports in the fan-out cone. -flat Hierarchical pins, that is, pins that do not exist in a flattened netlist, must not be returned . -endpoints only Only return pins and ports that are legal timing end points. Driver pins, floating pins and pins connected through disabled timing arcs are not included. -endpoints_ only When this option is specified, on l y the timing endpoints will be inc l uded in the result . [ -level cel lLevel] Include pins of all cells that are at a distance up to eel/Level cell arcs from the root pin . -only_ cells The result will include only cells in t he timing fanout of the source_list and not pins or ports . [ -pin_ leve l - clock_ tree Indicates t h at all clock source pins and / or ports in the design are to be used as the l i st of sources . Clock sources are specified using create_ clock . If there are no clocks, or if the clocks have no sources, the result is the empty collection. This option is exclusive with the -from option . pinLevel] Include all pins that are at a distance up to pinLevel pin arcs from the root pin . - flat There are two major modes in which all_ fanout functions : h ierarchical (the default) and f l at. When in hi erarchica l mode , only objects within the same hierarchical level as the current source are included in the result. In flat mode, the only non - leaf objects in the result will be hierarchical source pins. -levels cell_ count The traversal will stop when reaching a depth of search of cell_ count hops, where the counting is performed over the layers of cells of same distance from t he source. 5 5 -pin_ levels pi n_ count The traversal will stop when reaching a depth of search of pin_ count hops, whe re the counting is performed over the layers of pins of same distance from the source. -step_ into_hierarchy This option may only be used in hierarchical mode and only has effect with e ither -levels or -pin_ levels . Without the switch, a hierarchical block at the same level of hierarchy as the cu rrent sink is consider ed to be a cell; the o utput pin s are considered a single level away from the related input p i ns, regardless of what is inside the block. With the swi t ch enabled, t h e counting is performed as though the design were flat, and although pins inside the hierarchy are not returned, they determine the depth of the related inpu t p in s . 6 6 all_instances all instances Creates a col l ection o f a l l insta nces of a specific design (or library cell) in the current des i gn, relat i ve to the current instance. You can ass i gn the resulting col l ection of cel ls to a variab l e or pass it i nto another command. Given a collection of library cells and modules, returns all instances of those cells, or given a name pattern , returns all instances of cells and modules whose name match the name pattern . SYNTAX Syntax col lection all_ instances (-hierarchy] object_ spec all_instances object \ [-hierarchical] \ [-quiet] ARGUMENTS -hierarchy Searches for instances in all l evels of instance hierarchy below the current instance. By defau lt, only instances from the current level of hierarchy are where the arguments have the following meaning: object Collection of library cells, modules, or names of cells and modules for which to return all instances . [-hierarchical ] Match cells at any level in t he hierarchy. [ - quiet] Suppress the messages _ con sidered . object_spec Specifies the target design or library cell. This can be a design collection, a lib_ cel l collection, or a name. 7 7 append_to_collection append_to_collection Ad d ob jec t ( s ) to a c o l lec tion . Mo difies v a ri able . Appends the specified collection objec t _ col lecti on to the collection held by the collection variable base_collection. If this variable does not exist, this command creates it. You can choose to remove the duplicate objects from the resulting collection. SYNTAX Syntax col l ecti on add_ to_ collection var_ name object_ spec [ - unique] col l ec ti on var_ name l i st object_ spec append_to_c ollection base collection \ obj e ct_collection \ [-unique] ARGUMENTS where the arguments have the following meaning : var_ name Specifies a variable name . The objects matching object_spec are added into the collection referenced by this variable . object_ spec Specifies a l ist of named objects or collections to add. base coll ecti on The variable that holds the original collection . Is created if needed . obj ect_ collection A collection of objects to add to the original collection . [-un i que] Removes duplicate objects from the resulting collection sto red in the variable base_ collection. - unique Indicates that duplicate objects are to be removed from the res u lting collection . By defa u lt, dup l icate ob j ects are not removed . 8 8 characterize_context Captures the timi ng context of a list of instances . SYNTAX str ing characterize_ context ( - timing) [ -design_ r u l e s) [ - constant_ inpu ts ] (-no_ boundary_ a nnotation s ] c e ll_ list l is t [ -envi r onmen t] cell list Command: characterize_context <db:module_inst_list> Derive timing constraints for a set of cell instances. option: -timing -environment -design_rules -constant_inputs -no_boundary_annotations -output_dir string(.) --get_option arg<l> --set_option ... --get_default arg<l> --set_default ... --system_default --list_options --load_options --license --help not supported yet not supported yet not supported yet not supported yet not supported yet directory to wr ite derived sdc get option value set option value get default value set default value use system default values list current option values load current option values list required licenses display command help ARGUMENTS -timing Characterizes timing information; for example, clocks, input a n d output delays, and timing excep t ions. -environment Characterizes environment-related information; for example , operating conditions (process, temperature, and voltage), wire load model, capacitive loads on input and output pins, and driving cell information on input pins . -design_ rules Characterizes design rulesi for example, max_ capacitance, max_ transition, and max_ fanout. - constant_ inputs Cha racter i zes logic constants p ropaga ted to input pins of t he instance being character iz ed by the case analysis capability of PrimeTime . -no_boundary_annotations Disables characterization of annotated capacitance on boundary nets as annotated capacitan ce in the characterized instance. Instead, the port wire capacitance is adjusted to account for any difference between the estimated and annotated values . By default, PrimeTirne characterizes annotated capacitance on boundary nets as annotated capacitance in t he characterized instance. cell_ list Specifies a list of instances to characterize. 9 9 check_timing check_timing Reports timing problems in the design. The following timing violations are reported : Sh ows p ossib le t i ming p roblems for design. • latch_fanout-A latch fans out to itself or to another latch connected to the same clock. • no_clock-No clock reaches a sequential cell's clock pin. • string check_ timing [ - ve r bose ) [ - signi f i can t _ digits digits] [-ms _ mi n_ separa t ion del t a] [ - overr ide_ default s c h eck_ list ] [-incl ude check_ list] [-excl ude check_ list] no_input_delay-An input port does not have an input delay constraint. • SYNTAX no_driving_ceii-A port does not have a driving cell constraint. • unconstrained_endpoints- An endpoint of a timing path, such as an output port or data pin of a sequential cell, does not have a timing constraint set. Syntax check timing [-verbose] \ [-extra] \ [-scenario name] float d elta i nt digits lis t c h eck_ list ARGUMENTS -verbose where the arguments have the following meaning : -significant_digits digits Specifies t he number of digits of precision to be displayed by warnings that show floating point numbers . Allowed values are 0- 13; the default is determined by the report_ default_ significant_ digits variable, whose default value is 2 . Use this option if you want to override the default . -ms_min_separation delta Minimum separation value between master and slave clocks. The default minimum separation i s 0 . 0 . -override_ defaults check_list Overrides the checks in timing_ check_ defaults using check_ list. See the man page of timing_ check_ defaults for its default value . [ - verb os e ] In the report, include the names of the pins and ports with timing constraint problems. [ - ext r a] In addition to the regular timing checks, also check the completeness of the timing arcs in the Liberty files. [ - scenario name] Shows detai l ed information about potential problems . Specifies the scenario file to use. The scenario file contains the conditions under which to analyze the design such as Process-Voltage-Temperature corners. If you do not provide a scenario name, the timing checks are based on the soc and Liberty file set for the current design. -include check_ list Adds the checks listed in check_ list to the checks in timing_ check_ defaults . -exclude check_l ist Subt racts the checks listed in check_ list from t he checks in timing_ check_ defaulta . check_ list Gives the list o f checks to be performed . Each element in this list is one of the following strings: clock_crossing, data_ check_multiple_ clock, data_ check_no_ clock, generated_ clocks, generic , la tch_ fanout, latency_override, loops, rns_ separation, rnultiple_clock, no_ clock, no_ input_ delay, retain, signal_ level, unconstrained_ endpoints. 10 compare_collections compare_collections Compa res the con t e nts of two collec t ions . If the same objects are i n bo t h collection s, the resu lt is "0 " (like st r ing compare) . If they are different , the res u l t is n o n zero. The order of the objects can optional l y be con sidered . Compares collections. If both collections contain the same objects, the command returns 0; otherwise , it returns -1 . You can control whether the order of objects should be taken into account. SYNTAX Syntax int compare_ collections [ - orde r _ dependen t ] collect i onl col l ect i on2 c o l l ec t ion collectionl co l lec tion collect i on2 compare_c o lle c tions c olle c ti onl collec tion 2 \ [-order_dependent] ARGUMENTS where the arguments have the following meaning : -orde r _depende nt Ind icates that the order of t he objects is to be consider ed ; tha t is, the col l e ct i on s are con side red to be differen t if t he objects a r e ordered d i ff er en tly . colle c tionl Specifies the ba se c ollection for t he compa ri son . The empty str ing (the empty col l e ct i on ) is a lega l value for the collection ] argumen t . collect i on] and collection 2 Collections to compare . [ - order_depende nt ] Indicates that collections are only considered identical if the order of the objects in the collections is the same. collec t i on 2 Specifies the collection with which to compare to collectionl . The empty string (the empty collec tion ) is a legal value for the c ollection2 a rgumen t. 11 11 connect net connect Connects a net to specified p ins or ports . Connects port and pins to a net. lfthe port and pins are already connected to other nets , you must explicitly specify that you want to reconnect them; otherwise, you get an error. If you want to connect a port to a net that is already connected a port, you must have marked these ports and the net as a feedthrough upon creation, and you must mark this connection as a feedthrough as well. By default, the connect Tel command honors the dont_touch attribute set on a net and issues the ChgDontTouch error when you try to connect to such a net. You can however force a connection. SYNTAX i n t connect_net net object_ spec str ingnet list object_ spec ARGUMENTS Syntax connect -net net name \ pins_and_ports \ [-reconnect]\ [-feedthru] \ [-force] where the arguments have the followi ng meaning : net Specifies the n ame of the net to which the pins and ports are to be connected. object_ spec Specifies a list of pins or ports to connect to net. -net net name Name of the net to which you want to connect the pins and ports. pins_and_ports Names of the pins and ports to connect to the net. By default, only pins and ports that are not yet connected to a net are allowed to be connected . Use the -reconnect argument to allow all pins and ports to be connected to this net. [-reconnect ] Allows you to specify pins and ports that are already connected to nets. Those pins and ports are disconnected from their original net and reconnected to the specified net. 12 12 copy_collection copy_collection Duplicates the conten t s of a collec ti on , res u lt i ng in a new collec t ion . The base collection remains unchanged . Returns a new collection that contains the same objects as a specified collection . Note that the objects are not copied , only the collection of those objects. SYNTAX Syntax col le c tion copy_collection collectionl collection collectionl copy_collection collection where collection are the objects you want to copy. ARGUMENTS collectionl Specifies the col lect i on to be copied. If t he empty string is used f or t he collection] argument , the command returns t he empty string (a copy of the empty col lec ti on i s the empty collection) . 13 13 create_configuration Command: create_configuration Don't support. Creates a con fi gurati on f o r mu lti -scenario a n alysis . SYNTAX create_ configuration - globa l_da ta file_ l i st li st file_li st -global_data { <string> --get_option arg<l> --set_option --get_default arg<l> --set_default ... --system_default -- l ist_options -- l oad_options --l icense --help } order dependent setup files (require) get option value set option value get default value set default value use system default values list current option values load current opt i on values list required licenses display command help ARGUMENTS - global_da ta An orde r dependen t list of f i l es con ta in ing everything that is common across the ent i re a nalysis. These fil es must at the very minimum contain the c omma nds needed to read the design n etl ist . 14 14 create_operating_conditions Comm and: create_operating_conditions standard SOC command Cr e ate s a new se t o f operating condi ti ons in a l i b rary. SYNTAX i n t create_ operating_ conditions - name name - librar y libra ry_name - process process_value -temperatur e temperature_value -voltage voltage_ value [-tree_ type tree_ type] [ - calc_mod e calc_ mode] [ - rail_ vo l tages rail_value_pairs ] str i ng name s t r i ng library_name float process_value float temperature_ value float voltage_value str i ng tree_type str i ng calc_ mode Tel list rail_ value_pairs option: -name string name of ope r ating condi tion (requi r e) -library string name of lib r ary ( req uire) -process double(O.OOO) process scaling f actor ( r equire) -tempe r ature do uble(O.OOO) temperature value (requi r e) -voltage double(O.OOO) voltage value (req uire) -tree_type tree_type(balanced_tree) tree type tree_type = balanced_tree I best_case_tree I wo r st_case_tree -cal c_mode '~ not supported yet -rai l_vol tage 1' not supported yet --get_option arg <l > get option value --set_option ... set option value --get_default arg <l> get default value --set_default ... set default value --system_default use system default values --list_options list cu rr ent option val ues --load_options load cu rr ent option values --license list required licenses --help display command help 15 15 ARGUMENTS -name name Speci fi es the name of the new set of operating conditions. description: This command is the same as standard SOC command. -library library_name Specifies the name of the library for the new operating conditions. -process process_ value Specif i es the process scaling factor for the operating conditions. Allowed va l ues are 0.0 t h r ough 10 0.0. - temperature temperature_value Specifies the tempera ture value, in degrees Celsius , fo r the operating conditions. Allowed values are - 300.0 through +500.0 . -vo ltage voltage_value Spec i f ies the voltage value, i n volts, f or the operating condi t ions. Al lowed values are 0 . 0 through 1000 . 0 . -tree_ type tree_ type Specifies the tree type for the operating conditions. Allowed values are best_case_tree, balanced_ tree (the default), or worst_ case tree. The tree type is used to estimate interconnect delays by providing a model o f the RC tree . -calc_mode calc_mode For use only with DPCM l i braries. Specifies the DPCM delay calculator mode for the operating conditions; analogous to t he process used in Synopsys l ibraries. Allowed values are unknown (the defau lt ), bes t_case, nominal, or worst_case . The default behavior (unknown) is to use worst case values during analysis simi l arly to worst_case. If -rail_ voltages are specified, the command sets all (worst_case, nominal , and best_case) vol t age values . - rail_voltages rail_value_pairs Specifies a lis t of name-va l ue pairs that defines the voltage for each specified rail. The name is one of the rail names defined in the library; the val ue is the voltage t o be a ssigned t o that rail . By de f aul t, rai l vo ltages are as defined in t he library; use this option to override the default vo ltages for specified rails . 16 16 define_proc_attributes #Add extensions to a procedure define_proc_attributes Describes the help text of a specified Tel procedure and describes the attributes of its arguments. This Tel command allows you to use Aprisa's parse_proc_arguments Tel procedure in your procedure to parse its arguments. By using both the define_proc_attributes and parse_proc_arguments Tel commands, you integrate your procedure in the Aprisa environment. The meta arguments, such as--h, are enabled and the info and help commands also work for your procedure. [-info info_text] [-define_args arg_defs] [-command_group group_name] [-permanent] [-hide_body] [-hidden] [-dont_abbrev] name (Help string for the procedure) (Procedure argument definitions for verbose help) (Command group for procedure. Default: Procedures) (Procedure cannot be overwritten) (Body cannot be viewed with 'info body') (Procedure does not show up in help or info) (Procedure can never be abbreviated) (Procedure name) Syntax define_proc_attributes \ procedureName \ -info string \ -define_args * \ where the arguments have the following meaning : procedureName Name of the procedure. -info string One-line help string for tile procedure. -define_args * Arguments and options of the procedure. This is a collection of argument definitions. Each argument definition has the following format: (arg_name opti on_help value_help da ta_ type attribu tes ) where: arg_name Name of the argument. If the name starts with a'-' , it indicates a named argument. otherwise, it is a positional argument. option_help Help string describing the argument. va l ue_ help Help string describing the acceptable values for the argument data_ type Type of value expected for this argument, such as float, string, boolean, one_of_string attribu tes Additional attributes, such as required, optional, and for types one_of_string, the list of values. 17 17 define user attribute define_user attribute Defines a user attribute . You must define an attribute before using it. User attributes, similar to Aprisa attributes, have a name, a type, and can only be attached to objects of the specified type. You can create, modify, and delete user attributes. Attribute names must be unique within the class for which the attribute is defined, and the value of the attribute can only be of one data type. Defines a new user -de fi ned attribu t e. SYNTAX Syntax string define_ user_ attribute -type data_ type - classes class_ list [ -range_min min] [-range_max max] [ -on e_of values] (- impor t] [ -quiet] attr_name string data_ type list class_ list d o uble min double max list values string attr_ name ARGUMENTS bool \ where the arguments have the following meaning : - type data_typ e Specifies the data type of the attribute. The s upported data types are s t ring, int, float, doub le, and boolean. -classes class_list Defines the attribute for one or more of t he c l asses . The valid object classes are d e sign, port, cel l , pin, ne t , li b, define user attribute attr name \ -type int 1 float 1 string I point - class class l ib_ cell or l i b_pin. -range_min min Specifies min value f or nume ri c ranges. This is only valid when the data_ type attr name Attribute name. -type int I float I s t ring I point I bool Data type of its value. -class cla.ss Class name of object for which it is defined. is i nt or double . Specifying a minimum constraint without a max i mu m constraint creates an a t tribute which accep ts a value = min. -range_max max Specifies max value f or numeric ranges. This is only valid when the data_ type is int or double. Specifying a maximum constraint without a minimum cons trai nt creates an attribute which accepts a value = max . -one_o:E values Provides a l ist of allowable strings . This is only valid when the data type is s t ring. -import Impo rt thi s attribute :Erom a design or library database . -qui e t Does not report any messages. attr_narne Spec i fi es the name of the attribute. 18 18 derive_clocks Create s c locks on sourc e pins i n design. SYNTAX s tring derive_ clocks -peri od period_ value [ -wave f orm edg e_ list ] f lo at period_ val ue l i st e d ge_list ARGUMENTS - period period_value Specifies the clock period of the automatically derived clocks. The clock period has a va lue greater than or equal to zero (val ue = 0). -waveform edge_l i st Specifies the rise and fall edge t i mes of the clock , i n l ibrary time units, over an entire c l ock period . It defines the c lock edge s pecification. The first time that is l isted is a rising transit ion ; typica l ly the first rising t r ansition after time zero . There must be an even number of increasing times and alternating rise and fall times . I f you do not specify a n edge_ list va lue, the command assumes a defau lt waveform that has a rise edge of 0.0 and a fall edge of period_value/2. derive clocks Creates clock definitions for all missing clocks so that design registers are constrained. These generated clocks are specified by a clock period and a set of times when clock edges occur, similar to regular clocks. The main difference is that the missing clocks are generated by Aprisa as opposed to being defined as part of the SDC constraints. Syntax derive clocks \ -period period \ -waveform times where the arguments have the following meaning: -period period Clock period for all missing clocks. -waveform times Clock waveform, specified as a collection of times at which clock edges occur, starting with a rising edge. 19 19 filter The filter command, a synonym f or the filter_ collection command, is a DC Emu l ation command prov i ded for compatibi l ity with Design Comp i l er. filter This command is aliased to filter_collection . 20 20 fi Iter_collection Fi lters a n existing co l l ec t ion, resulting in a new col lect i on . The bas e collecti on remains un changed . filter collection Retains from a given collection of objects only those objects that meet the specified criteria. Criteria are formulated as logic and pattern-matching expressions of attributes and values. The following operators are supported: equal != : not equal !< <= : not match pattern match pattern : less than : less or equal > : greater than >= : greater or equal &.&. : Logic AND II : Logic OR The pattern matching syntax can be the Tel regular expression or the Tel glob bing (also known as wildchar) syntax. You can use both Aprisa and user-defined attributes in filter expressions. Before using user-defined attributes, you must have defined them using the define_user_attribute Tel command. Moreover, you can also filter objects based on the existance of user attributes on these objects. For convenience, many Aprisa commands, such as all the get_ *Tel commands, have a -filter argument you can use to filter objects based on a Tel regular orglobbing expression. SYNTAX Syntax co llection filter_collection base_collection expression [-regexp ] [-nocase ] filter_collection collection expression \ [ { attributename -exists } ] \ [-rege:x.p] \ [ -nocase] c o llectionbase_collection string express ~ on 21 21 ARGUMENTS base_collection Spec i f ies the base collection to be fi l tered . This co llec t ion i s copied t o the result collection. Objec ts are removed from the result collection if they are eva l ua t ed as false by the condi ti onal expression val ue . Subs t itu t e the collection you want for bas e_ collection. expre ss ion Specifies a n expression with which to filter ba se_collec ti on. Substitute the s t ring you wan t fo r expression. where the arguments have the following meaning : collection Collection on which the filter criteria is applied . Only objects that meet these criteria are returned by the filter. expression Expression using constants, object attributes, and the operators listed above. [ { attributename - exi s t s -regexp Specifies that the=- and !- fil ter operators wil l us e rea l regular express i ons . By defaul t , the =- and !-fil t er operators use s imple wildcard pattern ma tchi ng with the * and ? wi l dcards . -noca s e Makes the patte rn match case - insensitive. When you specify this option, you must also specify the -regexp opt ion. } ] Only retain objects that have an attribut e of the specified name. [- regexp ) Use Tel regular expression syntax for the pattern . The default is Tel globbing syntax. [-nocase) Expression is case insensitive. 22 22 foreach in collection foreach in collection Iterates over the e l emen ts of a c ol l ect i on. Executes a set of Tel commands on each object from a given Aprisa collection. This command is equivalent to the foreach Tel command but has the advantage that it operates directly on an Aprisa collection, which is much more efficient than a Tel list. SYNTAX Syntax s tr ing foreach_ in_ collection itr_var collections body string i tr_ v a r list coll ec t ions string body foreach in collection object collection ( body } ARGUMENTS where the arguments have the following meaning : itr_ var obj ec t Tel variable containing the object on which the body of Tel commands is operated . colle cti o n Collection of objects on which the body of Tel commands is operated. This can also be a Tel expression returning a collection. { body I Set of Tel commands that is executed on each object in collection, one at a time. Specifies the name of the iter a t o r va r i abl e. collections Specif i es a l i st of col l ections over which to iterate. body Specifies a scr i pt to execute per iter ation . 23 23 get_ attribute get_attribute Retr i eves t h e v a l u e of a n a ttri b u te on a n obj ec t. Returns the value of the specified attribute of an object or a collection of objects. If you pass a collection of objects, then a collection of attribute values is returned. The command can also be used to check whether the attribute exists on that object. Syntax SYNTAX string get_ attribute [-class class_ name] stri ngclass_name st r i ngobject_ spec or col l ection object_spec stringa t tr_ name [-quiet ] object_ spec attr_ name ARGUMENTS - class class_ name Spec i fies the class n ame of object_spec, if object_spec is a name. Va l id values for object_spec are design, port, cell, pin, net, lib, lib_cell, lib_pin, clock, timing_path, and timing_point. You must u s e this option if object_spec is a name . -quie t Indica t es that any er r or and warnin g messages are not to be reported. object_spec Spec i fies a single object f rom which to g et the at t ribute va lu e . object_ spec must be is either a collec ti on of exa c tly one object, or a name whi ch is combined with the c l ass_name to find the object. I f object_spec i s a n ame , you must also u se t he - class option . attr name Specifies the n ame of the attribute whose va l ue is to be retrieved . ge t _at t r i b u te obje c t_or_ collection att r _ n ame \ [ - c l a ss c e ll I net I p ort I pin I lib_c ell I lib_pin) \ [ - e x i st ] \ ( -qui e t ] where the arguments have the following meaning : obj ect_ or_ coll ecti on Object or collection of objects whose attribute value you want to retrieve . a t tr n ame Name of the attribute to retrieve. [- c lass c e l l I net I p o rt I lib_ cell I lib_pin ] pin Only examine objects of the specified type. [-ex i s t ] Check whether the object attribute exists. If you specify a collection of objects, then the function only returns true provided all objects in the collection have the attribute. [-qui et ] Prevents an error to be issued if an attribute is not found. 24 24 get_generated_clocks get_generated_clocks Creates a collec t ion o f gener ated clocks. Returns a collection of generated clock. objects. The returned set of generated clocks may be selected by name, by the Aprisa attribute-based object filter, or by a combination of these. Syntax SYNTAX collection get_generated_clocks [- quiet] [ - regexp] [- nocase] ( - fi l ter expression ] pa tt e r ns st ringexpression list patterns get_generated_clocks clockpattern \ [-filter attribute_constraint] \ [-regexp] \ [-nocase] ARGUMENTS -quiet where the arguments have the following meaning : -regexp Views the patterns argument as real regular expressions rather than simple wildcard patterns. Al so, modifies the behavior of the =- and !- filter operators to compare with real regular expressions ra ther t han simple wildcard patterns. -nocase clockpattern Only return clocks whose names match the pattern. By default, Tel globbing syntax is assumed. [-filter attribute constraint ] Only return generated clocks whose attributes meet the constraints defined in attribute_constraint. For more information on the syntax of the attribute constraints, see the filter_co//ection Tel command. (-regexp] Suppresses warning and error messages if no objects match . Syntax error messages are not suppressed . Treatthe name patterns in attribute_ constraint as a regular expression . By default, Tel globbing syntax is assumed. [-n ocase] Ignore case when performing name matches in at tribute_constraint. When combined with -regexp , makes matches case- insensitive. You can use nocase onl y when you also use -regexp. - f ilter expression Filters the collection wi t h expression. For any generated clocks that match patterns, the expression is evaluated based on the generated cloc k 's attributes. If the expression evalua t es to tru e , the g enerated clock i s included in the result. patterns Matches generated c l ock names agains t patterns. Patterns can include t he wildcard characters • *" and M? ... • 25 25 get_object_name get_object_ name Gets the na me of the object in a co l l ection of exact l y one object . Returns the name of the specified object, or returns a collection of names of a specified collection of objects. SYNTAX Syntax string get_ object_ name collection stringcoll ec ti on get_ object_ name object I - multiple objects ARGUMENTS where the arguments have the following meaning: co l lection Specifies the collection. This must be a co l lection of exact l y one object. object Object whose name you want to retrieve . -multiple Controls whether the command expects a single object or a collection of objects. objects Collection of objects whose name you want to retrieve . 26 26 get_path_groups get_path_groups Creates a collec tion of path groups fr om the current design . You can assign t he se path groups to a variable or pass them into another command . Returns the list of names of all path groups given a glob-style pattern or a regular expression. Syntax SYNTAX collection qet_path_qroups [-qui e t] [ - regexp ] [ -nocas e ] [-fi lter expressi on] stringexpression l ist patterns get_pa t h_groups clock names \ [-quiet ] \ [-regexp) \ [-nocase ) ARGUMENTS where the values have the following meaning: patterns - quiet Suppresses warning a nd error messages if no objects match. Syntax error messages are no t suppressed . clock names Name or regular expression. All path groups with a launching clock or a capturing clock that have a name matching the regular expression are returned. [-quie t ] Do not report errors or warnings. [-reg exp] Treat clock_names as a regular expression. [ -noca se] Do not consider case when matching clock names to the regular expression clock_ names. - regexp Vi e ws the patterns argument as real regular expressi ons rather than simple wildcard patterns . Also, modifies the behavior of the =-and !- filter operators to compare wi th rea l regular expressions rather than simp l e wildcard patterns . - nocase Whe n combined with -regexp makes matches case-insensitive . You can use nocase only when you also use -regexp . 1 -filter expression Filters the collection with expression. For any path groups that match patterns, the expression is evaluated based on the path group's attributes. If the expression evaluates to true, the path group is included in the result . NOTE: This command returns a list of strings and not a collection of objects as most other get~ Tel commands do. For this reason. no -fiffer argument is supported. patterns Matches path group names against patterns. Patterns can include the wildcard characters "*" and "?" 27 27 get_ti ming_paths get_timing_paths Creates a col lec tion of timing pa ths f or custom reporting and other proc essing. You can a ssign t h e se timing paths to a va riable or pass t hem i nt o another command . Returns a collection of timing paths for custom processing . A timing path is of object type timing_path. You can list all the attribute names of the object using the list_ attribute Tel command with the -class timing_path argument. To list one or all attribute values, use the get_ attribute or report_attribute Tel command. To iterate timing paths in a collection, use the foreach_in_collection Tel command. One attribute of a timing_path object is the points collection, which consists of multiple timing points. A timing point is of object type timing_point. You can list, report, and get attributes of a timing_point object using the list_ attribute, report_ attribute, and get_ attribute Tel commands, respectively. SYNTAX Syntax string get_ timing_paths [ - f rom from_l ist I -ri se_ from rise_ from_ list I -fa l l_from fall _ from_ list] [- to to_ list I -rise_ to rise_ to_ list I - fa l l_ to fall _ to_ list] [ -exclude exclude_ list I -r i se_ exclude rise_ exclude_ list I -fal l_exclude fall _ exclude_ list] [ - throu gh through_ list] [- ri s e _ t h rough rise_ through_ list] [ -fall_ through fall _ through_ list] [ -delay_ type delay_ type ] [ -nworst paths_per_ endpoint ] [ -max_paths max_path_ count] [ -group group_ name ] [ -true ] [ -unique_p ins ] [ -true_ t h resh old path_ de l a y] [ -slack_ greater_ tha n greater_ slack_ limit] [ -slack_ l esser_ t h an lesser_ slack_ limit] [ -ignore_ register_ feedbac k feedback_ slack_ cutoff] [ - aocvm ] [ - include_h ierarchical_p ins ] [ - justify ] [ -trace_ l atch_ borro w] [- reca l cul ate ] [ -start_ end_pai r ] [ -dont_ merge_ dup l i cates ] [ -pre_ comman ds pre_ command_ stri n g ] [-post_ cornmands post_ command_ string ] [ -pa t h _ type format] get _ti ming_ pat hs objects\ [ - from pinlist ] \ [- ri se_f rom pinlist ] \ [-fall_from pinlist] \ [-to pinlist] \ [-rise_ to pinlist] \ [ - fall_to pinlist] \ [-through pinlist ] \ [-rise_through pinlist] \ [ - fall_thro ugh pinlist ] \ max rise max fall [-del ay_type max I mi n I min_max mi n_ri se I min_ fa ll ] \ [-nworst inte ger] \ [ - max_paths integer] \ [-path_type full 1 ful l clock I full clock_ expanded] \ [-slack_ greater_than double ] \ [-slack_l ess_than double ] \ [- gro ups {st ring [string] ... }] \ [- sce na rio string] \ [-no_hierarchica l _p ins] \ I \ 28 28 list list l i st list list list list list list list list list from_list rise_ f r om_ li s t fall _from_l ist to_ list rise_ to_ list fall _ to_ list exclude_ list rise_ exclude_ list fall _ exclude_ list through_ list rise_ through_ list fall _ through_ list stringdelay_ type string format in t paths_per_ endpoint int max_path_ count l ist group_ name f l oat path_ delay float greater_ slack_ limit float lesser_ slack_ limit floa t feedba ck_ slack_ cutoff ARGUMENTS I where the arguments have the following meaning : -from f r om_list Specif ies a l is t of fr o m pins, po r t s, net s , o r cloc k s to b e repor t e d . Pa th startpo in ts are typically the input ports or c l ock pins of registers . If you specify a c l ock, al l startpoints are con$idered if they are clocked by the clock . obj ec t s Only select paths that contain one of the specified objects of type pin , port, or clocks. [ - f rom pi n lis t ] Only select paths that start from one of the specified list of pins . [ - r ise_from pi n lis t] Only select paths that start with a rising signal from one of the specified list of pins. [ - f a ll from pinlist ] Only select paths that start with a falling signal from one of the specified list of pins. [ - t o p inlist] Only select paths that end in one the specified list of pins . [ - ris e to pinli st ] Only select paths that end with a rising signal in one the specified list of pins. [ -fal l _ to pinl i s t ] Only select paths that end with a falling signal in one the specified list of pins . [ - thro ugh pi n list ] Only select paths that go through at least one of the specified pins. name d clock. but o nly the path s lau nche d by fa l li ng edge of the c lock a t the c loc k source , tak ing i n to a c c oWlt a ny l og i ca l inv er s i o ns al ong t he c l o ck path . [ - ri se_through pinli s t] Only select paths that go through at least one of the specified pins with a rising signal. -ex cl u de exclude_list Specifies that o n ly paths not incl uding the named p i ns , ports , nets , cell i ns tances are t o b e repor ted . Repor ti ng wi ll excl u de a l l d ata p a ths from/ throu gh/to t h e name d pi n s , ports , n e ts and c e ll instanc es . If a cell i n sta nce [ - f a ll_thro ugh pinlist] Only select paths that go through at least one of the specified pins with a falling signal. -rise_ from ri s e_ f rorn_li s t Same a s the -from op ti on, e xce pt that the p a th mu st r i se from t h e objec ts spe cified. If a c lock ob ject is sp e cified, t hi s o pt ion s elec t s st ar tpoints clocked by t h e n amed cloc k , but only the pat h s launched by risi ng edge of the c l ock at the clo c k source , tak i ng i n to acc o unt a ny logi c a l i nv ersions along the clock path . -f a ll_from tall _ from_ list Same as the - from option , except t h a t the path mu st fall from t h e objects specified. If a clock object is spec ifi ed, this option selects star t poi n ts clocked by the named clock , b u t only the p aths launched by fallin g edg e of the c l ock a t t h e cloc k sou rce, tak ing int o ac cou nt any log ical i nve r sions along the cl ock p a th . -to to_list Spe cifies a l i st of t o pi n s, p o rt s, ne ts, o r cloc k s t o b e r e p o rt ed . Pat h endpoi n ts are typi ca lly t he ou tput ports or d a ta pi n s of regis t ers . If you spe cify a cl ock, a ll e ndp o i n t s a re cons idered if t h ey are cons t r ai ned by the clock . -rise_to rise_ to_ list Same as the - to option , but applies on ly to p a ths rising at the endpoin t. If a c l ock obj e ct i s spe cifie d, this opt i o n s e l e cts endpoi n ts clocked by the named cloc k , but only the path s captu r ed by risin g edge of the cloc k at c l ock sour ce , tak ing in to a ccoun t any logi c al inversions alon g t h e clock path. - f all_to f all_to_list Same as the -to option, b u t applies only to path s falli n g at the endpoin t . If a c l ock obj ec t i s s p e cified, this op ti on s e l e cts e ndpoi nt s clocke d by t he 29 ZY is specified, all pins of the cell are excluded. -exclude has h i gher precedence than -from/ - through/ - to. - exclude does not work with -true pt i on . -excl\lcle is exclusive with -:ri~Je_excl\lcle or -fall_ excluClfll . -exclucle does not apply to borrowing path from -trace_ la.tch_ borrow option or clock path from path full_ c:lock/full_ clock_ expanded op ti ons . [-delay_type max I mi n I min_ max max_rise I max fa l l I min rise min fall] min_max-Paths with a minimum or maximum delay. -fall_exclude tall_exclude_list Same as the -exclude option, but applies on l y to paths fall i ng at the named p i ns, ports, nets, cell i n stances. -rise_through ri se_through_ list Specifies the same as the -through option, excep t that the path must rise through the objects specified . -fall_through tall_ through_list Specifies the same as the - through option, except that the pa th mus t fall through the objects specified. - delay_type delay_type Specifies the type of path delay. Valid values are max (the default), min , min_:max , max._ rise, :max_ fall , min_ rise , or min_ fall . The " rise" or ~fall " in the delay_type refers to a rising or falling transition at the path endpoint. max_rise-Paths with a maximum delay for a rising signal. max_fa/1-Paths with a maximum delay for a falling signal. min_rise-Paths with a minimum delay for a rising signal. min_fa/1-Paths with a minimum delay for a falling signal. [-nwors t integer] Number of worst paths to retain per path group. The default value is 1. [-max_ paths integer ] Maximum number of paths to retain per path group. The default value is 1. [- p ath_ t ype ful l I fu l l ful l clock_expanded ] c l ock full_ clock-Retain the -nworst paths for each path group and include the timing of the clock from the clock root to the clock of the state element that launches the signal and the clock to the state element that captures the signal. - max_paths max_path_ count Specifies the maximum number of paths to get per path group, where max_pat.h._count = 1 The default is 1. -path_ type forma. t Specifies t he format o f the path report and h ow th e timin g pa t h is displayed . The allowed value is full_ clock_ expanded , which displays full clock paths between a p rimary clock and a related generated clock in addition to the full_clock timing path . full_ clock_ expanded-Same as fu/l_c/ock . but also include the clock path from the original clock to the generated clock. [ -slack_greater than doubl e] -group group_name Restricts the collection to paths i n this group_ name. Paths are grouped by using the grO\lp_path or cree.te_ clock command. Specifies that the longest ( le.ast - slack) true paths in the design are to be reported . This option can require long r unt imes for certai n designs that have many false paths. The true_ delay_p:rove_ true_ backt:rack_ limit and true_ delay_pr ove _ false _ b acktrack_ limit variables are u sed to limit t h e amount of backtracking during the operation of the report_ timing command with the -true option . The set_ case_ ana.ly s is command is used t.o specify a partial input vector to be considered for - true analysis _ - true canno t be combined with -max_patha (lj, -nworat Ol, -dela.y_ type (pa t h type other tha n max ), unique , -rise_ through , fall_ through and - rise_ from and fall _ from options: true is mutually exclusive with them. - unique__pins Specifies that only paths through a unique set of pins are to be reported . This option can require longer runtimes when used in combination with the nworst option with a large number of paths targeted for reporting . Selects paths based on their timing. The following are valid values: full-Retain all pins along the -nworst paths of each path group from launch pin to capture pin . This is the default report . - nworst paths_per_ endpoint Gets n worst paths to endpoint, wh ere paths_per_endpoint is = 1. Th e default is 1, meaning that only the wors t path to an endpoint is considered. Specifying larger values of paths_per_endpoint increases run time. -true max-Paths with a maximum delay. min-Paths with a minimum delay. -rise_exclude rise_exclude_list Same as the -exclude option, but applies on l y to path s rising at the named p in s, ports, nets, cell instances. - through through_ list Specifies a list of thr ough pins, ports, or n ets to be reported. Only paths through the named pins are considered . You can specify many through_list groups by using multiple -through options . The objects specified within one -through option are assumed to be in OR mode. The grou p of objects specif ied with multiple -through options is assumed to be in AND mode. If you specify -through only once, PrimeTime reports only the pa t hs that trave l through one or more o f the objects in the list. If you specify multiple -through options, PrimeTime reports only the paths that t ravel through one or more o f the objec t s i n each list. PrimeTirne uses the exact order in which the -through opt i ons are l i sted; so to obtain correct results, you must ensure that this order is the same as that followed by the actual paths in the circuit. Only select paths based of the specified delay type . The following types of delay are supported : Only select paths whose slack is greater than the specified value. The default value is -100000000000000000000. [-slack less than double] Only select paths whose slack is smaller than the specified value. The default value is 100000000000000000000. [-g roups {string [string] ... ]] Only select paths belonging to one the specified groups. [-scenario stri ng] Only select paths from the specified scenario. [ - no_hierarch i cal_p in s] Do not report hierarchical pins . 30 Jo -star t_end__pair I n dicates that paths a r e rep orted for each pair of startpoi n t and e ndpoi n t based on connectivity . This option c a n lead to lon g r un time with l a r g e memory usage and can lead to gen erat ing a huge number of paths depending o n the d esign . By de f ault this option wi l l o n ly search for p a ths which are violati n g . This defau l t val u e ca n be changed b y havi n g a n expl i cit -s. l o.ck_ le sse r _ than option. The optio n s t ha t do not work with th i s op t ion are -nworst , -max_paths , -unique_pina , -true , - justify , -alack._ greater_ than , ignore_ regiater_ feadbac k. Un l i ke with other options of get_ timi ng_paths , this option cau ses the paths retu rn ed to n o lon ger be sorted based on sl a ck, instead , paths are a rran ged based o n the endpoint with those sharin g the same e ndpo in t appear i ng n e x t to o n e a n oth e r. The max imum n umber of p a ths re tu r n ed is limited to 2000000 . In order to avoid the poten tia l of return ing duplic a t e paths, this option works as though the variable t irni n g_ report_ always_ u se_ valid_ s t art_ end__poin ts wa s set t o tr u e . vhere the arguments have the following meaning: wns I tns Specifies whether to return worst negative slack or total negative slack. [-setup I -hold] Specifies whether to return the setup or hold timing result. The default is setup timing . [-scenario scenario] Specifies for which timing scenario to return th e timing QoR metric. - t rue_ threshold pa t h_ de lay Used with the -true opt i o n . Speci f ies a th r eshol d p a th del a y v a l u e , i n l i brary time uni ts , to be used by the -true opt i on to speed up searching . If this option is specified , the get _ tim.ing_patha command wi th the -true option r e t urn s the first p ath it fi n ds g r e ater t h an o r equa l to pat h_ delay , rather than conti n ui n g to s e arch f or a lon g er one. - s lack_ greater _than g.rea cer_ sl ack_ limi c Sp ecifies tha t o n ly those paths with a s l ack greate.r than greacer_ slack._limit are to be reported . This option can be combi n ed with -alack_ lasaer_ than to report on ly those p a ths i n side or outside a gi v e n slack r ange . -slack_ lesser _ than lesser_ slack_limi t Specifies th a t only those paths with a slack l ess than lesser_ slack__limit are to be reported . This option can be combi n e d with -slack._ greater_ than to report on ly those paths i n side or o u tside a given slack r ange . - ignore_ register_ feedback feedback_ .slack_ cutoff Specifies t h at timing paths are t o be ignored if they start and end at the same register t h a t ho l ds a v alue . Th i s op ti on applies to mi n delay as wel l as max delay reports. Paths are ignored on l y if the slack i s less t h an the spec ifi ed feedbac k__.slack_ cutof£ va l ue . This opti o n is appl i e d as a fi lter t o t h e path s after t h ey are generated. Therefore, the number of pa t hs genera t ed may be less t han t h e number specified with t h e -nworst and - max_pa t hs op t ions . -aocvm Specifi es t h a t the re t u r ned timi ng paths are to be ad j usted us i ng AOCVM information . The orde r in wh ich the path s are re t urned rna tches t h e o r der in whi ch t h e p aths would h ave been returned had th i s opt i on not been speci f ied. This option automat ical l y sets - path_ type full _ clock_ expanded . -include_ hierarch ical_pins Specifies that t he returned timing pa t hs contain points for each h ierarch i cal pi n crossed, as we l l as al l l eaf p i ns in the pa t h. - jus t i f y Speci fi es t o find and repor t an inpu t vector t hat sens it izes t he reported path s or to repor t t he pa t h a s fal s e if no inpu t vector is f ound. Use t h e ae t _ case_ ana.lysis command to specify a partial input vector to be cons i dered f or -justify ana l y si s. - trace_l atch_ b o rrow Th is op tion contro l s t h e type o f report genera te d f o r a path tha t star t s at a tran s parent l atch . If t he pat h startpo in t b o rrows f r om t h e pre v i ous stage, using t his option causes t h e report t o show t he entire se t of b o rrowing paths t h a t lead up t o t he b o rrowing l a t c h , starting with a n onbo rrowing path o r a non i nverting sequentia l l oop. - recalculate Indicates t h a t pa t h reca l cu l a t ion shoul d be appl i ed during the search. The wo r s t r eca l cula t ed pa t hs mee t ing t he pa t h requ i rements are re t urned. This option can result in long run times due to t he pa t h search ing required . Th is option does not wo r k with -justify , -true , -slack._ greater_ than and oth er mu l ti scenario op tions, including -pre_ commanas , -post_ commands , dont_merge_ duplica.tes and -attributes . -pre_ commands pre_ command_ string This op ti on i s ava i labl e on l y if t he user invokes PrimeT i me with the mul ti_ scenario op t ion. This opt i on a l lows users to speci f y a string of commands t o be executed i n the s l ave con t ex t befo r e the execu t ion of the merged_ repo rting c ommand . Commands mus t be grouped u$ing t h e "; " characterThe maximum si z e of a command is 1000 c h ars. 31 Jl -pas t_comma n ds pas t_command_s tring This option is available o nly if the u ser invokes PrimeTime with the multi_scenario option. This option allows users to specify a string of commands to be exec u t ed in the slave context after the exe cution of the merged_reparting caromand s . Commands are grouped using t h e c haracter. The ma x imum size of a command is 1000 chars. -don t_rnerge_dup l ic a tes This option is available o nl y if the u ser invokes PrimeTime with the mu lti _ scenario option. It turns OFF a main capability in me r ged reporting that i s ON by default . The option affects the manner in which p at hs from multiple scenarios are merged. By default, when the same path is reported from more than one scenario. PrimeTime reports only t he single most critical i ns tance of that path in the merged report and shows its assoc i ated scen ario. By us ing this opt i o n, PrimeTirne wi l l not mer ge duplicate instances of the same path into a sing l e instance, bu t inst.ead shows all critica l instances of the path from a l l scena r ios . S ince the number of paths reported is limited by th e -nworst . -max_pat.hs and other options of this command, t.he r es ulting merged report, o,1hen t h is option is used, may not be evenly spread out across the design, but inste a d may be focussed on the portion of the design that is critical in each scenario. -attributes attribute_ 1ist This option is available only if the user inv okes Pr irneTime with the multi _ scenario option .A l is t of attributes to be retrieved from a slave collection. If t hi s option is n o t specified then only the f u ll _ name. scenario_,name and object _ class attributes are retrieved . This op t i o n should be u sed in conj u n c ti on with se t _ d i str ibuted_paramet er collection_ levels commands to con tr ol the amount of data retrieved from the 32 32 index_collection index collection Creates a single e leme n t collection . I . e. Given a collection and an index into it, if the index is in range, extracts the object at that i ndex and creates a new col l ection conta i ning only that objec t . The base collection remains unchanged. Retrieves an object at a specified position from a collection . SYNTAX Syntax collection index_collection col l ectionl index co llec t i on col lect i on l int index index collection collection index ARGUMENTS where the arguments have the following meaning: collectionl Specifies the collection to be searched . c ollecti on Collection from which to retrieve the object index inde x An integer indicating the position in the collection . The first object is at index 0. Speci f ies the i ndex into the collection. Al lowed values are integers from 0 to s i zeof_collection - 1. 33 33 inser t _ b uffer Inserts a buf f er a t one or more plns. Command: insert_buffer --interactive internal development utility SYNTAX option: -net collection the net to be buffered (require) -buffer cell collection specify buffer library cell -candidate location point buffer/ inverters cand i date location (require) -skip_legalize skip incremental placement legalization -no_worse_timing do not commit if timing does not improve -inverter_pair use inverter pair in stead of buffer -connected fanout collection fanouts connected with added buffer. -module collect ion buffer/ inverters module -new_net_name string spec i fy the name of new net -new_buf_name string spec i fy the name of new buffer stri ng insert_ buffer [-libraries lib_spec] [-inverter_pair ] [-new_net_names new_net_names] [-new_cell_names new_cell_names] pin_or_port_list lib_cell list new_net_names list new_cell_names list pin_or_port_list st ring lib_ cell ARGUMENTS - libraries lib_ spec If this option is specif i ed, then PrirneTirne resolves lib_cellP from the libraries contained in the lib_spec only . Libraries are searched in the order in which they appear in lib_spec. lib_spec can be a l i st of library names, or collect i on s of libraries l oaded into PrimeTirne; the la t ter can be obtain ed using the get_ libs command. You canno t specify th i s option if a full library cell name has been specified. description: This command is for AtopTech internal use only. -inverter_pair Indicates that a pair of inverting library cells is to be inserted i n stead of a single non-inverting library cell . - new_n et_names new_net names Specifies the net name to be given to the new net that PrimeTirne inserts . This option can only be used if only one buffer or an inverter pair is being inserted . If one buffer i s being inserted , you have to pass only one ne t name. If an inver t er pair is being inserted, you have t o pass t wo net names. These names can be any valid net names, but must be the leaf names i.e. not the hierarchical names. The new names must not contain embedded hierarchical separators . The new names must be unique in the current context (as specified by current_instance) . If you use this option, you have to also use t he new_ cell_ names option. 34 34 - new_cel l _names new_cell_names Specifies the cell name to be given to the new cell that PrimeTime inser t s . This option can only be used if only one buff er or an inverter pai r is being inserted . If one buffer is being i nserted, you have to pass only one cell name. If an i nverter pair is being inserted, you have to pass two cell names. These names can be a ny valid cell n ames, but must be the leaf names i . e . not the hierarchi cal names . The new names must not con t ain embedded hierarchical separators. The new names mus t be un ique in the current context (as specified by current_instance) . If you use th i s option, you have to also u se the new_net_ names option. pi n_or__port_list Specifies a lis t of pins or ports to buffer. 35 35 link_design Re so l ves r e fe rence s i n a de s i gn. link_design Builds the complete design by resolving references from instances to cells. This command pertom1s the following functions: • The different LEF, GDS, and Liberty libraries are combined to build an internal project library with cells that have all views needed by Aprisa (timing view, layout \Jiew, abstract \Jiew, and so on). • The references in the imported design are replaced by references to cells from this project library. • In a hierarchical design , this step also resolves the references from blocks in the design to cells representing hard blocks. If no design has been set yet with the cu"ent_design or cu"ent_module Tel command, then Aprisa sets the current design to the first found module without a parent. To build the design, the Jink_design Tel command uses the following infonmation : • Verilog netlist (loaded with the read_ veri/og Tel command) • Logic/timing library (loaded with the read_liberty Tel command) • Physical library (loaded with the read_lef, read_mi/kyway_fram, load_fibrary Tel commands) • PR_LIB or GDS abstract libraries stored with the project, when available. These need not be loaded explicitly. They allow you to examine the abstract in the context of the complete design. For references to Liberty models that are not yet loaded, Aprisa uses the search path as set by set_link_path Tel command. Only Liberty libraries can be loaded on demand. All physical libraries must be loaded explicitly for the /ink_design Tel command to add them to the project library. When you load several libraries containing cells with identical names, Aprisa issues a warning and uses the first cell found. It is, however, recommended to ensure that all cells have unique names. Re-executing the link_ design Tel command on a design causes Aprisa to rebuild the internal project library using the current settings of the search path and library variables, and re-establishes the binding of instances in the design to cells in the project library. When saving a design, you have the option to save a local copy of the physical cells of the internal project library with the design . The gdslib library contains the full layout in GDS fonmat as loaded from GDS or OASIS. The pr/ib library contains the routing abstract in PR_LIB fonmat, as loaded from LEF, Milkyway FRAM, or PR_LIB libraries. Bot the prlib and gdslib libraries are stored with the project. Once these project libraries exist, they are always loaded when the design is loaded. By default, the link_design Tel command links these libraries after external libraries that were loaded using read_Jef, read gds. read oasis or load library Tel commands with the -link first argument, that is, cells of these external libraries will overrule cells saved in the project libraries. O'sing the db parameter, use_own_ lib_before_ link_ first, the prlib and gdslib project libraries are linked first , that is , only cells that do not yet exist in the project libraries are picked up from external libraries , even if the -link_first argument was used. When the use_own_/ib_before_link_first parameter is set, the link_first argument only affects the order of libraries linked after the project libraries . You can control how Aprisa deals with name conflicts when importing GDS cells . When th ird-party macros are imported , typically they come with their own GDS libraries . Enable the persistent db parameter, auto_uniquify_gds_cel/s, to automatically generate unique names for cells with identical names but different content. Cell content is considered different if any shape on any layer differs, or if they contain cross-references of different cells. Only GDS cells who have the cell attribute uniquify set are eligible for uniquification . 36 36 Note that, even though they contain the same information, Aprisa makes a distinction between empty modules and missing modules. An empty module has an (empty) Verilog definition ; A missing module is a module who was not found and whose Veri log definition was inferred. You control whether empty modules should be considered errors. Missing modules are always considered errors. With regards to busses , Aprisa expects bus nets to be connected to bus pins.A UbPinNotBus error is issued when the Verilog netlist contains a connection of a bus to a pin that is not defined as a bus pin . You can specify that a pin is a bus in one ofthe following two ways: • Load a .lib with the correct library pin bus definitions. • Use a Verilog stub to describe the library cell with its bus pins. There are two cases when a bus pin is inferred from the bus net it is connected to: • A cell is a proto-lib_cell or a proto-module . • The db parameter, default_bus_lib_pin_order, specifies a default bit order. This approach allows Aprisa to infer that a pin is a bus pin and to infer how the bus pins are connected to the net bits. Note that this method is not recommended. Syntax SYNTAX string link_ design [ - verbose] [design_name] stringdesign_name [ - remove_ sub_ designs] [ - keep_ sub_ designs] ARGUMENTS l ink_d esign [ -proto) \ (- replace_ own_ pr_l ib_ wi t h I string [ string] .. . )] \ [- rep l ace_own_gds_lib_wi th { stri ng [ s t ring ] . . . } ] \ [ - r e l oad_ lg_ lib_ wi t h_ diff] \ [-no_p r oto_l ib_ce l l ] \ [-strict ] \ [-max_r ef_ co un t _ fo r_proto_ module integer ] \ [-min_pln_count fo r _ proto_module integer ] \ [-al l ow_ defined_empty_modules ] \ [-bind_lib _ ce ll_only_ to_ empty_ modul e ] where the arguments have the following meaning : - verbose [-pro to] - remove_sub_designs Indicat es t hat subdesigns are to be remove d after linking. By de fault, subdesigns are removed. Use this option t o free up memory and improve per f ormance. For more in f ormation, s ee the s ec ti on en titled " Performanc e Consider ations ." Create prototype modules and library cells for all cells referenced in the netlist for which physical models are missing. [- repla ce_ own_p r_lib_wi t h { strin g [s trin g] ... )] In the project library, replace all cells whose names are in the specified list with cells that have the same name from one of the loaded libraries. The project library can be saved on disk when the project is saved , and contains a copy of all cells with an Aprisa layout view that are used in the design. [-rep l ace_ o wn_gd s_lib wi th { s tring [strin g] . .. )] Indicates that the linker is t o display verbose messages. Replace all cells in the projects's own gdslib whose name is in the specified list of cell names with cells that have the same name from one of the loaded libraries. The project's own gdslib is created when the project is saved and contains a copy of all cells with a GDS layout view that are used in the design . -keep_ sub_ design s Indicates that subdesigns are to be kep t after l i nking. By defaul t, subdesigns are removed. Use this option to keep t he sub-designs around so that current_design can be changed to o ther designs later. design_ name Sp ecifies the n ame of the design to be linked; the defau l t design . is the current 37 37 [-re l oad_lg_lib _ wi th_dif f) Reload Liberty files from different Linux paths based on the current search_path or link_path settings. By default, a Liberty file is not loaded if another Liberty file with that same file name and same internal library name is already loaded , even ifthe path name is different or the file on disk (that is, its timestamp) changed . Use this argument if you want to replace the Liberty file with a new version that is in a different path but has the same file name and internal library name . After using this argument, the old version ofthe Liberty file can be removed from memory using the remove_fibrary -af/_ unused Tel command . [-no_ p r o to_li b _ cell ) Do not create a dummy library cell if no valid cell is found. [-st ric t ] Do not link unless all logical and physical library cells are present. This is the default behavior. If the -proto argument is used , this argument is not applicable . If for a module no abstract is found, the abstract is generated automatically, and the warning LnkNoAbs is issued. [ -c he ck ) Link but issue a warning when library cells are missing, physical (LEF) or logical (Liberty) models are missing, when the pins on instances do not match the ports defined on the library cells or when pins in physical models do not match the pins on logical models. [ -max_r ef_co u n t f or_ pro t o_ mo du l e maxinst) (-min_ pi n_ cou nt_ f or_pro t o_ modul e minpin) [- a llow_d ef i ned_emp t y_mo d ules ] [ -b ~nd_ll b odu l e] c e ll_ on l y_t o_ e mp t y_ m Maximum number of references allowed for proto-modules . If more than maxinst instances of the missing cell exist, no proto-module is created. The default value is 10. Minimum number of pins required for proto-module. If a missing cell has less than minpin pins, no proto-module is created. The default value is 50. Do not treat empty modules as errors. Only bind a module to a corresponding library cell if that module is empty. 38 38 list_attributes Lists currently d e fi ned attrib utes . list attributes Lists the attributes of an object type ifthe -class argument is specified . Otherwise. it lists attributes of all available object types . For a list of supported object types, see Aprisa Classes. SYNTAX Syntax s tring list_ attributes [ -appl ica t ion ] [- class class_ name ] str ingclass_name list attrib utes \ [-class class] \ [ - p a tt e r n string] \ [ - sort] ARGUMENTS - applica t i on Lists application attributes as well as user-defined attribu tes . -class cl ass_name Limit the l i sting to at t ribu t es of a single class. Val i d classes are design, port , cell, net, and so on. ARGUMENTS - application Lists appl i cation attributes as well as user-defined attributes. - class where the arguments have the following meaning:: [-class c lass ] Specifies the type of object for which to return the attributes. [-pattern string) List the attributes or report on the attn butes that match the specified name pattern. [-sort) Sort the names of the reported attributes . cl ass_name Limi t the l i sting to attributes of a single class. Val id classes are d esign, port, cell, net, and so on. 39 39 list_libraries list libraries Lists al l l i b rar i e s that ar e read into Pr i meTime . Lists all libraries that are loaded into an Aprisa session. The command returns the full paths to libraries, or, if the project was saved with the -a/1_/ibs, -prlib, or -gdsfib arguments, the paths are shown as own_pr_lib, lg_/ib, or gds_pr_Jib. For each library, four names are reported: • file_name is the UNIX file name. • full_name is the UNIX file name, except for a Liberty file, where the full_name is the file_name followed by the intemallibrary name. • full_path is the absolute UNIX path with all symbolic links resolved. • search_path is the path name to the library as specified in the library search path. When you save a project, you control whether the full_path or the orig_pathto files are stored with the db parameter dont_expand_paths. You can also obtain this information from the following read-only attributes on each library: • fu/l_name-Full name of the library, including the name of the file and the internal name of the library. • base_name -Base name of the library. For Liberty files, this is the internal library name; For all other libraries, such as LEF and GDS, this is the name without suffix of the file containing the library. • source_fi/e_name-Name of the Linux file from which the library was read . • source_fi/e_searoh_path_name-Path name of the Linux file containing the library, using the path as specified in the search path. This path may contain symbolic links and may be relative. • source_fite_full_pattl_name-Absolute path name of the Linux file containing the library, with symbolic links resolved. You can list the attributes, use the following Tel command: % list attr -class lib SYNTAX Syntax string list_ libraries [-only_ used ] list_lib raries [ l i b_n ames ] \ [-only_used] \ [-detail ] \ [ -lib_cell cells] 40 40 ARGUMENTS - only_used Ind icates only the list libraries in u se . A library is in u se if a link ed d esign links to library cells from the library. where the arguments have the following meaning: [lib_names ] Only report on the specified libraries. [-only_used] Only list the libraries if they contain cells that are used in the current project. [-deta il] List for each library all the cells that are used in the current project. [- l ib_cel l cells) Only report on cells from the specified list. The link path information and list of libraries are not reported . lfthis argument is used with the -only_used argument, only used cells from the list are reported . 41 41 load_of Gets the capacitance of a library cell pin . It i s a DC Emulation command provided for compatibility with Design Compiler . SYNTAX float load_of lib_pin st ri nglib_pin Comm and: load_of <string:lib_pin> <lib_pin> lib pin Tel procedure option: --help display command help ARGUMENTS li b__pin Specifies the name of the library cell pin, or a collec tion tha t contains the library cell pin, for which to get the capacitance. description: return pin load 42 42 parse_proc_arguments # Parse arguments to a procedure define_proc_attributes Describes the help text of a specified Tel procedure and describes the attributes of its arguments. This Tel command allows you to use Aprisa's parse_proc_arguments Tel procedure in your procedure to parse its arguments. By using both the define_proc_attributos and parse_proc_arguments Tel commands, you integrate your procedure in the Aprisa environment. The meta arguments, such as--h, are enabled and the info and help commands also work for your procedure. -args arg_list result_array (Argument list to be parsed) (Name of array to use to store parse results) Syntax define_proc_attributes \ procedureName \ -info string \ -define_args * \ where the arguments have the following meaning : proceduxeName Name of the procedure. -info string One-line help string for the procedure. -defi ne_args * Arguments and options of the procedure. This is a collection of argument definitions. Each argument definition has the following format: {arg_name opti o n_help value_help data_type attributes) where: arg_ name Name of the argument. If the name starts with a'.', it indicates a named argument. otherwise, it is a positional argument. op t ion_ help Help string describing the argument. value_ help Help string describing the acceptable values for the argument data_ type Type of value expected for th is argument, such as float, string, boolean, one_of_string a ttribu t es Additional attributes, such as required. optional, and for types one_of_string, the list of values. 43 43 read_aocvm read aocvm Reads advanced on -chip variation (OCV) derate factor tables. Reads an advanced on-chip variation (OCV) derating model from a text file. This is the recommend method to build such a model. The set_aocvm_componentTcl command will be phased out eventually. SYNTAX in t read_ aocvm Syntax read aocvm tile [-use_db_distance_unit] aocvm_file ARGUMENTS aocvm_ fi l e Specifies the name o f the advanced OCV file. where the arguments have the following meaning: file Name of the advanced OCV model file to read. (-use_db_dista nce_uni t ] Assume distances are in user-defined distance units instead of database units. The syntax of the file is as follows: version version number object_type design I l ib_cell I cell rf_type rise I fall I rise fall delay_type cell I net I cell net derate_type early I late object_spec string depth set_ of_ M floats _ distance set of N fl oats table N r ows M colums - -- where the lines have the following meaning : object_type design I lib cell 1 cell Derating model holds for standard cell, a specific block., or for a complete design . rf_type rise I fall I rise fall Derating factor holds for a rising event, a falling event, or both. By default, the setting holds for both. del ay typ e c ell I ne t ne t I cell Derating factor applies to cells , nets, or both . 44 44 derate_type early I late Setting holds for an early path (signal path for hold analysis, or clock path for setup analysis) or for a late path (signal path for setup analysis, clock path for hold analysis). object _ spe c string This line is ignored for now. Will be implemented in future release. depth set of M f loa ts Different values of logic depth for which a column of derating factors is provided . Note that M can be zero, indicating that this is a one-dimensional model that has derating factors that are only a function of the distance. distance set of N floats Different values of distance for which a row of derating factors is provided. Note that N can be zero , indicating that this is a one-dimensional model that has derating factors that are only a function of the depth . tab le N ro ws M columns N rows, with in each row M values. Each row corresponds to a distance . Each column corresponds to a depth . 45 45 read_milkyway _fram read_milkyway Reads physical library data from a Milkyway FRAM library. The FRAM library contains the cell frame views, that is, for each cell the location of its pins and the blockages for the router on the various layers. In addition the route abstracts, also the no_pg and no_signal route guides are read. The reader fully supports the Milkyway 2008 standard. Reads in one l inked design fro m milkyway database. Syntax SYNTAX int read_ milkyway [-version version] scenario scenario_ name] CEL_ name string CEL_name string scenario_ name string design_ library [ -netlist_onl y ] [-library design_library] [- read_rni l kyway_frarn mw_library_path where mw_library_path is the path name of the Milkyway database to read. ARGUMENTS - version version Specifies the version of the design to be read. For examp l e , there are design files unde r the CEL view in the milkyway design library design_lib: 'design_ lib/CEL /des ignl_pre_routel :l', 'design_lib/CEL/ designl_post_r oute:2' etc. The 1 or 2 after the •: • is the vers i on number of the design. The default is to read the most current version. -netlist_only Indicates that only the netlist is to be read; constraints are not read. The default is to read both netlist and con strain ts. -library design_library Specifies the absolute or rela tive pa t h to the MW design library. This option can be l eft out if t he variable mw_ design_ library specifies the path to the MW design library . -scenario scenario_ name MW database is capable of storing multiple constraint s that can correspond to various scenarios of running the design. This option specif ies the name of the scenario for reading in constraints from MW database. The default is to not use a scenario. CEL_ name Specifies the design filename to be read . For example, there are design files under the CEL vi ew in the milkyway design library design_ l ib: 'design_ lib/ CEL/designl_pre_route l :l', 'design_lib/ CEL/designl_post_rou t e : 2' etc. The designl_pre_route or designl_post_route are the CEL_name argument. Do not include version n umber in this argument . 46 46 read_milkyway _tech read_milkyway Imports the technology information from a Milkyway database. Reads in one l inked design fro m milkyway database. SYNTAX Syntax int read_ milkyway [- version version] scenario scenario_ name] CEL_ name s tr ing CEL_name string scenario_ name string design_ library [ -netlist_onl y ] [-library design_library] [read_ milkyway_tech filename \ (-r lc mode l rlc model] \ [ - rlc=corner MIN I NOM I MAX] [-r o u t ing _dir h v I vh ) \ ARGUMENTS where the arguments have the following meaning : - version version Specifies the version of the design to be read. For examp l e , there are design files unde r the CEL view in the milkyway design library design_lib : 'design_ lib/CEL/designl_pre_ routel: l', 'design_lib / CEL/ designl_post_ route:2' etc. The 1 or 2 after the •: • is the vers i on number of the design. The default is to read the most current version. Name of the Milkyway file to read. f il ename [ -r lc_mode l rlc_model] -netlist_only I ndicates that only the netlist is to be read; constraints are not read. The default is to read both netlist and con strain ts. [-rlc_corner MIN I NOM I MAX ] -library design_library Specifies the absolute or rela tive pa t h to the MW design library. This option can be l eft out if t he variable mw_ design_ library specifies the pa t h to the MW design library . [-routing_dir hv -scenar io scenario_ name MW database is capable of stor ing multiple constra ints that can correspond to various scenario s of running the design. Thi s option specifies t he name of the scenario for reading i n constraints from MW database. The defa ul t is to not use a scenario . I vh ] Name ofthe RLC model that is created as part ofthe technology import. The default value is MW. Read the RLC data of the specified corner. The default value is MAX. Routing direction for all layers . For the hv routing direction , which is the default value, metal1 is routed horizontally; metal2 is routed vertically; metal3 is routed horizontally, and so on . For the vh routing direction, metal1 is rou1ed vertically; metal2 is routed horizontally; metal3 is rou1ed vertically, and so on. CEL_ name Specifies the design filename to be read. For example, there are design files under the CEL v iew in the milkyway design library design_ l ib: 'design_ lib/ CEL/designl_pre_route l :l', 'design_lib/ CEL/designl_post_rou t e : 2' etc. The designl_pre_route or designl_post_route are the CEL_name argument. Do not include version number in this argument . 47 47 read_parasitics Reads ne t parasitics information from a n SPEF, DSPF, RSPF, or binary parasitics file and uses it to annota t e the current l y linked design . read_parasitics Loads parasitic information extracted from a third-party tool onto the current design . By default, th is command reads parasitic data in SPEF format. The command accepts names with the special character ' (single quote) and insert an escape character. For example , nets that are set to 1'b0 and 1'b1 may result in SPEF net names such as the following: cx_w r ap/ucx / udpj ctl / 1\'bl SYNTAX Syntax Boolean read_parasitics [-format file_ fmt ) [-complete_with completion_type ] [-lumped_cap_only ] [-pin_cap_i n clu ded] [-incremen t] [ - path prefix] [-keep_capac itive_ coupling] [ - coupling_reduction_ factor f a ctor] [-tr i plet_ type ttype ] [-quiet] [ -syntax_only] [-eco] [-origin al_file_name file_name ] [ - ilm_context] [-keep_ var i a t ion s ] [-create_ default_ variation s) f i le_ names read_ paras i t i c s f ilenames \ [- f ormat DS PF I SPEF ] \ [- lumped_ cap_ onl y ] \ [- p i n_ cap_in c l uded ] \ [-inc r eme nt] \ [- qui e t ] \ [-syn tax_ only ] \ [- path path] \ [-stri p _ pa t h prefix ] \ [- merge_s ame_n et_ coup l ing ] \ [- condi tion { condi t i on [condi tion ] ... string string string s tr i n g string float }] file_ fmt completion_ type path_ name file_ names ofname factor ARGUMENTS -format file_ fmt Specifies the format of the parasitics file . Allowed values are SPEF, DSPF, RSPF and SBPF {Synopsys Binary Parasitics Format) . If - format is not specified, the app l ication can determine whether the file is SPEF, DSPF, RSPF, or a compressed ver sion of those three ascii formats . However , to read a file in SBPF , you must specify - format SBP~ . -complet e _with completion_ type This op t ion does not apply to the RSPF format. Indicates t hat a net with partially annotated parasitics is to be completed by inserting capacitances and resistances according to completion_ type. Allowed values are zero, which completes the net by inserting zero capacitances and resistances; and wlm, wh ich compl etes the net by inserting capacitances and resistances derived from wire load models. This option is equivalent to reading the parasitics file and then using the command complete_ net_p arasit i cs -complete_ wi th . Note : complete _ net_parasitics and read_parasiti c s -camplete_with complete a net only if all missing segments are between two pins and the nets are partial ly annotated (nets are not affected if they are ful l y anno t ated or have no annotation at al l ). Also , t h e net mus t be h ierarch i cal, so t hat if the parasit i cs for the b l ock- l evel parts of a net are missing, those where the arguments have the following meaning: fi l ename [ - f o rma t Name of files with parasitic information to load. DSPF I SPEF ] Format of the parasitic data . The default file format is SPEF [ -lumped_ cap o n l y] Only annotate the total capacitance of the nets. [- pin_ca p_inc l u d e d] RC networks already include the pin capacitances. [-increment] Add these parasitics to previously annotated parasitics instead of replacing them . [ - quiet] Do not report the annotated parasitics in the log file. [ - syn tax_only ] Do not load the parasitics but check if the SPEF syntax is valid . Note that this is only a syntax check . It 48 does not check whether the parasitic file matches the netlist. parasitics could exist in the top-level net. If any of these conditions are not met, you must correct the SPEF or DSPF file manually. -lumped_cap_only This option does not apply to the SBPF format. Indicates that only the total capacitance of ne ts is to be annotated as a lumped capacitance on the annotated nets . The RC networks specified in the parasitics file are discarded . The annotated lumped capacitance is the capacitance specified when t he net is declared in the parasitics fi le . -keep_ capacitive _coupling Indicates that t he cross capacitors are to be kept in the RC networks data structure . Thi s facilitates the capacitive crosstalk analysis, but does not turn it on. This option disables the -ooupling_ reduction_ factor option ; the command will fai l if both options are specified. All coupling capacitors are split to ground with a factor of 1 .0 if crosstalk analysis is not activated . This option applies to both the SPEF and t he SBPF format . This option requires a PrimeTime SI l icense. [ - pa t h path] Relative path from the current design to the hierarchical design name for which the parasitic file has been created. [ - s t r i p _ path p r e fi x] Prefix of all SPEF or DSPF objects that needs to be stripped. [ - merge_s a me _n e t _coup l ing] Merge coupled capacitances between same nets. [-condi tion { condition List of SPEF parasitic conditions to load. [condition] ... Jl -pin_ cap_ included Indicates that t he RC networks are to include the pin capacitances. By default, the RC network does no t include pin capacitances. This option does not apply to the RSPF fo r ma t . The RC pi model in RSPF format has to alv1ays include effect o f pin capacitances . -increment Indicates that previously annotated parasitics on the nets listed in the parasiti cs file are not to be overwr itten . Additionally, any incomplete annotations in t he parasitics file are not to be rejected. By default, the RC annotation specified in the parasitics file overwrites the previous parasitics annotations of the nets listed in the parasitics file . Use this option for annotating hierarchical parasitics files. - path prefix Specifies a relative path from the current design to the hierarchical design name for which t he parasitics file has been created. By default, absolute pathnames are used . Use this option if the parasitic s file refers to an object (for example, net) in a hierarchy (for example, hier) . Do not u se this option if the parasitics fi le refers to an absolute path (for example, bier/ net) . -coupling_reduction_factor factor This option applies only to t he SPEF format and the SBPF format . A positive fl oating point number that specifies the factor to apply when reducing coupling capacitances to grounded capacitances. The default value is 1 . 0 . This option is disabled if the - k eep_ capaoitiv e _ ooupling option is specified. The command will fail if both options are specified . -triplet_ type ttype This option applies only to the SPEF and PARA forma ts . Several values in SPEF and PARA, s uch as capacitor and resistor values, can be specified as triplets - min: t yp:max . By default, PrimeTime takes the max value. Usi ng this option, t he user can select the min or typ value. Allowed v a l ues are max (the default), typ, and min. - quiet Indicates that the report_ a nnot ated_parasitics report is not to be generated when t he parasitics fi l e has been read. By default, after reading the parasitics file, the repo rt _ annot ated_parasitio s -eheok command is executed. This command reports the number of annotated nets, v e rifies the completeness of annotated RC networks on nets, and checks that no RC elements dangle. It is recommended that you use the - quiet option when reading multiple parasitics files in incremental mode. -syntax_only Indicates that read_parasitics is to parse the file for syntax errors without p erforming any parasitic annotation . Us e this option to troubleshoot your paras iti cs file and avo i d generating error messages during the actual ann otation . No design is required to use -syntax_ only . 49 49 -ilrn_ context Indicates that the annotation is being performed i n the presence of Inteface Logic Models (ILMs). An original design parasitics can be used to annotate a design with ILMs us i ng this opt i on . This option does no t issue error messages for missing nets, cells and pins. - eco Indicates that the files being currently annotated are ECO parasitics from Star-RCXT . PTSI can read ECO parasitics that are written out by Star-RCXT only. The ECO parasitics can be annotated only when there are some existing parasitics that are already annotated. ECO parasitic files contain re extracted p arasitics for just the ECO nets and their immediate coupling ne i ghbours only and do not contain all the nets of t he design . Incremen tal analysis can be performed after reading ECO parasitics. -original_f ile_ name orig_ f i le_name This option can only be used when -eco option is being used. If the original annotation is performed via multiple parasitic files into PTSI, then the ECO parasitic file corresponds to one of the original files (because it corresponds to one extracted database in Star - RCXT). PTSI wi l l try to determine the corresponding original file but it is not always possible. You can use this option to specify which origina l parasitic file does the ECO file correspond to. file_ names When the forma t is one of SPEF, DSPF, RSPF and SBPF, i t specifies a list of files from which parasitics information is to be read. -keep_ variations Indicates that the statistical parasitic information are to be kept in the RC networks data structure. This facilitates the variation aware timing analysis, but does not turn it on. This opti on appl ies o n ly to SBPF format for now. Also, currently, this option does not work with either -eco option or -increment option. This option requires a Pr imeTime VA license. -create_ default_ variations Specifies that default parasitic variations should be created for all the variation parameters. The default variations created are all assumed to be of normal distribution. The mean and sigma values are a lready present in the parasitic fi l e. 50 50 read_sdf read sdf Reads lea f cell and net t iming informa t ion from a f ile i n Standard De l ay Forma t (SDF) and uses that information to annotate the current design . Reads timing data from a standard Delay Format (SO F) file and back-annotates the design . Both regular text files and compressed gzip files are supported. NOTE: The listed unsupported options will be supported in a future release. Syntax SYNTAX string read_ sdf [- load_d e l ay n et I cell] [-ana lysis_type single I bc_ wc I on_chip_ variation] [ -mi n_ file min_ fname] [-max_ fil e max_fname] [ - path path_name] [- type sdf_min I sdf_typ I sdf_rnax] [-min_ type sdf_ rnin I sdf_ typ I sdf_ rnax] [-max_t ype sdf_min I sdf_ typ I sdf_max ] [-cond_ use min I max I min_ max ] [-syntax_ only] [ -strip_path strip_path_ name ] [-quie t ] [ -worst ] file_name string st r ing string string string path_ name sd f_file_ name min_s df_ file_name max_sdf_file_name strip_path _ name read_sdf f ile \ [- l oad_delay load_dela y ] \ [-analys~ s _type analysis_type] \ [ - min_ file min_ file] \ [-max_file max_file] \ [-pa th path ] \ [-min_t ype sdf_min 1 sdf_type 1 sdf_max ] \ [ -max_type sdf_ min I sdf_ t ype I sdf_ma x] \ [-t y p e sdf_rni n I sdf_type I sdf_rnax] \ [-cond_use cond_use] \ [-strip_pa th strip_path] \ [ - syn ta x_ only] \ [-qui et ] where the arguments have the following meaning : ARGUMENTS -load_de l ay net I cell Indicates whether load delays are included in net delays or in cell delays in the t iming fi l e being read . The defaul t is cell. The l oad delay is the file Name of the SDF file to read. por tion of c e ll delay arising from the capacitive load of the net dr i ven by [-load_delay t he cell . -ana lysis_type single I bc_wc I on_chip_variation Use this option only if you have not already set an analysis type wi th set_operating_ conditions -analysys_ type . If you are i n min_max mode, the defaul t is bc_wc . single indicates that only one operating condi tion is to be used. Spec i fying either bc_wc or on_chip_variation switches to min_max mode and causes bo th min imum and maximum del ays t o be rea d fr om the SDF file . De l ays i n SDF are represented in the form of tripl ets (sdf_min:sdf_ typ : sdf_max). By default, the -analysis_type bc_wc I on_ chip_ variation option reads the sdf_ min and sdf_ maxdelays, respectively. To change this , use the -min_ type and -max_ type opt i ons. - min_file min_sdf_tile_name Use this opt ion only if the mi n imum and maxi mum de lays are in two separa te SDF files. Specifies the file from which mi nimum delay timing i nformation is to be read . The timing file must be in SDF format version vl.O, v2.0, v2.1 or v3.0. -max_file max_ sdf_ file_name Use this option only if the minimu m and maximum delays are in two separate Not supported yet. loa~delay] [-mi n _file min_file] Not supported yet. [ -max_file max_ file] Not supported yet. [-path path] Not supported yet. [-min_type sdf_min I sdf_typ sdf_max ] Not supported yet. [-max_t ype sdf min sd f_max ) Not supported yet. sdf_typ (-type s df min I sdf_type [- co nd_use cond_ use ] sdf max] Not supported yet. Not supported yet. 51 51 -path path_name Specifies the path from the current design to t he subdesign fo r which the timing file has been created. [-st r ip_path str ip_path] Not supported yet. [- syntax_only] SDF files. Specifies the file from which maximum delay timing information is to be read . The timing file must be in SDF format version vl . O, v2.0, v2.1 or v3.0. Not supported yet. [-quiet] Not supported yet. -type sdf mi n I sdf_typ I sdf_max Indicates which of the SDF triplet delay values are to be read fr om the SDF file. De lays i n SDF are represented in the form of triple t s (sdf_min : sdf_typ : sdf_max) . By default, read_ sdf reads the maximum delays sdf_ max . Note: If you use -type while in min/max mode (for example, if you use operating_conditions bc_bw I on_chip_variation ), a single value is annotated onto both min and max val ues of an arc. -m in_type sdf mi n I sdf_typ I sdf_max Specifies which of the SDF triple t de l ay values are to be read from t he SDF file for minimum delay. Delays in SDF are represented in the form of triplets (sdf_min : sdf_typ : sdf_max) . By defau lt, read_ sdf reads the minimum delay s sdf_min . Use this option onl y with option -analysis_ type bc_ wc I on_ chip_ variation. - max_typ e sdf_mi n I sdf_t yp I sdf_max Specifies which of the SDF triplet de lay values are to be read from t he SDF file for maximum delay . De l ays in SDF are represented in the form of triplets (sdf_min:sdf_typ : sdf_max) . By default , read_ sdf reads t he maximum delays sdt_max . Use this option only with option -analysis_ type bc_ wc I on_ chip_ variation. - cond use min I max I min max Use this option only if the SDF f ile includes some conditional de l ays using the SDF construct COND, and if the Synopsys library in use does not specify conditional delays . min indicates that the minimum o f a ll conditional delays is to be used to a nnotate the corresponding timing arc. max indicates to u se the maximum; min_max indicates min_rnax operating conditions; the minimum of all conditional delays is to be used for t he minimum operating condition, and t he ma x imum of all conditional delays is to be used for the maximum operating cond ition, You cannot use min_max with a single operating condition; you mus t be in min_max mode. - syntax_ only Indicates that no tim ing annota t ion is to be performed; syntax only is to be processed . Use this option to verify that your SDF syntax is correct and will not issue any error messages. - strip_path strip_path_name Speci fies a prefix path that is to be stripped from all SDF objects. Such a prefix path i s usually a result of generating an SDF file for a subdesign, and using th is subdes ign as the current design . - quie t Use this option to skip execut ion of report_ annotated_ delay and report_ annotated_ check after reading SDF. - worst Indicates that read_ adf is to annotate the current design only wi th delays worse than the current annotated delays; appli es to annota ted net and cell delays and ann otated tim i ng checks. The worst delay i s defined as the most pessimistic delay . Th i s means prirnetirne annotates the min of minima, and max of maxima values. sdf_file_name Speci f ies the file from which tim i ng informa t ion is to be read. The t iming f i l e must be in SDF fo rmat version vl.O, v2.0, v2 . 1 or v3.0. 52 52 read_vcd Command: read_vcd <string:name> The read_vcd command specifies the switching activity information generated by simu lation for use in power calculation. I nternally, non -VC O format switching activity i s converted to VCO . SYNTAX i n t read_ vcd [ - path prefix ] [ - s tr ip_path prefix ] [ - z er o_ de l ay] [ -pipe_ exec comma nd ] [ -ce l ls cell_ l i st ] [ - time time_ list] fi l e _ narne st r ing str ing str ing l is t l ist prefix fi l e _ name command ce l l _ l ist tirne_ list ARGUMENTS -path prefix Specifies a relative path from the current design to the hierarchical lowlevel design for which the VCD file has been created . By default, absolute path names a r e used. Use this option if the VCD file refers to an object in a hierarchy. Do not use this option if the VCD file refers to an absolute path. option: list required licenses --license display command help --help license: AP Command: read_verilog <string:filenames> reads Verilog files for linking option: do not perform additional -no check syntax/ semantic checking --get_option arg<l> get option value --set_option set option value --get_default arg <l > get default value --set default ... set default value --list_options list current option values --load_options load current option values list required licenses --license display command help --help description: This command parses Verilog files and build a net-list ready for 'link_design'. The net-list is not a design database and it will be removed after the link_design is done. -strip_path strip Specifies a path pref ix that is to be stripped from all t he object names read from the VCD file . This option is applied to strip the testbench / instance path from the VCD file. -zero_ delay Specifies the VCD file comes from a zero delay simulation . -pipe_exec command Specifies a shell command which is used to generate the VCD file file_ names. This option will invoke the command and directly pipe the output VCD file to PrimeTime-PX. In another word, the simulation and power analysis are in parallel run . No VCD disk file is generated at all. 53 53 - time time_ window_ value Specifies a time value in nanoseconds (ns) . If the time window is specified , power will be calculated only for the events happening within this time wi n dow . The user can specify as man y time periods as n ecessary ; however, the user must specify the beginning time of simu lation windows in increasing order . If the u ser does n ot know the end of simulation time, user can u se a n ega tive number in -time op tio n to indicate t h e end of simu la ti on . This option g ives the use r t h e flexi bi l ity to focu s o n t h e time window o f interest. - cells cel l _ li st Spe cifies t h e cell n ames or co l lections o f c el ls for whi ch power need to be calculated. 1"1/ithout t hi s option, Pr i meTime PX calculates power fo r t he whole des i g n. file_ n ame Specifies the switchin g acitivity file name to be read . If file_ name e nds with gzipped file, a compre ssed fi le, a VC D+ file, and a FSDB file, respective ly, otherwise it is assumed to be in t he VCD format. 54 54 read_veri log read_verilog Reads i n one or more Ver i log files . Reads the hierarchy and connectivity information of a design from a set ofVerilog files and builds a netlist ready for linking , that is, binding instances to modules and library cells using the link_ design Tel command. The actual design database is only created during the link_design step. lfthe Verilog netlist contains connections to pins that do not exist on the library cell, then these pins are automatically generated to the library cell and a warning is issued. This command automatically recognizes and reads Verilog files in GZIP format. SYNTAX Syntax st ring read_ verilog [-hdl _ compiler] f i l e_ n ames l ist f i l e_names read_verilog files \ ARGUMENTS where the arguments have the following meaning : -hdl _compiler Indicates that the Verilog files are to be read using the PrimeTime e .x ternal reader (p t xr) that uses HDL Compiler. Reading files in this way requires an HDL Compiler license while the read i s in progress. HDL Compiler supports the comp le t e Verilog language, but uses more CPU and memory than does the native PrimeTime Verilog reade r . fi le_names Spec ifies names of one or more f iles to be read. [ - no check) \ files Names of the Veri log files to read . Aprisa automatically recognizes and reads Verilog files in GZIP format. [ -no_ c h eck ] Do not perform additional syntax and semantic checki ng . Th is expedites the reading , but may cause fatal enrors down the road . Use this argument only if you read in Verilog files that have been previously checked . 55 55 redirect # Redirect output of a command to a file redirect Redirects the output of any Tel command to a user-specified file or to a Tel variable. The redirect command allows you to send the output to more than one destination, such as to the screen and a file using the -tee argument. If you do not want to tee the output, you can redirect the output via the standard Tel method as follows: c ommand [-append] [-tee] [- file] [-variable] (Append output to the file) (Tee output to the current output stream) (Output to a file (default)) (Output to a variable) > fil e Syntax redi r e ct t a r get c omman d \ [ - a ppend ] \ [ - t ee] \ [ - v ariable] \ [ - c ompres s] Or, to pass arguments to command: redi r ect targ et [c omman d comma nd option s) \ [-appe nd ] \ [-tee] [ - v ariabl e] \ [ -comp r e ss ] target command_string (Name of file / variable target for redirect) (Command to redirect. Should be in braces {}.) where the arguments have the following meaning: t arge t Name of the file to which to write the output, or, if the -variable argument is used. name of the Tel variable in which to store the output. command Name ofthe Tel command whose output you want to redirect. command_ opt ions Command options to command. [- app end ] Append output to the file instead of overwriting the file. [-t ee] Copy the output to the screen. [- variab l e ] Redirect output to a Tel variable instead otto a file. [- comp r ess ] Compress the output file. 56 56 remove_annotated_delay remove_annotated_delay Removes annotated d elay s f rom t he des i gn, either on s peci f i c cells or nets, between spec ific pins, or all a nnotated delays i n t he design. Removes the delay information on selected nets, ports, or pins that was loaded from an external timing tool. You may want to use this command to ensure only Aprisa-calculated delay information is used and no delays slipped in from an external source . SYNTAX Syntax s t ri ng remove_ annotated_delay remove_annotated_delay objects \ [ -from pin_or_port] \ [- to pin_or_port ] \ [-all] [-all ] [ - f rom from_list] to_list ] [ object_spec ] [- t o list l ist l is t from_ list to_ list object_ spec ARGUMENTS where the arguments have the following meaning : - all obj e cts Names of objects for which to remove the delay. [ - f rom pin_or_p or t] Indi cates tha t all a nnotated delays in the design are t o be removed. This option is e xc l usive of the -from , -to , and object_ spec op tions . Remove delay from the specified pin or port. [ - to pi n_ or_port] Remove delay to the specified pin or port. [ - a ll ] Remove all annotated delay. -from from_list Specifies a l ist of pin s or ports that a r e the startpoints of the timing arcs f or wh i ch anno t ated delays a re t o be removed . You canno t comb i ne t his op t i on with object_ spec. -to to_ list Specifies a l is t of pins or po rts that are the e ndpoints of the timing arcs f or which annotated delays are to be removed . You cannot combine thi s option v1ith objec t _ spec. ob j ect_ spec Speci fie s a list o f leaf cel ls or nets for which all annota t ed d elays are to be removed. You cannot combine this option with -from and - to . 57 57 remove annotated transition remove_annotated_transition Remove s p r evi ous l y-annotated transi t ion times from p i ns or por t s design . i n the curren t Removes the transition time information from the specified pins that was loaded from an external timing tool. You may want to do this to ensure only Aprisa-calculated transition time infonnation is used and no transition times slipped in from an external source. SYNTAX Syntax i n t remove_annotated_transition - all I pin_list remove_annotated_transition pin_list \ list [-all] pin_l ist ARGUMENTS where the arguments have the following meaning: - all Indicates that all a nno tated trans ition times in the design a r e to be removed . -all a n d pin_list are mutually exclusive; you must use one of these, bu t no t both. pin_ list Names of the pins for which to remove the annotated transition. [-all ] Remove all annotated pin transitions. pin_ list Speci f ies a lis t of pins or por ts from which annotated transition times are to be r emoved . -all and pin_ lis t are mutually e xclusive; you mu st u se one of these, but n ot both. 58 58 remove_capacitance remove_capacitance Removes cap ac itanc e on nets o r po rt s . Removes user-specified capacitances from ports and nets that were set using the set_foad Tel command. The real extracted capacitances will be used instead. SYNTAX Syntax s tr ing remove_ capacitance net_ or_port_ lis list net_ or_port_ list remove capacitance net_or_port_list where net_or_port_list is the names of the nets or ports for which to remove capacitances. ARGUMENTS net_ or_port_ l ist Specifies a list of ports and nets in the current design , whose capacitan ces are removed . 59 59 remove_case_analysis remove_case_analysis Removes the case analysis va lue on i npu t . Removes case analysis that was set using the set_case_analysis Tel command. Case analysis allows you to specify constant values for selected nets that are propagated through the design . SYNTAX Syntax st r ing remove_ case_ analysis port_ or_pin_ list li st port_ or_pin_ list remove_case_analysis objects where objects is the list of objects for which to remove case analysis. ARGUMENTS port_or_pin_list Lists ports or pins f o r which the case analysis entry is to be removed. 60 60 remove_ clock remove- clock Removes one or more c lo cks f rom t he c u r r ent design. Removes all or a selected set of clocks in the design. SYNTAX Syntax stri ng remove_clock - a l l l i st c lock_ l i s t I clock_ lis t ARGUMENTS remove_clock [cl ock_lis t ] \ [ - all ] were the arguments have the following meaning : -all Specifies to remove a l l clocks in the c u rren t des i g n . cl ock_ list Specifies a list of collections contai ning c l oc ks or patterns matching the clock names . [clock_ list ] List of clocks to remove. [ - all ] Remove all clocks. 61 61 remove_clock_gating_check remove_clock_gating_check Captures clock - gating checks . Disables all clock gating setup and hold timing checks related to the SOC constraints set with the set_clock_gating_check Tel command. This removal is permanent and is typically done after all the clock trees are generated. The timing analyzer still takes into account the clock gater cells , but their setup and hold constraints are assumed zero. Note that theta parameter, timing_disab/e_c/ock_gating_checks, disables all timing checks involving clock gater cells. For an MCMM design, if you specify the -all_ scenarios argument, the command applies to all scenarios regardless of the scenarios that are in the current session. Syntax SYNTAX string remove_clock_gating_check [-setup] [object_list] list object_list [-ho ld] [-rise] [-fa l l] [-high I - l ow ] ARGUMENTS remove _clock_gating_check \ -all I clock_ or_ clockPins \ [-all_scenar:ios] where the arguments have the following meaning: - setup -hold Indicates the remova l of the clock- ga t ing constraint on the hold t ime only . If you do not specify either t he -setup or -hold option , both setup and hold constraints are removed . clock or clockPins Collection of clocks or clock pins identifying the clocks for which to remove clock gating checks. -all Indicates the removal of the clock-gating constraint on the set up time only . If you do not specify ei the r t he -setup or -hold option, both setup and hold constraints are removed . Remove all clock gating checks for all clocks. -all scenarios Remove the constraints for all scenarios . Note that this argument is only applicable for an MCMM design when there is no work scenario set. - rise Indicates the removal of the clock-gating constaint on the rising d elays only. If you do not spec i fy e ither the - rise or -fall option, constraints on both rising and falli ng de l ays are removed. -fall Indicates the removal of the clock-gating constai n t on the falling delays only. I f you do not speci f y ei t her t he -rise nor -fall opt i on, c onst r aints on both ri sing and falling delays are removed . -high Remove the high specification from the obejct list , previously set up by set_clock_gating_check command . This option has to be either h igh or low .. 62 -low Remove the low s p ecification f rom the obejct list, previously set up by set_clock_gat i ng_check command. This option has to be either high o r low. ob jec t_list Spec i fi es a l ist of objects in the current design for which to remove the clock gat i ng check. The ob j ects can be clocks, ports, pins, or cells . I f you specify a cell, all input p i n s of that c ell are affected. If you do not specify any objects, the clock- gating check is removed fr om t he current design. 63 63 remove_ clock_grou ps Removes s peci fi c e x clusive or asynchro nou s clock gro ups f r om t he current d e sign . SYNTAX Bool ean remove_clock_groups - physica l ly_ exc l usive I - exc l usive - name name_list I -all list I - asynchr onous name_list ARGUMENTS Command: remove_clock_groups remove clock groups option: -all -name * -physically_exclusive -logically_exclusive -asynchronous --get_option arg<l> --set_option ... --get_default arg<l> --set_default ... --system_default --list_opt ions --load_options --license --help remove all clock groups clok group list physically exclusive logically exclusive asynchronous get option value set option value get default value set default value use system default values list curren t option values load current option values list required licenses display command help description: %remove_clock_groups -asynchronous -all -physically_ exclusive Specifies that groups set for physically exclus i ve clocks are to be removed . The -physically_ exclusive , -logically_ exclusive and -asynchronous options are mutually exclusive; you must choose onl y one. - logica l ly_exclusive Specifies t hat groups set for logica lly exclusive c lo c ks are to be removed . The -physically_ exclusive , -logically_ exclusive a n d -as ynchronous options are mutually exclusive; you must choose only one . - asynchronous Specifies that groups s e t for asynchronous c l ocks are to be removed . The physically_ exclusive , -logically_ exclusive and -asynchronous options are mutually exclusive ; you must choose only o n e. - name name_list Specifies a list of clock grou ps to be removed, which matches the groups i n the given names. You should use the set_clock_ groups command to predefine these names. Subst itute the list you want for name_list. The -name and - a l l options are mutually exclusive . -all Specifies to remove all groups set for exclusive or asynch r onous clocks in the current design. The -name and -all options are mutua l ly exclusive. 64 64 remove_ clock_ latency Removes clock lat e ncy in f o rmati on f rom specified objects . SYNTAX st r i ng remove_ clock_ latency [ - s ourc e ] (- cl oc k clock_ li s t] ob jec t _lis t list list clock_lis t objec t _l ist ARGUMENTS Command: remove_clock_latency [db:object_list] standard SOC command option: -source -all -offset -inc_delay -ocv --get_option arg<l> --set_option --get_default arg<l> --set_default ... --system_default --list_options --load_options -- license --help remove source latency remove all latency offsets remove latency offset remove incremental delay offset remove ocv latency get option value set option value get default value set default value use system default values list current option values load current option values list required licenses display command help description: This command is the same as standard SOC command. - source Specifies that clock source laten cy should be removed. -clock clock_list Removes any n etwork laten cy def i n ed on the pin/po rt objects i n obj ec t_l ist which refers t he clocks in clock_list from the design . If the -clock option is supplied when object_ list refer s to clock objects, a warn i n g is issued that the option is n ot relevant in this case a n d ex e cution of the command proceeds as if -clock was not given . This opti on does not remove a more g ener al latency sett i ng withou t any specific clock . obj e ct_ list Provides a list of c locks, por t s, or pins . 65 65 remove_clock_ sense Removes unatene s s information de fi ned on pins . SYNTAX st ring remove_clock_sense Command: remove_clock_sense <db:object_list> standard SOC command option: - all -clocks collection [ -all ) [ -clocks cloc k_list ] object_list list list clock_list ob ject_ list ARGUMENTS -clocks clock_list Optionally specifies a list of clock objects to be associated with the given pin ob ject s in object_l ist . If the -clocks opt i on is spec i fed, o nly t he unateness specified for that particular clock domain will be removed. Otherwise , unateness information for a l l c l ocks passing through the given pin objects wi l l be removed. The -clocks option can o nly remove clock sense predefined by set_ clock_ sense -clock. It does no t remove t he default clock sense setting for this given pin. --get_option arg<l> --set_option ... --get_default arg<l> --set_default ... --system_default --list_options --load_options --license --help remove all clock unateness from current design constraint applied to specified clocks only get option value set option value get default value set default value use system default values list current option values load current option values list required licenses display command help description: This command is the same as standard SOC command. -all Remove al l unateness i n format i on in current design . object_ list Lists of p i ns wi th predefined una teness to remove. 66 66 remove_clock_ uncertainty Removes c lock uncertain ty in f ormation p rev ious l y set by the set_clock_uncertainty command. Command: remove_clock_uncertainty [db:object_list] Remove clock uncertainty constraints. SYNTAX string remove_ clock_ uncertainty [ object_ list I - fr om trom_clock -rise f rom rise_trom_ clock - fall_from tall_trom_clock -to to_clock I -rise_ to rise_ to_ clock I - f all_to tall_to_cl ock] [ - ri se ] [-fall ] [-setup] [ - hold ] [object_ list ] l ist l i st list l i st l i st li st l i st trom_ clock rise_ from_ clock tall_from_clock rise_t o_ c l ock fall_to_clock to_clock object_ list option: -all -append - end -setup -hold -from collection -to collection --get_option arg<l> --set_option ... --get_default arg<l> --set_default ... --system_default --list_options --load_options - -license --help remove all uncertainty remove append uncertainty remove end uncertainty for setup only for hold only from clock to clock get option value set option value get default value set default value use system default values list current option values load current option values list required licenses display command help ARGUMENTS - from from_cloc k -to to_ clock These two options specify the source and d es t ination clocks for interclock uncertainty. You must specify either the pair of -from/-rise_ from/-fall _ from and -to/-rise_ to/-fall_ to , or object_list; you cannot specify both. description: Remove clock uncertainty constraints from design. - rise_from r~se_trom_clock Same as the -from option, but i ndicates that uncertainty applies on l y to rising edge of the sou rce clock . You can use only one of the -from , rise_ from , or -fall_ from options. Use -rise_ from i nstead of the obsolete option -from_ edge rise . - fa ll from tall_ trom_ clock Same as the -from option, but indicates that uncertain t y applies onl y to falling edge of the source clock. You can u se only one of t he -from , rise_ from , or -fall_ from options. Use -fall_ from i nstead of the obsolete option -from_ edge fall. -rise_to rise_to_clock Same as the - to option, but indicates that uncertainty applies only to r i sing edge of the destination clock . You can use onl y one of the - to , -rise_to , o r -fall_ to options . Use -rise_ to ins t ead of the obsolete option -to_ edge rise . 67 67 - fall to tall to_clock Same as the -to option, but indicates that uncertainty applies only to falling edge of the destination clock. You can use only one of the -to , -rise_ to , or - fall _ to opt i ons . Use - fall _ to instead of the obsolete option - to_ edge fall. object_list Speci fie s a list of clocks, ports, pins, or ce l ls f r om wh i ch uncertainty information is to be removed . You ca n use either the pai r of -from/-rise_ from/ -fall_ from and -to/-rise_ to/-fall_ to options or the object_ list option, but you cannot specify both ; they are mutually exclusive. -rise Specifies that uncertainty is to be removed fo r only the rising clock edge. By d efault, uncertainty is removed f or both rising and f all i ng clock edges . This option is valid only for interclock uncertainty, and is now obsolete. Unless you need this option for backward-compatibility, use -rise_to ins t ead. - fall Specifies that uncertainty is to be removed for only the falli ng c l ock edge. By defau lt, uncertainty is removed fo r both rising and fal l i ng clock edges. This op t ion is valid only for interclock uncer t ainty, and is now obsolete. Unless you need th is option for backward- compatibility, use -fall_ to instead. -setup Specifies that only se t up check uncertainty is to be removed. By default, both setup and hold check uncerta int ies are removed. -hold Specifies that only hold check uncertainty is to be removed. By default, both s etup and hold check uncer tainties are removed. 68 68 remove_configuration Command: remove_configuration Don't support. Removes a configura t ion f o r mu l ti - s c e n a r i o a n alysis . SYNTAX boolean remove_ configuration option: --license --help list required licenses display command help 69 69 remove_ data_check Removes speci f ied da t a- t o-da ta checks previ ous ly se t by se t _data_check. SYNTAX string remove_ data_ check {-from from_ object I - rise_frorn from_object I - f al l _from from_object} {-to to_object I - r ise_t o to_object I -fa l l _ to to_ object} [-se tup I -ho ld ] [-cloc k clock] objec t object object from_ object to_ object clock_ object ARGUMENTS -from tcom_objecc Specifies a pin or port in the current design as the related pin of the data to- da ta check to be removed. Both rising and falling checks are ra~ved. You r:~ust specify one of -fran, -rise_from , or -fall_from . Command: remove_data_check remove all data check constraints. option: -from collection -rise_from collection -fall_from collection -to collection -rise_to collection -fall_to collection -clock collection -setup -hold --get_option arg<l> --set_option --get_default arg<l> --set_default ... --system_default --list_options --load_options --license --help not supported yet not supported yet not supported yet not supported yet not supported yet not supported yet not supported yet not supported yet not supported yet get option value set option value get default value set default value use system default values list current option values load current option values list required licenses display command help description: remove all data check constraints. -to to_object Specifies a pin or port in the current design as the constrai ned pi n of the data-to-data check to be created. Both rising and falli ng checks are removed. You must specify one of -to , -rise_t o , or -fall_t o . -rise_f rom fr~~objecc Similar to the -.from option, but applies to only risi ng delays at the re lated pin. You must specify one of -from. - rise_from , or -fall_from. -fall_from from_object Silllilar to the - from option, but applies to only falling delays at the related pin. You must specify one of -from, -riae_from , or -fall_from . 70 70

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