Goodard v. Google, Inc.

Filing 127

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Goodard v. Google, Inc. Doc. 127 1 2 3 4 5 6 7 ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 William H. Manning (pro hac vice) E-mail: WHManning@rkmc.com Brad P. Engdahl (pro hac vice) E-mail: BPEngdahl@rkmc.com Jacob S. Zimmerman (pro hac vice) E-mail: JSZimmerman@rkmc.com Aaron R. Fahrenkrog (pro hac vice) E-mail: ARFahrenkrog@rkmc.com Robins, Kaplan, Miller & Ciresi L.L.P. 2800 LaSalle Plaza 800 LaSalle Avenue Minneapolis, MN 55402 Telephone: 612-349-8500 Facsimile: 612-339-4181 David E. Marder (pro hac vice) E-mail: DEMarder@rkmc.com Robins, Kaplan, Miller & Ciresi L.L.P. 800 Boylston Street, 25th Floor Boston, MA 02199 Telephone: 617-267-2300 Facsimile: 617-267-8288 John P. Bovich (SBN 150688) E-mail: JBovich@reedsmith.com Reed Smith LLP Two Embarcadero Center, Suite 2000 San Francisco, CA 94111 Telephone: 415-543-8700 Attorneys for Plaintiffs Advanced Micro Devices, Inc. and ATI Technologies ULC UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN FRANCISCO DIVISION ATTORNEYS AT LAW MINNEAPOLIS ADVANCED MICRO DEVICES, INC., et al., Plaintiffs, v. SAMSUNG ELECTRONICS CO., LTD., et al., Defendants. Case No. CV-08-0986-SI PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF Case. No. CV-08-0986-SI PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF Dockets.Justia.com 1 2 3 4 5 6 7 TABLE OF CONTENTS Page INTRODUCTION ........................................................................................................................... 1 ARGUMENT ................................................................................................................................... 1 I. II. CLAIM CONSTRUCTION LEGAL PRINCIPLES ........................................................... 1 THE CHENG '990 PATENT .............................................................................................. 2 A. B. Description of the Invention .................................................................................... 2 "Integrated Memory" Is a Limitation That Requires the Memory To Be Formed As a Single Integrated Circuit..................................................................... 3 1. 2. C. D. E. III. "Integrated Memory" Means a Memory Formed as a Single Integrated Circuit. ........................................................................................ 4 "Integrated Memory" Is a Limitation in Claim 20....................................... 5 ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IV. ATTORNEYS AT LAW MINNEAPOLIS AMD's Construction of "Burst Mode Operation" Is Taken Verbatim From the Patentee's Argument to Overcome Prior Art During Prosecution..................... 7 "Consecutive Addresses" Should Not Include a Limitation That Is Directly Contradicted by the Specification. ........................................................................... 9 AMD's Construction of "Enable / Disable" Is Correct Because It Does Not Import Limitations on Unrecited Sense Amplifiers. .............................................. 10 THE SAKAMOTO '893 PATENT.................................................................................... 13 A. Description of the Invention .................................................................................. 13 1. 2. 3. B. C. D. Insulated Gate Field Effect Devices........................................................... 13 Fabrication and Structure of MOSFETs .................................................... 14 Improvements Claimed by the '893 Patent................................................ 15 AMD Accepts Samsung's Construction of "Self-aligned to the Respective First and Second Opposed Sides of the Gate." ...................................................... 15 Samsung Accepts AMD's Construction of "The Depth of Said First and Second Impurity Regions." .................................................................................... 15 "Channel-free" Means "Without a Channel."........................................................ 15 THE PATEL '830 PATENT.............................................................................................. 17 A. B. Description of the Invention .................................................................................. 17 "Gate Electrode . . . Is Divided into a Plurality of Segments" Means the Segments Must Share a Common Doped Region. ................................................. 18 -iPLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF Case. No. CV-08-0986-SI 1 2 3 4 5 6 7 V. C. D. Two Structures Are "Electrically Connected Directly" if There Is No Active Device Between Them. .............................................................................. 20 The "Vcc Current Bus" Is Internal and Supplies Charge....................................... 23 1. 2. The Bus Is Internal to the Integrated Circuit.............................................. 23 The Bus Supplies Charge. .......................................................................... 24 E. A Gate Segment Is "Independently Connected Electrically" if It Has Its Own Connection. ................................................................................................... 24 THE PURCELL '434 PATENT......................................................................................... 25 A. B. C. Description of the Invention .................................................................................. 25 An "Arithmetic and Logic Unit" Must Be Capable of Performing Both Arithmetic and Logic Functions. ........................................................................... 26 A "Bus Coupling Said Carry Save Stage to Said ALU" Cannot Be Limited to a Direct Physical Path. ....................................................................................... 28 ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VII. VI. ATTORNEYS AT LAW MINNEAPOLIS THE PEDNEAU '200 PATENT........................................................................................ 29 A. B. Description of the Invention .................................................................................. 29 The '200 Intrinsic Record Does Not Exclude Addresses and Instructions from a "Data Pattern."............................................................................................ 30 THE ORR '879 PATENT .................................................................................................. 31 A. B. Description of the Invention .................................................................................. 31 Neither the "Control Panel" nor Any Other Term Limits the '879 Claims to a Personal Computer. ............................................................................................. 32 CONCLUSION .............................................................................................................................. 35 Case No. CV-08-0986-SI - ii - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Page Cases Baldwin Graphic Sys., Inc. v. Siebert, Inc., 512 F.3d 1338 (Fed. Cir. 2008).................................................................................. 2, 30, 33, 34 Broadcom Corp. v. Qualcomm, Inc., 543 F.3d 683 (Fed. Cir. 2008).............................................................................................. 13, 34 Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801 (Fed. Cir. 2002).................................................................................................. 5, 6 Cohesive Techs., Inc. v. Waters Corp., 543 F.3d 1351 (Fed. Cir. 2008)............................................................................................ 27, 34 Comark Commc'ns, Inc. v. Harris Corp., 156 F.3d 1182 (Fed. Cir. 1998).................................................................................................. 11 Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448 (Fed. Cir. 1998).................................................................................................... 1 Freescale Semiconductor, Inc. v. Promos Techs., Inc., 561 F. Supp. 2d 732 (E.D. Tex. 2008) ..................................................................................... 5, 6 Halliburton Energy Services, Inc. v. M-I LLC, 514 F.3d 1244 (Fed. Cir. 2008).............................................................................................. 1, 34 Hazani v. United States Int'l Trade Comm'n, 126 F.3d 1473 (Fed. Cir. 1997).................................................................................................... 9 Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379 (Fed. Cir. 2008).............................................................................................. 2, 27 Howmedica Osteonics Corp. v. Wright Med. Tech., Inc., 540 F.3d 1337 (Fed. Cir. 2008).................................................................................................... 2 IMS Tech., Inc. v. Haas Automation, Inc., 206 F.3d 1422 (Fed. Cir. 2000).................................................................................................... 6 Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111 (Fed. Cir. 2004)............................................................................................ 12, 19 Insituform Techs., Inc. v. CAT Contracting, Inc., 99 F.3d 1098 (Fed. Cir. 1996).................................................................................................... 20 Johns Hopkins Univ. v. CellPro, Inc., 152 F.3d 1342 (Fed. Cir. 1998).................................................................................................. 29 Merck & Co., Inc. v. Teva Pharms. USA, Inc., 347 F.3d 1367 (Fed. Cir. 2003).................................................................................................. 12 Merck & Co., Inc. v. Teva Pharms. USA, Inc., 395 F.3d 1364 (Fed. Cir. 2005).............................................................................................. 4, 12 N. Am. Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335 (Fed. Cir. 2005).................................................................................................... 8 N. Am. Vaccine, Inc. v. Am. Cyanamid Co., 7 F.3d 1571 (Fed. Cir. 1993)........................................................................................................ 5 Negotiated Data Solutions, LLC v. Dell, Inc., __ F. Supp. 2d __, 2009 WL 186180 (E.D. Tex. Jan. 16, 2009) ................................................. 6 TABLE OF AUTHORITIES ATTORNEYS AT LAW MINNEAPOLIS Case. No. CV-08-0986-SI - iii - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Nystrom v. TREX Co., 424 F.3d 1136 (Fed. Cir. 2005).................................................................................................. 27 Oatey Co. v. IPS Corp., 514 F.3d 1271 (Fed. Cir. 2008)........................................................................................ 2, 29, 35 Osram GmbH v. U.S. Int'l Trade Comm'n, 505 F.3d 1351 (Fed. Cir. 2007).................................................................................................... 2 Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)........................................................................................... passim Poly-America, L.P. v. GSE Lining Tech., Inc., 383 F.3d 1303 (Fed. Cir. 2004).................................................................................................... 6 Scanner Techs. Corp. v. ICOS Vision Sys. Corp., 365 F.3d 1299 (Fed. Cir. 2004).................................................................................................... 5 Southwall Techs., Inc. v. Cardinal IG Co., 54 F.3d 1570 (Fed. Cir. 1995)...................................................................................................... 7 SRI, Int'l v. Matsushita Elec. Corp. of Am., 775 F.2d 1107 (Fed. Cir. 1985).................................................................................................. 13 Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313 (Fed. Cir. 2002).................................................................................................... 2 Ventana Med. Sys., Inc. v. Biogenex Labs., Inc., 473 F.3d 1173 (Fed. Cir. 2006).................................................................................................. 34 V-Formation, Inc. v. Benetton Group SpA, 401 F.3d 1307 (Fed. Cir. 2005).............................................................................................. 2, 27 Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576 (Fed. Cir. 1996).............................................................................................. 19, 22 Voda v. Cordis Corp., 536 F.3d 1311 (Fed. Cir. 2008)........................................................................................ 2, 28, 34 ATTORNEYS AT LAW MINNEAPOLIS Case No. CV-08-0986-SI - iv - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 INTRODUCTION Plaintiffs Advanced Micro Devices, Inc. and ATI Technologies ULC (collectively "AMD") have accused Defendants Samsung Electronic Co., Ltd., Samsung Semiconductor, Inc., Samsung Austin Semiconductor, LLC, Samsung Electronics America, Inc., Samsung Telecommunications America, LLC, Samsung Techwin Co., Ltd., and Samsung Opto-Electronics America, Inc. (collectively "Samsung") of infringing seven AMD patents: U.S. Patent Nos. 5,559,990 ("'990"), 5,248,893 ("'893"), 4,737,830 ("'830"), 5,545,592 ("'592"), 5,623,434 ("'434"), 5,377,200 ("'200"), and 6,784,879 ("'879"). Six of those seven patents (all except '592) now are before the Court for construction of claim terms. AMD's '990, '893, and '830 patents relate to memory. The '434 and '200 patents disclose and claim improved technology for processors. Finally, the '879 patent claims a processing unit and programming instructions for a valuable graphical user interface for controlling video in electronic devices. AMD submits that each claim term at issue should be given the scope reflected in the claim language, unless the intrinsic record explicitly and unambiguously puts those of skill in the art on notice that a term has a more limited or more expansive scope. AMD respectfully requests that the Court construe each term according to AMD's proposed construction. ARGUMENT I. CLAIM CONSTRUCTION LEGAL PRINCIPLES Claim construction is a matter of law for the Court. Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1456 (Fed. Cir. 1998). The inquiry begins with the words of the claims themselves. Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005). The use of the terms in the context of the claims "can be highly instructive." Id. Claim differentiation raises a presumption that the construction of terms should not result in claims with identical scope. Halliburton Energy Services, Inc. v. M-I LLC, 514 F.3d 1244, 1251 n.3 (Fed. Cir. 2008). Terms that appear in multiple claims generally should be given the same meaning. Phillips, 415 F.3d at 1314. The specification provides context for claim construction, but preferred embodiments from the specification should not be read into the claims without an express definition or Case. No. CV-08-0986-SI ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS -1- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 disclaimer in the intrinsic record. Phillips, 415 F.3d at 1316, 1323. To disclaim claim scope, the specification must use "words of manifest exclusion," Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313, 1325-26 (Fed. Cir. 2002), or "unequivocally preclude" embodiments that otherwise would be within the ordinary meaning of the claim terms. Baldwin Graphic Sys., Inc. v. Siebert, Inc., 512 F.3d 1338, 1346 (Fed. Cir. 2008). A definition of a claim term in the specification must clearly reflect an intent to limit the claims. Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381 (Fed. Cir. 2008). A proposed construction that excludes all preferred embodiments from the claims generally cannot be correct. Oatey Co. v. IPS Corp., 514 F.3d 1271, 1277 (Fed. Cir. 2008). The purpose or objective of the invention also may be considered. Osram GmbH v. U.S. Int'l Trade Comm'n, 505 F.3d 1351, 1358 (Fed. Cir. 2007). Specifically, a claim term should not be construed in a way that contradicts or defeats the purpose of the invention. Id. Statements made by the applicant during prosecution may rise to the level of a disclaimer if they expressly and clearly exclude embodiments from the scope of the claims. Voda v. Cordis Corp., 536 F.3d 1311, 1321 (Fed. Cir. 2008). The Court may consider prior art cited during prosecution as part of the intrinsic record to provide context for the meaning of terms in the art. V-Formation, Inc. v. Benetton Group SpA, 401 F.3d 1307, 1311 (Fed. Cir. 2005). Expert testimony and dictionary definitions may assist the Court in understanding how one of ordinary skill in the art would understand the claim terms. Phillips, 415 F.3d at 1318. Inventor testimony, however, generally does not carry weight for claim construction. Howmedica Osteonics Corp. v. Wright Med. Tech., Inc., 540 F.3d 1337, 1347 (Fed. Cir. 2008). II. THE CHENG '990 PATENT A. Description of the Invention ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS The Cheng '990 patent describes improvements to computer memory. Memory in a computer stores and provides data to a processor or other device that requests it. Declaration of Andrew Wolfe ("Wolfe Decl.") 18. The '990 patent describes a memory with dedicated circuitry for each of its subarrays that enhances the performance of memory by providing for (1) high-performance burst modes, and (2) selective enabling of sense amplifiers. Id. Case No. CV-08-0986-SI -2- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 Generally, memory is comprised of an array of memory locations divided into rows and columns, and circuitry such as registers, decoders, and sense amplifiers for accessing these locations. Id. The registers and decoders are responsible for processing the address of a data request to identify its location in the array. Id. The sense amplifiers "amplify" the contents of that location for output from the sense amplifier, and eventual output to the requesting device. Id. The array and the circuitry can be formed as a single integrated circuit or as a plurality of integrated circuits. Id. Some claims of the '990 patent improve memory performance by dividing the array of memory locations into a plurality of subarrays, each with circuitry dedicated solely to it. Thus, each subarray has its own set of registers, decoders, sense amplifiers and other circuitry. Because each subarray has dedicated circuitry, each subarray can act independently but in coordination with another subarray to provide two significant performance enhancements. First, the dedicated circuitry provides for high-performance burst modes that can output data more quickly than traditional burst modes. While some claims require a high-performance burst mode, others do not. The dedicated circuitry also provides for selective sense amplifier enablement: while some sense amplifiers are enabled to output data, others are disabled. Because sense amplifiers consume large amounts of power, this feature of the '990 patent results in significant power savings. Again, some claims require structure for selectively enabling sense amplifier enablement while others do not. B. "Integrated Memory" Is a Limitation That Requires the Memory To Be Formed As a Single Integrated Circuit. "Integrated memory" (asserted claims 20, 22-23) AMD's Construction "A memory fabricated in a single integrated circuit." Samsung's Construction This is part of the preamble and is not a limitation. Were a construction required, the proposed construction is: "A memory containing one or more integrated circuits." -3PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS Case No. CV-08-0986-SI 1 2 3 4 5 6 7 AMD has proposed "integrated memory" for construction. The term "integrated memory," which appears in the preamble to claim 20, is a limitation of the claim that means "a memory fabricated in a single integrated circuit." Samsung argues that the phrase is not a limitation and, although Samsung agrees the term relates to integrated circuits, that it should be construed as a memory containing one or more integrated circuits. Thus, the issues for the Court are: (1) does the term "integrated memory" mean a memory fabricated in a single integrated circuit; and (2) is "integrated memory" a limitation on claim 20. The answer to each of these questions is "yes." 1. "Integrated Memory" Means a Memory Formed as a Single Integrated Circuit. The '990 patent claims demonstrate that the patentee intended "integrated circuit" and "integrated memory" to mean a single integrated circuit. See Phillips, 415 F.3d at 1314 ("Differences among claims can also be a useful guide in understanding the meaning of particular claim terms."). Claim 1 of the '990 patent recites "a memory." Claim 6 recites "[t]he memory of claim 1 wherein the memory is fabricated in an integrated circuit." Claims 8 and 14 read similarly. As a result, the memory in claims 1 and 8 encompasses memory fabricated in one or more integrated circuits, whereas the memory in claims 6 and 14 encompasses only memory fabricated in one integrated circuit. Wolfe Decl. 26. The "integrated memory" of claim 20 must also encompass only memory fabricated in one integrated circuit in order to give meaning to all terms in the claim. See Merck & Co., Inc. v. Teva Pharms. USA, Inc., 395 F.3d 1364, 1372 (Fed. Cir. 2005) ("Merck II") (observing that constructions giving meaning to all terms of a claim are preferred). Because the "memory" of claim 1 can be one or more integrated circuits, the "integrated memory" of claim 20 must mean something else; otherwise the term "integrated" is superfluous. In this case, "integrated memory" means memory fabricated in a single integrated circuit. The specification provides further support for this conclusion, stating: "some embodiments are not integrated into one integrated circuit." '990 at 13:7-10 (emphasis added) ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS Case No. CV-08-0986-SI -4- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 (Ex. A).1 The specification also refers to "the" integrated circuit. Id. at 7:16-18. Thus, when the patent limits claim scope to memories fabricated in an integrated circuit, it means "one integrated circuit." See Freescale Semiconductor, Inc. v. Promos Techs., Inc., 561 F. Supp. 2d 732, 749 (E.D. Tex. 2008) (holding that "an integrated circuit" meant "a single integrated circuit" where patentee indicated that the invention was implemented in a "single integrated circuit"). Thus, the patentee here has indicated that "integrated circuit" and "integrated memory" mean "one integrated circuit." '990 at 13:7-10 (Ex. A). The general presumption that the "indefinite article `a' or `an' in patent parlance carries the meaning of `one or more'" arises from the "use of the transition `comprising' in conjunction with the article `a' or `an.'" Scanner Techs. Corp. v. ICOS Vision Sys. Corp., 365 F.3d 1299, 1305-06 (Fed. Cir. 2004). In the absence of the transition "comprising," one must look to the specification for some indication that the patentee "intended it to have other than its normal singular meaning." N. Am. Vaccine, Inc. v. Am. Cyanamid Co., 7 F.3d 1571, 1575-76 (Fed. Cir. 1993) (emphasis added) (holding that "a" did not mean "one or more" in claim without transition "comprising"). No such indication exists here. The intrinsic record consistently supports the presumption that the article "a" or "an" should be given its "normal singular meaning." Id. Thus, to give meaning to all claim terms and to the specification's descriptions of embodiments of the invention, "integrated memory" must mean a memory fabricated in a single integrated circuit. 2. "Integrated Memory" Is a Limitation in Claim 20. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS In claim 20, "integrated memory" is used intentionally and adds important structure to the claim. Catalina Mktg. Int'l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808-09 (Fed. Cir. 2002) (explaining that preamble that does more than merely describe structurally complete invention limits claim). As shown above, comparison of the preambles to independent claims 1 and 8 on the one hand and claim 20 on the other establishes that "integrated memory" means a memory fabricated in a single integrated circuit. Also, the addition of "integrated" signifies to one of ordinary skill that the "integrated memory" of claim 20 requires the memory to be fabricated in a Citations to "Ex. __" refer to exhibits attached to the Declaration of Aaron R. Fahrenkrog in Support of Plaintiffs' Opening Claim Construction Brief, submitted with this brief. Case No. CV-08-0986-SI 1 -5- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 single integrated circuit, whereas the "memory" of claims 1 and 8 does not. Wolfe Decl. 27. "Integrated memory" is not merely a descriptive name given "to the set of limitations in the body of the claim that completely set forth the invention." IMS Tech., Inc. v. Haas Automation, Inc., 206 F.3d 1422, 1434 (Fed. Cir. 2000). The body of claim 20 does not completely set forth the invention: "integrated" does not appear anywhere other than the preamble, and the claim elements could be found in a combination of one or more integrated circuits. Wolfe Decl. 27. Thus, a single integrated circuit is not inherent to the remaining claim elements. Id. Instead, "integrated memory" is the structure in which the claimed limitations must be present. Freescale, 561 F. Supp. 2d at 749. "Integrated memory" is "a fundamental characteristic of the claimed invention that is properly construed as a limitation of the claim itself." Poly-America, L.P. v. GSE Lining Tech., Inc., 383 F.3d 1303, 1310 (Fed. Cir. 2004). The specification explains that whether the claimed memory is formed as a single integrated circuit is an important structural feature of the invention. The specification states that "some embodiments are not integrated into one integrated circuit." '990 at 13:7-10 (Ex. A); see Catalina Mktg., 289 F.3d at 808 ("[W]hen reciting additional structure or steps underscored as important by the specification, the preamble may operate as a claim limitation."); Negotiated Data Solutions, LLC v. Dell, Inc., __ F. Supp. 2d __, 2009 WL 186180 at *18-19 (E.D. Tex. Jan. 16, 2009) (finding "integrated circuit" provided limiting structure when used in preamble to a claim); Freescale, 561 F. Supp. 2d at 749 (same). Furthermore, one of the preferred embodiments in the '990 patent is specifically identified as an integrated circuit. '990 at 7:8-18 (Ex. A). See Negotiated Data, __ F. Supp. 2d at *18 (noting that patentee uses "integrated circuit" to "describe the preferred embodiment"). "Integrated memory" is a claim limitation. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS Case No. CV-08-0986-SI -6- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 C. AMD's Construction of "Burst Mode Operation" Is Taken Verbatim From the Patentee's Argument to Overcome Prior Art During Prosecution. "Burst mode," "Burst mode operation," and "Burst mode read operation" (asserted claims 1-14, 20, 22-23) AMD's Construction For "burst mode" (claims 1, 8, 20): "A serial transfer mode in which a memory transfers the contents of a plurality of locations in response to the address of one location." For "burst mode operation" and "burst mode read operation" (claims 8, 20): "A serial transfer in which the contents of a plurality of locations are provided in response to the address of one location." Samsung's Construction For "burst mode," "burst mode operation" and "burst mode read operation" (claims 1, 8, 20): A mode for sequentially accessing memory locations in which the memory receives the address of one memory location and provides in response the contents of a plurality of consecutive memory locations. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS AMD's constructions of the phrases "burst mode," "burst mode operation," and "burst mode read operation" are correct because they are based on an argument the patentee made to the examiner in an attempt to overcome prior art. Samsung, which proposed these phrases for construction, also draws its proposed construction from the intrinsic record. Samsung's construction is incorrect, however, because it is taken from a general, less-probative statement, and is open to an interpretation that does not comport with the claims or the specification. "Arguments and amendments made during the prosecution of a patent application and other aspects of the prosecution history . . . must be examined to determine the meaning of terms in the claims." Southwall Techs., Inc. v. Cardinal IG Co., 54 F.3d 1570, 1576 (Fed. Cir. 1995). AMD's construction of "burst mode" is taken verbatim from a patentee argument in the '990 patent file history. The patent examiner initially rejected claims in the '990 patent as being anticipated by U.S. Patent No. 4,636,986. Office Action, Jan. 26, 1995, at 3 (Ex. G). The examiner stated that "burst mode . . . as claimed in the instant invention . . . is nothing more than a beginning mode address and an ending address which is equivalent to a serial transfer2 of A serial transfer outputs several memory locations one at a time. Wolfe Decl. 31. In contrast, a block transfer outputs several memory locations simultaneously. Id. Case No. CV-08-0986-SI 2 -7- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 information of which the reference teaches burst mode transfer to the extent of the claims." Id. (footnote added). In arguing to overcome the rejection, the patentees asserted that "burst mode . . . is not any serial transfer but a serial transfer in which the contents of a plurality of locations are provided in response to the address of one location." Amendment, Apr. 27, 1995, at 4 (emphasis added) (Ex. H). Because the patentee used the exact same language in arguing for patentability, AMD's construction defines what "burst mode" means in the context of the '990 patent. See, e.g., N. Am. Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335, 1344-46 (Fed. Cir. 2005) (holding that arguments made during prosecution to overcome prior art can both limit claim scope and override general rules of claim construction); Wolfe Decl. 32. Samsung's construction was not presented as an argument in response to a rejection but instead was lifted from a general description contained in the introductory section to the patentee's appeal brief. Appeal Brief, Sept. 27, 1995, at 2 (Ex. I). As such, it is to be accorded little probative effect as to the meaning of the term. Furthermore, Samsung's proposed construction is at odds with the '990 patent claims. Samsung's proposed construction calls for the memory to output a plurality of "consecutive memory locations." The phrase "consecutive memory locations" is not found in any claim. Instead, the claims refer to "consecutive addresses." To the extent that Samsung's construction suggests physically consecutive memory locations, it is unsupported by the claims and contradicted by the specification of the '990 patent. '990 at 2:16-37; claims 1, 8, 20 (Ex. A). ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS Case No. CV-08-0986-SI -8- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 D. "Consecutive Addresses" Should Not Include a Limitation That Is Directly Contradicted by the Specification. "Consecutive addresses" (asserted claims 1-14, 20, 22-23) AMD's Construction "Consecutive addresses" and its variations need no construction and should be given their ordinary meaning. For "consecutive addresses" (claims 1, 8, 20): "Addresses following one after the other in order." For "memory locations L1, . . . Ln" (claim 8): "Locations corresponding to addresses following one after the other in order." For "locations L1 and L2" (claim 1): "Two locations corresponding to addresses following one after the other in order." These terms need no construction and should be given their ordinarily understood meaning because the specification does not indicate that they are used in a unique or special way. Hazani v. United States Int'l Trade Comm'n, 126 F.3d 1473, 1480 (Fed. Cir. 1997). Alternatively, AMD's construction is proper because it is consistent with the intrinsic record. Indeed, Samsung, which has proposed the phrases for construction, agrees that "consecutive" means "following one after the other in order." Samsung adds a vague "wherein" clause that imposes limitations that are directly contradicted by the specification. Samsung's added limitation that "each memory location represents a cell that is associated with a single address" contradicts the specification's statement that, "[i]n some embodiments, each memory location M-i includes several memory cells, for example, eight cells as in FIG. 5." '990 at 6:10-12 (Ex. A). In the context of this patent, a cell is only one bit of memory. Wolfe Decl. 36. The specification further explains that the memory described in FIGS. 8-28 incorporates 8-bit memory locations. '990 at 7:5-10 (Ex. A). Thus, Samsung's requested limitation that each memory location has only one cell cannot be correct. Samsung's proposed construction also contains the limitation that the addresses proceed Case No. CV-08-0986-SI Samsung's Construction "Consecutive addresses" and its variations require construction. For "consecutive addresses," "memory locations L1, . . . Ln," and "locations L1 and L2" (claims 1, 8, 20): A set of addresses following one after the other in order from L1 to Ln wherein each memory location represents a memory cell that is associated with a single address. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS -9- PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 from L1 to Ln. This limitation is wrong because claim 20 does not refer to any particular set of locations, and claim 1 refers only to the addresses L1 and L2. The limitation also is incompatible with claim 1. Changing claim 1's limited set L1 to L2, to the unlimited set L1 to Ln, improperly narrows the claim scope. Claim 1 recites limitations that apply to L1 and L2, but Samsung's construction requires those limitations to apply to the unlimited set L1 to Ln. Accordingly, the construction of "consecutive addresses" is "addresses following one after the other in order." E. AMD's Construction of "Enable / Disable" Is Correct Because It Does Not Import Limitations on Unrecited Sense Amplifiers. "Enabling" and "Disabling" of "Sense Amplifiers" (asserted claims 3, 8, 23) AMD's Construction For "sense amplifiers . . . are enabled/disabled" (claim 3): "Sense amplifiers are enabled when they are selected to develop a signal on their outputs, and are disabled when they are not selected to develop a signal on their outputs." For "control circuit for selectively enabling / "control circuit enables" (claims 8, 23): "a circuit that selects sense amplifier circuits to develop a signal on their outputs" Samsung's Construction For "sense amplifiers . . . are enabled/disabled" / "control circuit enables" (claims 3 and 23): Developing a signal on the output of a sense amplifier only when it is transferring data from its output to the memory output, and not developing a signal on the output of a sense amplifier when data is being transferred from a memory location to the sense amplifier. For "control circuit for selectively enabling" (claim 8): Developing a signal on the output of a sense amplifier only when it is transferring data from its output to the memory output or developing a signal on the outputs of a predetermined number of sense amplifiers whose outputs are to be transferred to the memory output immediately after the currently enabled sense amplifier transfers its data to the memory output, and not developing a signal on the output of the remaining amplifiers to which data is being transferred from memory locations to the sense amplifiers. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS Samsung selected these phrases for construction as a single term. Accordingly, AMD's constructions of these phrases focus on the element common to each: enabling and disabling sense amplifiers. A sense amplifier is enabled when it is selected to develop a signal on its output; it is disabled when it is not selected to develop a signal on its output. This construction Case No. CV-08-0986-SI - 10 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 applies consistently across all claims. In contrast, Samsung proposes unacceptably vague constructions that narrow claim scope and exclude a preferred embodiment. Thus, the Court must decide whether to adopt a construction that restricts the enable/disable status of sense amplifiers that the claims intentionally do not restrict. "The appropriate starting point . . . is always with the language of the asserted claim itself." Comark Commc'ns, Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998). The relevant portions of claims 3, 8, and 23 yield the following straightforward results: Claim 3 Language "[T]he sense amplifiers from which the contents of said location L1 are being transferred are enabled . . ." "[T]he sense amplifiers to which the contents of said location L2 are being transferred are disabled . . ." Sense Amplifier (SA) Status The SA for location L1 is enabled. ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW The SA for location L2 is disabled. MINNEAPOLIS The claim places no restrictions on any other sense amplifiers: they could be all enabled, all disabled, or some enabled and some disabled. Claim 8 Language "[S]aid control circuit enables a sense amplifier circuit whose output signals are being transferred to the output of said memory but . . ." "[S]aid control circuit does not enable all said sense amplifier circuits at the same time." Sense Amplifier (SA) Status The control circuit enables at least the SA providing data to the memory output. The control circuit disables at least one SA not selected to provide data to the memory output. The claim places no restrictions on any other sense amplifiers: they could be all enabled, all disabled, or some enabled and some disabled. Claim 23 Language "[T]he control circuit enables the sense amplifier circuit selected to provide data to the memory output and . . ." "[T]he control circuit . . . at the same time disables one or more sense amplifier circuits Case No. CV-08-0986-SI Sense Amplifier (SA) Status The control circuit enables at least the SA selected to provide data to the memory output. The control circuit disables at least one SA not selected to provide data to the memory PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF - 11 - 1 2 3 4 5 6 7 not selected to provide data to the memory output." output. The claim places no restrictions on any other sense amplifiers: they could be all enabled, all disabled, or some enabled and some disabled. Although each claim uses slightly different phrasing, the results are the same: during a burst mode operation at least one sense amplifier is enabled, at least one sense amplifier is disabled, and the claims do not include limitations regarding the existence or status of any other sense amplifiers. That is consistent with the specification and a preferred embodiment detailed by the patentee. '990 at 5:49-61 (Ex. A); see Merck & Co., Inc. v. Teva Pharms. USA, Inc., 347 F.3d 1367, 1371 (Fed. Cir. 2003) ("Merck I"). AMD's constructions preserve the selective enabling and disabling of sense amplifiers as described in the claims. AMD construes only what is necessary: what it means to enable and disable sense amplifiers. AMD does not construe more because the remaining claim language is clear on its face, and doing so would render portions of that language redundant. See Merck II, 395 F.3d at 1372 (preferring constructions that do not render claim terms superfluous). That AMD's constructions apply consistently across claims 3, 8 and 23 verifies the correctness of this approach. Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111, 1119 (Fed. Cir. 2004). AMD's constructions are also correct because they come from the specification. See Phillips, 415 F.3d at 1316 (observing that "the specification necessarily informs the proper construction of the claims"). The specification states: "[w]hen line 350.L-i is low, the sense ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS amplifier circuit 350.L-i is enabled to develop the signal on its output." '990 at 11:24-26 (emphasis added) (Ex. A). Enablement occurs when the sense amplifier is selected: the specification explains that sense amplifiers are enabled to allow them "sufficient time to develop their output signals" before transferring data. Id. at 5:50-54. Because a sense amplifier can have only two states, enabled or disabled, a sense amplifier is disabled when it is not selected to develop a signal on its output. Wolfe Decl. 38. Placed in claims 3, 8 and 23, AMD's constructions do not alter the effects of the claim Case No. CV-08-0986-SI - 12 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 language shown in the tables above: during a burst mode operation at least one sense amplifier is enabled, at least one sense amplifier is disabled, and the existence of or status required for any other sense amplifiers is unrestricted. In contrast, Samsung's constructions narrow claims 3, 8 and 23 by (1) adding limitations found nowhere in the patent, and (2) importing limitations from other claims. See Broadcom Corp. v. Qualcomm, Inc., 543 F.3d 683, 689 (Fed. Cir. 2008) (observing that it is improper to limit claim to unclaimed features); SRI, Int'l v. Matsushita Elec. Corp. of Am., 775 F.2d 1107, 1122 (Fed. Cir. 1985) (finding that it is error as a matter of law to import limitations from one claim into another). Samsung's constructions require certain sense amplifiers to be enabled or disabled, when the claims do not restrict the status of those sense amplifiers. Such limitations contradict the claim language and exclude an embodiment detailed in the specification. '990 at 5:45-61 (Ex. A). Samsung also imports limitations from at least one dependent claim into an independent claim. Consequently, Samsung's constructions cannot be correct. III. THE SAKAMOTO '893 PATENT A. Description of the Invention 1. Insulated Gate Field Effect Devices ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS The '893 patent relates to insulated gate field effect devices (also known as Metal Oxide Semiconductor Field Effect Devices, or "MOSFETs"). MOSFETs function as transistors in integrated circuits. Declaration of Jack Lee ("Lee Decl.") 8. In integrated circuits, a MOSFET can operate as a switch, being "on" when current is able to pass through it from the source to the drain, and "off" when no current should pass through. Lee Decl. 10. A useful analogy is to compare a MOSFET to a water spigot. The "source" is the pipe leading to the spigot, the drain is the water outlet from the spigot, and the gate is the valve that turns the water on or off. When the spigot (or gate) is turned off, no water (or current) flows through the device. Id. An example of a MOSFET is shown in Figure 9 of the patent. Paragraph 9 of the Lee Declaration depicts a colored version of Figure 9 with additional labels. The key components include the source and drain, which are found in the substrate of the integrated circuit, an insulating layer formed on the substrate, and a gate formed on the insulating layer. Case No. CV-08-0986-SI - 13 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 2. Fabrication and Structure of MOSFETs A process called "doping" plays a key role in MOSFET fabrication. Doping refers to the process of treating parts of the integrated circuit with various chemicals, known as "impurities," to increase the number of charge carriers. Lee Decl. 11. N-type doping increases the number of one type of charge carrier (electrons), whereas P-type doping increases the number of a different type of charge carrier (holes). Id. In the example MOSFET shown in Lee Decl. 9, the gate, source and drain have P-type doping, whereas the substrate beneath the gate and between the source and drain has N-type doping. The area at the border between the source/drain and the substrate becomes depleted of carriers (such as holes) that can carry current from the source to the drain. Lee Decl. 12. Similarly, the area at the border between the gate and the substrate also becomes depleted of carriers. Id. These areas without carriers are known as "depletion zones." Id. These zones are identified in the figure at Lee Decl. 9. These depletion zones prevent current from flowing from the source to the drain. Lee Decl. 12. The transistor is in an "off" state because there is no channel between the source and the drain through which the current can flow. Id. In other words, the transistor does not conduct current. Id. The transistor is "on" when current can flow from the source to the drain. Lee Decl. 13. To accomplish this, voltage is applied to the gate and drain. Id. This "operating voltage" creates two electric fields. Id. One field (a vertical field) pulls carriers to the surface of the substrate under the insulation layer. Lee Decl. 13-14 (description and figure illustrating vertical field). These carriers can carry current, but need a second force to pull them in either direction. Lee Decl. 13. This force is provided by the second electric field, a horizontal field that pulls current from the source to the drain. Lee Decl. 13-15 (description and figure illustrating horizontal field). Carriers are pulled to an area near the gate and between the source and drain, known as a "channel." Lee Decl. 16, 18 (description and figure illustrating channel). The channel disappears near the drain. Lee Decl. 16. However, carriers (and therefore current) can make it through to the drain because the area without a channel is very small and the horizontal electric field is very strong. Id. The area without a channel that can conduct current when the transistor Case No. CV-08-0986-SI ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS - 14 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 is turned "on," even though the channel disappears, is known as a "pinch-off region," (Lee Decl. 16), and is identified as "Lg1." '893 at Fig. 4 (Ex. B); see also Lee Decl. 9. 3. Improvements Claimed by the '893 Patent The '893 patent claims a MOSFET with a particular structure. Specifically, it includes a recessed, or concave, area where the insulating layer and gate dip down into the substrate. '893 at 6:1-9 (Ex. B). The recessed area is curved at least in part. Id. at 6:21-27. Figure 4 depicts an embodiment of the claimed transistor. A colored version with additional labeling is found at Lee Decl. 18. The claimed invention dramatically improves MOSFETs by making the effective channel length longer. '893 at 4:3-37 (Ex. B). Thus, MOSFETs can be made smaller without some of the negative side effects presented by shrinking the distance between the source and drain. Lee Decl. 17. B. AMD Accepts Samsung's Construction of "Self-aligned to the Respective First and Second Opposed Sides of the Gate." AMD accepts Samsung's proposed construction. Accordingly, the claim term "selfaligned to the respective first and second opposed sides of the gate" shall now mean "formed by a process in which the gate is used as a mask during source and drain implantation." C. Samsung Accepts AMD's Construction of "The Depth of Said First and Second Impurity Regions." Samsung accepts AMD's proposed construction. Accordingly, the claim term shall now mean "the depth of the source and drain regions." See Ex. P. D. "Channel-free" Means "Without a Channel." ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS "Channel-free region" and "Channel-free zone" (asserted claims 1, 2, 4) AMD's Construction "The terms `channel-free region' and `channel-free zone' refer to areas where there is no channel." Samsung's Construction "A portion of the substrate without an inversion region/zone and that conducts current." The crux of this dispute is whether the channel-free area must conduct current. The parties also disagree whether "channel-free" areas should be described in simple terms as areas Case No. CV-08-0986-SI - 15 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 without a channel (as AMD urges) or by introducing additional jargon regarding "inversion regions" (as Samsung urges). AMD's construction is simple, readily understood by a jury, and reflects ordinary meaning. As a matter of plain English, "channel-free regions" and "channel-free zones" refer to areas where there is no channel. The specification uses "channel-free" in a manner that is consistent with the common, ordinary meaning. Figure 9 identifies an area of the substrate labeled as "Lg1" as a "channel-free length." '893 at 3:24-26; Fig. 9 (Ex. B). In the text of the specification corresponding to this figure, it states that "between one end of the channel region 13 and the drain 5, there is a region of a length Lg1 without a channel being formed therein." Id. at 2:6-8 (emphasis added). Thus, the specification equates the term "channel-free" with being "without a channel." Samsung apparently agrees that the area in question is without a channel (although it refers to the area as being without an "inversion region") but incorrectly adds the words "that conducts current" to the end of its construction. By requiring that the channel-free area conduct current, Samsung limits the scope of the claims to transistors in the turned-on state. As explained above, there is a small channel-free area in the turned-on state that conducts current (also known as a "pinch-off region"). See pp. 14-15, supra. Samsung excludes the turned-off state, where the channel-free region (the entire area beneath the gate and between the source and drain) does not conduct current, from the scope of the claims. See p. 14, supra. Samsung's narrow construction is inconsistent with the claims. See Phillips, 415 F.3d at 1312 (describing primacy of claim language in claim construction). In particular, claim 4 recites a "channel-free zone" that develops when the transistor is "in the turned off state." '893 at 6:1320 (Ex. B). In other words, claim 4 specifically includes the area under the gate and between the source and drain that does not conduct current when the transistor is turned off. Therefore, the term "channel-free" cannot be limited to an area that exists only in a transistor that is turned on. Nothing in the intrinsic record undermines or disclaims the plain language of claim 4. The specification describes the pinch-off region in the "on" state of the device (that conducts current) as "channel free." See '893 at Fig. 9 (using term "Channel-Free Length"), 1:67-2:3 Case No. CV-08-0986-SI ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS - 16 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 (explaining that Figure 9 shows status "when operating voltage is supplied") (Ex. B). There are no statements, much less an unequivocal statement, disclaiming channel-free areas that do not conduct current. Thus, nothing in the intrinsic suggests that the "channel-free" area is limited to one that conducts current in the turned-on state. Finally, Samsung substitutes "inversion zone" for the term "channel." First, the term "inversion zone" is not used in the patent, so it introduces additional technical jargon that has no meaning to lay jurors. Second, Samsung's new term creates confusion because other parts of the asserted claims refer to the "channel." '893 at 6:13-16 ("a channel-region formed between the source and drain regions, for defining a channel that conducts current") (Ex. B). It is confusing to refer to a "channel" in one part of a claim and refer to the absence of a channel using a different term. IV. THE PATEL '830 PATENT A. Description of the Invention ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS The '830 patent relates to the field of decoupling capacitors. A decoupling capacitor is a device that reduces voltage spikes in electronic circuits. Declaration of Eby Friedman ("Friedman Decl.") 11. Voltage spikes occur when there are changes in the amount of current in the power lines (busses) of electronic systems. Id. This behavior is particularly problematic in modern integrated circuits, where faster switching speeds exacerbate voltage spikes, leading to malfunctions in circuit logic. Id. The capacitors act as reservoirs of charge to smooth out the effect of changes in current. Id. Capacitors are made up of three components: a top plate, a middle layer of insulation, and a bottom plate. A diagram illustrating these three components is found in the left hand side of Friedman Decl. 13. The '830 patent claims significant improvements to the concept of using capacitors to reduce voltage spikes. In particular, it describes such capacitors as being at the substrate level (under the busses). '830 at 6:20-29 (Ex. C). Claim 1 describes the structure of the capacitor as being similar to that of a MOSFET. The bottom plate of the capacitor is a doped region of the substrate. Id. at 6:27-29. The top plate is known as a "gate electrode." Id. at 6:22-23. The Case No. CV-08-0986-SI - 17 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 insulation between the two is referred to as "gate oxide." Id. at 6:29-31. A diagram illustrating these components is depicted in the right hand side of Friedman Decl. 13. Claim 5 describes an improvement that is of particular importance. It discloses an embodiment wherein the gate electrode of claim 1 is "divided into a plurality of segments and each of said segments is independently connected electrically" to one of the said busses. '830 at 6:54-56 (Ex. C). This segmented gate is one of the key innovations disclosed by the '830 patent because it reduces electrical resistance and creates redundancy that allows the capacitor to continue to operate even if one segment suffers a fabrication defect or burns out. Id. at 5:26-43. AMD previously asserted the '830 patent in this district in Oki Am., Inc. v. Advanced Micro Devices, Inc., No. C-04-03171-CRB. The parties litigated the validity of claims 1-6. In a "Memorandum and Order" filed November 13, 2006 ("Oki Order") (Breyer, J.) (Ex. K), this Court ruled on summary judgment that claims 1-4 were invalid, but declined to find claims 5 and 6 invalid. Here, AMD is asserting only claims 5 and 6. Some of the claim terms were construed in the context of the summary judgment order. Id. B. "Gate Electrode . . . Is Divided into a Plurality of Segments" Means the Segments Must Share a Common Doped Region. "Gate electrode . . . is divided into a plurality of segments" (asserted claim 5) AMD's Construction "For each doped region (lower plate), the gate electrode (upper plate) is divided into a plurality of segments." Samsung's Construction "In the improved integrated circuit structure of claim 1, the gate electrode is divided into two or more separate gate electrode segments." ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS AMD proposes exactly the same construction for this term as the one adopted by this Court in the Oki Order: First, [claims 5 and 6] do not simply require, as Oki primarily contends, a plurality of MOS capacitors as recited in claim 1; instead, the claims introduce a limitation wherein for each doped region (lower plate), the gate electrode (upper plate) is divided into a plurality of segments, and each is separately wired to the bus. '830 at 6:53-58. Oki Order at 12 (emphasis added) (Ex. K). Case No. CV-08-0986-SI - 18 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 The Oki Court's construction should be adopted in this case, because it explains that the gate segments identified in claim 5 must share a common doped region. The concept of a gate electrode divided into "segments" has meaning only if those segments share a common doped region. Friedman Decl. 18. If each gate segment had its own doped region, there would simply be a collection of individual capacitors, each containing separate top and bottom plates separated by insulation. Id. The word "segment" would lose all meaning in the context of the claim. Id. To illustrate this point, the figure in the top portion of Friedman Decl. 19 depicts gate segments sharing a common doped region and the bottom portion illustrates various gates, each paired with their own doped region of the substrate (i.e., separate capacitors). Only the top portion could be referred to as having "segmented" gates. Friedman Decl. 19. If the purpose of claim 5 were simply to require a plurality of individual capacitors, as illustrated in the bottom portion of Friedman Decl. 19, then the patentees could have said so in much simpler language. In fact, the patentees did just that in claim 2. There, the patent claims the structure of claim one, wherein the "capacitance means comprise more than one of said MOS capacitors." '830 at claim 2 (Ex. C). The fact that claim 5 does not use this plain language, and instead claims a "segmented" gate, is strong evidence that a different meaning should apply. See Innova/Pure Water, 381 F.3d at 1119 (explaining that all claim terms are presumed to have meaning, and a court should strive for a construction that gives meaning to all of its terms). The specification also supports AMD's claim construction. The specification is "always highly relevant to the claim construction analysis." Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). The embodiment that corresponds to claim 5 depicts a common doped region. '830 at 5:11-14; see also Fig. 16 (Ex. C). This embodiment shows multiple gate electrode segments (structure 18) sharing a common, underlying doped region without insulation separating the underlying doped regions from each other. Id. at 5:18-25; Friedman Decl. 20. The claim language itself is also highly instructive. Claim 5 states that "said gate electrode . . . is divided into a plurality of segments." '830 at 6:54-55 (Ex. C). The antecedent basis for "said gate electrode" is the "gate electrode" of independent claim 1. That claim, in turn, makes clear that the gate electrode overlies "a doped region." Id. at 6:27-28 (emphasis added). Case No. CV-08-0986-SI ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS - 19 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 The specification confirms that "a doped region" refers to a single doped region. Although "a" typically means one or more than one following "comprising," "a" is limited to meaning "one" where a plural interpretation would be "inconsistent with" the stated function of the invention. Insituform Techs., Inc. v. CAT Contracting, Inc., 99 F.3d 1098, 1105-06 (Fed. Cir. 1996). This is such a case. Here, the patentee cites lower resistance as an advantage of the structure recited in claim 5. '830 at 5:30-32 (Ex. C). Specifically, the patentee states that by doping the areas in the substrate (N+ regions, shown as region 21 in Figure 16) corresponding to the gaps between the gate segments, "additional vias can be formed through oxide layer to interconnect not only N+ contact regions 20 and 22, but region 21 as well with the overlying bus. . . . This serves to further lower the resistance between the Vss bus and channel 24, i.e., the lower plate of capacitor 16." Id. at 5:26-32 (emphasis added). In other words, resistance can be lowered by having additional connections to the doped area of the substrate below and in between the gate segments. For this to happen, the gate segments would have to share a common doped region, as depicted in Figure 16. Friedman Decl. 22. Further, a person of ordinary skill in the art would understand that having a common doped region would be highly desirable to achieve the goal of lowered resistance. Id. As a matter of physics and electrical engineering, a decrease in resistance can only be assured if the bottom plate of the capacitor is a single node or electrical location with multiple connections. Id. C. Two Structures Are "Electrically Connected Directly" if There Is No Active Device Between Them. "Electrically connected directly between said busses" (claim 1, asserted claim 5) AMD's Construction "The bus and the capacitor are connected without any intervening active devices, such as transistors." Samsung's Construction "Connected through a direct and physical electrical connection, which includes no intermediate structures, to the Vcc current bus and the Vss bus." ROBINS, KAPLAN, MILLER & CIRESI L.L.P. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ATTORNEYS AT LAW MINNEAPOLIS The correct construction of this term begins, as it should, with the language of the claim itself. Phillips, 415 F.3d at 1312. The claim requires that there be a direct electrical connection Case No. CV-08-0986-SI - 20 - PLAINTIFFS' OPENING CLAIM CONSTRUCTION BRIEF 1 2 3 4 5 6 7 between the capacitor and the bus. '830 at claim 5 (Ex. C). The claim does not recite a direct "physical" connection. In other words, the shape or configuration of any material between the two items does not affect whether the connection is "direct" in an electrical sense, as long as there are no active devices. From an electrical perspective, a connection is "direct" as long as there is no "active device" (which, in the context of an integrated circuit, means a transistor, which often acts as a switch) between the two points. Friedman Decl. 24. If there were an active device between the two points being connected, the connection would be "indirect" because the switch could be turned off and there would be no connection at all. Id. A person of ordinary skill in the art would agree with AMD's construction because it is the one most consistent with the intrinsic record, including the file history. Friedman Decl. 24. There, the applicants equated an "indirect" connection with one containing a switch or transistor. For example, in the February 2, 1987 Remarks, the applicants distinguished two prior art references (Kuo and Mao) by stating that "[b]oth of [those] references, as understood, disclose coupling one plate of a capacitor to the source or drain of the switching device in a memory cell while the other plate is connected to the Vcc line." Remarks, Feb. 2, 1987, at 8 (Ex. L). This shows that the patentee distinguished art cited by the examiner by noting that, while one plate of the capacitor connected to the Vcc bus, the other plate connected to an active device--namely, a transistor or "switching" device. The patentee further distinguished the prior art references by drawing a distinction between an indirect connection through a transistor on the one hand, and a direct connection to a bus, on the other: While the capacitors of the memory cells of the references each have an upper plate connected to the Vcc (power) bus, the lower plate of their memory capaci

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