Goodard v. Google, Inc.

Filing 158

Goodard v. Google, Inc.

Doc. 158 Att. 5

Dockets.Justia.com

[ill

Lee et ai.
COMPUTER PROVIDING JXEXIBLE PROCESSOR EXTENSION, FL.EXIBLE INSTRUCTION SET EXTENSION, ANI3 M L I C T T EMULATION FOR UPWARD SOITWARE COMPATIBILITY
Inventors: Ruby B. Lee, Cupertino; Michael J. Mahon, San Jose, both of Calif. Assignee:

[45]

Patent Number: Date of Patent:

4,763,242
Aug, 9, 1988

FOREIGN PATENT DOCUMENTS
0041405 12/198t 0092610 11/1983 0123337 10/1984

European Pat: Off. European Pat. Off. European Pat. Off.

. .

.

OTHER PUBLICATIONS

Wewlett-Packard Company, Palo Alto, Calif.

Appl. NO.: 790,970

Fiied:
Int. a . 4

onU,laSs

Assimanr Examiner-Debra A. Chun Attorney, Agent, or Finn-Douglas L. Weller

Wescon Conference Record, Anaheim, Calif., U.S.A., vol. 24, Sep. 16-18, 1980, Bunky: "Enhancing CPU Performance: Slave, Co-Processor, Smart 1/0 Altemative~",pp, 1-8. Primary Examiner-Gareth D. Shaw
1571
ABSTRACT

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Go6F 9/w w/2w Field of Search ... 364/200 MS File, 9W MS File
Referencea Cited U.S. PATENT DOCUMENTS
3,242,465 4,084,235 4,104,720 4,205,370 4,484,273 4,S14,803 3/1966 4/1978 8/1978 5/1980 11/1984 4/198S Gloates et al. ................... 340/172.5 Hirtle et al. ......................... 364/200 364/200 Gruner ................................ Hirtle .................................. 364/200 Stimer e? al. ....................... 364/200 l 364/200 Agnew et a . ......................

allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although an assist's operation and design need not be defined at the computer's date of design. fnstructions are mapped to panicular assist, Assist instruccan be either executed hardware by an in Or emufated in software via a trap.
13 Claims, 6 Drawing Sheets

A computer and an instruction set are presented which

COMPUTER SYSTEM 1 1 : 0 COP
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ASS T CONTROL

BUS 159

PROCESSOR I03

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SFU 107.

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CONTROL UNIT 115

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INTERFACE 139

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MEMORY SYSTEM 111

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DATA PATH t49

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Aug. 9,1988

Sheet 3 of 6

9

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Sheet 4 of 6

515
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DECODE NEXT INSTRUCTION
c

INSTRUCTION AND ADDRESS, OF ASSIST INSTRUCTION

ASSESTS E MULATION SIGNAL, BROADCASTS ASSIST INSTRUCTION, AND ISSUES DELAYED TRAP

TRAP FOR ASSIST INSTRUCTION

T DEASSERTS

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Aug. 9,1988

Sheet 6 of 6

computer was still unable to execute an extension inCOMPUTER PROVIDING FLEXIBLE struction, and a second computer had to be designed. PROCESSOR EXTENSION, FLEXIBLE In the prior art, a computer was designed to run with INsTRucIlON SET EXTENSION, AM) IMPLICIT an add-on assist either present or absent. If the add-on EMULATION FOR UPWARD S O W A R E 5 assist was present in a configuration, a program with an COMPATIBILITY extension instruction intended for the add-on assist would be executed in hardware by the add-on assist. If BACKGROUND the add-on assist was absent in the configuration, code had to be written with a branch instruction instead of The present invention relates to a computer into which a number of assists can be easily added without lo the extension instruction. The branch instruction caused execution to jump to a software routine that would compromising software compatibility. An assist is hardemulate execution of the extension instruction. ware which extends a processor's capability. The proA serious disadvantage of the branch instruction was posed computer can support assists that are undefrned at the computer's date of design. In addition to being able that it did not provide software compatiblity. Code to execute a basic instruction set, the computer can Is written for a first computer that incorporated the addexecute one or more extension instruction sets. An exon assist was not portable to a second computer that did tension instruction set contains instructions that do not not incorporate the add-on assist, unless the code was belong to the basic instruction set. The computer can completely recomp2ed. Code written for the second implement the extension instruction, either executed in computer had to be completely recompiled if the code hardware via an assist, or emulated in software via a 20 was to operate efficiently as possible on the first comtrap. puter. in the prior art, it was either impossible or impractiAnother disadvantage of the branch instruction was cal to incorporate an assist into a computer, if the ms it that it did not provide fault tolerance at run-time. No was undefined at the comuuter's date of desim. Incoroption for emulation existed at run-time if the add-on prating the assist into thk computer wouldkversely 25 assist failed. If the add-on assist failed at run-time, code impact datapaths and controls of a processor within the written for the first computer could not be executed. ccmputer, and would fail to satisfy speed requirements for b t a main processor and the assist. Another veroh SUMMARY OF THE INVENTION sion of the computer would have to be designed which In accordance with the preferred embodiment of the 30 could more practically incorporate the assist. present invention, a computer, including a main procesIn the prior art, a computer sometimes incorporated a sor, a memory system, and an assist, are presented floating-point accelerator as a very specialized add-on which provide for flexible incorporation of additional assist. A typical floating-point accelerator had a highly assists, which provide for a flexible extension of a basic specialized interface to a processor. This highly specialized interface did not allow an incorporation of a differ- 35 instruction set, which provide for implicit emulation of an extension of the basic instruction set, and which ent type of assist. provide for software compatibility between computers Xrr the prior art, a limited method was devised with different configurations of assists, including conwhereby only a very few &ts could be added to a figurations with no assists. computer. Software programs written for a f i t computer, the f i t computer including a first main proces- 40 An assist can be incorporated into the computer, provided the assist follows a predefined hardware prosor and a fust assist, were not portable to a second tocol, simply by attaching the assist to the main procescomputer, the second computer including the fmt main sor via a set of buses. The assist decodes its own instrucprocessor but not the fust assist. tions, so that actual functional operations performed by In the prior art, a first computer was designed to execute a basic instruction set. The first computer suf- 45 the assist can be defined at a later date, The hardware protocol is set up so that the main processor is indifferfered the disadvantage of being unable to execute extenent to the actual number of assist's incorporated into the sion instructions defined at a later date. A second comcomputer, and to any actual functional operations perputer had to be designed which could execute the extenformed by a particular assist. The hardware protocol sion instructions as well as the basic instruction set. o There was no upward compatibility; although the a c fo operates in conjunction with software emulation s as eto make the main processor indifferent to a presence or ond computer could execute programs written for the absence of a particular assist within the computer. first computer, the first cornmiter could not execute The main processor interfaces with an assist in one of programs-written for the secoid computer. two ways, based upon a datapath used by the assist. An In the prior art, a scheme was devised whereby nue s t is defined as either a Special Function Unit, abbremerous opccdes were reserved within a basic instrucviated SFLJ, or as a co-processor, abbreviated COP. tion set for extension instructions. The scheme wm less than optimal, since too much valuable opcode space in An SFW receives and sends data to the main procesthe basic instruction set was reserved for currently sor's registen. An SFU can be incorporated into the undefined extension instructions. computer by directly impacting internal register buses In a variation of the scheme just discussed, a second of the main processor. Direct coupling to the main scheme was devised in which minimal opcode space in processor's internal register buses enables an SFU to the basic instruction set was reserved for an escape achieve a very high performance level. For an inteinstruction. The escape instruction indicated that subsegrated main processor, such as a Very Large Scale quent instructions were not to be decoded as part of the Integrated processor on a chip, an SFO can also be basic set, but as extension instructions, until another incorporated by attaching to an external bus, achieving escape instruction was encountered. While the second a reduced performance level, but thereby not directly scheme solved a disadvantage in which too many o p impacting the internal register buses of the main procescodes were reserved for extension instructions, the fmt sor.

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tem. A memory system is typically either a main memory or a cache in conjunction with a main memory. A COP is incorporated into the computer without impacting internal register buses of the processor. A COP is 5 incorporated into the computer without impacting the processor's software register allocation and optimization problem. The main processor performs address calculations, virtual memory addressing, and virtual memory protection checking for a COP. 10 Assist instructions defrne all data movement allowed between an assist and another location. The main processor decodes and supports a processor field of an assist instruction. Hardware control and datapath needs for the first field are built into the computer. The assist IS decodes and supports an assist field of the assist instruction. The assist instructions are generic in nature; they define movement of data without regard to functional operations performed by the assists upon that data This 20 allows the computer to be easily configured with additional assists whose operations need not be defined at the computer's date of design. Opcode space is reserved within assist instructions so that functional operations can be defined at a later date. 25 Four basic opcodes are rewrved within the basic instruction set for all possible instruction set extensions. One basic opcode is reserved for SFU extension instructions, one for COP extension instructions, and two for COP load and store instructions. Any extension instntc- 30 tion, with one of these four basic opcodes is called an m i s t instruction. An extension of the basic instruction set can be accomplished by deftning opcude space reserved within the assist instructions for functional operations to be- 35 performed by an assist. The assist can be designed to perform a functional operation which accomplishes an extension of the basic instruction set. A particular Set of extension instructions can be identified bv a mau field within an assist field of the assist instruction. l%e map 40 field is recognized by the assist for whom the assist instruction is intended. Since data movement for assist instructions is supported by the computer, the assist can be easily inconporated into the computer. The computer can be config- 45 ured with a particular set of assists so that assist instructions are defined and tailored for a pmcular application, The present invention implements implicit emulation. If the computer encountem an assist instruction at run 30 time for an assist that is unable to execute, being either absent or failed, the main processor takes an emulation trap. Software emulates a functional operation defied by the assist instruction. If the assist is able to execute, the emulation trap is not taken, and the assist executes 55 the assist instruction. The emulation trap is a delayed, implicit trap. The hardware protocol calls for an assist to acknowledge its presence and its alive state in order to prevent the emulation trap from being taken. The emulation trap is 60 taken by default if the assist does not acknowledge its presence. The assist instructions and the hardware protocol allow the computer to be configured with a set of assists enabling an instruction set extension to be executed in 65 hardware. When the computer is configured without a particular assist, the computer takes an emulation trap for assist instructions which map to the particular assist,

A COP receives and sends data to the memory sys-

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ware. Upward software compatibility is provided, since via the emulation trap a configuration without a particular assist can still run code containing a particular assist instruction mapped to the particular assist. The implicit emulation trap and the hardware assists protocol also provide fault tolerance, since an assist that fails at execution time implicitly invokes the emulation trap to execute the assist instructions in software, thereby continuing execution, but with degraded performance. Hence, the current invention provides not only upward software compatibility but also fault tolerant features.

so that those assist instructions can be emulated in soft-

4

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1is a block diagram of a prefemed embodiment of the computer, an SFU,and a COP. F G 2 is an operational diagram of a typical SFW I. instruction. FIG. 3 is an operationel diagram of a first typical COP instruction. FIG. 4 is an operational diagram of a second typical COP instruction. FIG, 5 is a flow chart depicting steps taken for an emulation trap. FIG. 6 is a detailed diagram of an assist control bus.
DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of a computer configured with an SFW and a COP. A main processor 103 is connected v a a data bus 105 to an SFU 107, a COP 109, and i a memory system 111. Main processor 103 includes a control unit 115, a processor functional unit 117, a plurality of registers 119, and a processor bus interface 125. Control unit 115 receives an instruction u7 from memory system 111via data bus lo9 and processor bus interface 125. Memory system 111 includes a plurality of memory addresses 121. A plurality of words is stored within memory system 111, each word being located at a corresponding memory address. Instruction 127 is just one instruction among a plurality of instructions located within plurality of memory a#dresses 121. A word 169, just one word among the plurality of words, is also located within plurality of memory addresses 121. Instruction I 7 comprises a processor field 129 and 2 an assist field 131. Control unit 115 decodes processor field 129. I f pmcessor field l 9 indicates that instruction 2 127 is a basic instxuction, processor functional unit 117 executes instruction 127, loading or storing any required operands or results in plurality of registers 119 or in memory system 111. If processor field 129 indicates that instruction 127 is an assist instruction, stores a copy of instruction 127 is stored in a register among plurality of registers 119, An instruction space and an instruction offset which indicate a memory address 161 at which instruction 127 is located are also stored in registers 119. If a data reference is specified i instruction 127, a data space and a n data offset which indicate a data address are also stored in registers 119. Instruction 127 is also transferred to either SFU 107 or COP 109, and control unit 115 directs data movement defined by processor field 129. Assist field 131 includes a map field 133,which maps instruction 1'27 to SFU 107, to COP 109, or to another assist.

SFU 107 includes an S 6 control unit 135,an SFU Other SF'U instructions-are defroed with the same major opcode 290, but different minor op field 225, functional unit 137,and an SF'U bus interface 139. SFU bus interface 139 passes instruction l27 on to SFU con- allowing other forms of generic data movement betrol unit 135. SFU functional unit 137 executes assist tween the processor and any SFU.For example, zero, field 131.Control unit 115 directs SFU bus interface 139 5 one, or two words may be moved from a processor via an asaist control bus 159. Control unit 119 directs register among a pluntlity of registers 119 into an SFU. data movment via a data path 141 between a register FIG.3 is a detailed diagram of a typical COP load or $63,among plurality of registem 11% and sm fune store instruction 303. COP instruction 303 includes a tional unit 137. processor field 305 and an assist field 307. Processor COP 109 includes a COP control unit 143, a cop 10 field 305 is decoded and executed by main processor 1Q3, and assist field 307 is decoded and executed by h C t i 0 d unit 14% and a COP bus interface 147,COP instfuction l27 on to cop conCOP 109. Processor field 305 includes a major op field bus interface 147 P 311,a register source field 313,a register index field 315, wit 14% cop functional Unit $45 executes assist field 131. COntml unit 115 diseGts cop interface and a s p e register specifier 317. Assist field 307 in147 "& &t WntrOl bus 159. Control U& 115 directs 15 cludes a map field 3m and a register target field 321, data mOvement via a data path 14g between a Register source field 313 specifies a source register address 191 and COP functional unit 14S. 323 among plurality of registen 119 within main procesmove data between a Data path 5or 103. Register index field 315 specifiesan index regisresister among plurality of registem 119 and a Mc* ter 325 among plurality of registers 119. Space register SFU functional Unit among a P l d t Y Of SFu's. nata 20 specifier 317 specifies a space register 341 among a plurality of space registen 3n, path 149 can move data between a particular memory address pturality Of addresses and a p r o m o r 103 calculates an effective a d d f a , Particular cop functional unit among a plurality Of upon data within wurce register 323,index regisCOP'S. ter 325, space register 341, and other data within proMemory address 151,which Stores word 169, is IO- 25 cesser field 305,Main processor 103 calculates the efGated among pludity of memory addresses 121.Mem. integfective addrffs to insure that virtual ory addresses are accessed through a memory system unit 115 rity and protection checking integrity are maintained. bus interface 153, which is directed by via a memory control bus 155,An emulation trap banThe effective address is a concatenation of a virtual address space and an address offset. The virtual address dler 157 resides in memory system 111, is a detail& diagram of a typical sFu instrue- space is calculated from data within space register 341, FIG, a processor field and the other data within processor field 305. The adM3 tion 203 sm dress offset is calculated from data within source regisan assist field 207. Pracessor field uIs is de205 ter 323, index register 325, and the other data within coded and executed by processor 103, and 305* field 207 is decoded and executed by SFW 107. Proces- 35 processor A word 329 is located in memory system at the effecM)rfKd ZOJ includes a major op field 209, a register tive address. A COP 3 1 includes a fUllCtlOIlEl Unit 333, target field 2x1, and a op field 225. h i s t field 207 includes a map field 213 and a functional op field which includes a plurality of regsten 339. Word 329 is loaded into a target register 337 among plurality of 215. Major op field 209 identifies SFu d m c t i o n 1 89 40 E&krs 339.COP 331 grouped arnong a plurality of n COP'S 335. Map fieid 319 maps COP instruction 303 to an assist instruction. Minor op field 225 identifia a to be perCOP 331. Target register 337 is specified by register particular type of generic formed, in &is instance "store from sm." Register target field 321. Other COP load and store instructions me defined SidlalY, except that the amount of data target field 211 specifies a register 217 among plurality of re&ten 119.Major op field ~9 directs prmes- 45 transferred, and the method of calculating the effective address i different. In a COP store instruction, the data s from an word 219, 103 to move a is transferred from the COP to memory SyStem 111. pro217, assist, off data bus 109 and into &t data FIG. 4 is a detailed diagram of a COP instruction 403. C m r 103 is indifferent which word 219 originates from. M & pwegsor 103 c0-uCOP instruction 403 includes a processor field 405 and nicates with all assists via a hardware protoco] which H, an mist field 409.Prwessor field 409 comprises a major at any given time. me OP code. Assist field 4 7 includes a rnap field 411 and a 0 supports from 0 to 16 functional Op field 413. hardware protocol is discussed in greater detail below, A COP 415 is among a plurality of COP'S 417.Map in conjunction with FIG.6. An SFU 221 is among a plurality of S m s 223. Map field 413 maps COP instruction 403 to COP 415. Data field 213 maps SEU instruction 203 to SFU 221.Data op 55 op field 413 directs COP 415 to perform a specified fieid 215 directs SFU 2 U to perform a specified funcfunctional operation upon specified operands. tional operation upon a specified set of operan&. Major FIG.5 is a flow chart depicting steps taken for an op field u)9 and functional op field 215 direct SFU 221 emulation trap. Main processor 103 may execute in a pipelined mode, so that a plurality of pipeline stages for to move data word 219 onto data bus 105. since main processor 103 does not decode assist field 60 different instructions are performed simultaneously. In 207, and since main processor 103 interfaces with each a step 511, main processor 103 Fetches an instruction assist in an identical fashion, a second assist can be defrom memory system 111, and control unit 115 decodes the instruction. If control unit 115 ascertains in a step signed at a future date and easily coupled to data bus l and to assist control bus 159.So long as the second W 513 that the instruction is a basic instruction, not an assist follows the hardware protocol in interfacing with 65 assist instruction, processor functional unit 117 executes main processor 103,functional op field 215 will be able the basic instruction in a step 515. Main processor 103 to direct the second assist to perform a currently undereturns to step 511; another instruction is fetched and fined operation, decoded.

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If control unit 115 ascertains in step 513 that the instruction is an assist instruction, in a step 517 the assist instruction and information indicating an address of the assist instruction is saved in interrupt parameter registers, among plurality of registers 119. For co-processor 5 load and store instructions, information indicating the effective address of an associated data word is also saved in interrupt parameter registers. In a pipelined processor 103, information is saved in the interrupt parameter registers in such a way that these registers 10 contain information relative to the instruction that caused the intempt, when the interrupt is finally taken. In step 518, control unit 115 determines if the bit, corresponding to the particular assist, in the co-processor configuration register is set. At system initialization IS time,a bit in the co-processor coafguration register is set for every co-processor included in the hardware configuration for this system. The co-processor configuration register is one register among plurality of registers 119. If the bit in the co-processor configuration 20 register is set, then execution continues at step 519, otherwise the main processor takes an emulation trap at step 531. X a step 519, control unit 115 asserts an emulation n signal within assist control bus 159, or this signal is 25 normally asserted by a pull-up on that line of the assist control bus 159. The assist instruction is broadcast out over data bus 105. Main processor 103 issues an implicit, delayed trap. The implicit, delayed trap is an emulation trap; the emulation trap will be taken if, after an interval 30 of time has passed, the emulation signal is still asserted. If the assist instruction is mapped to an assist that is unable to execute, the emulation signal is not deasserted or pulled down. If the assist instruction is mapped to an assist that is 35 able to execute, the assist acknowledges main processor 103 by deasserting the emulation signal and executing the assist instruction in a step 523. Deasserting the emulation signal is performed to prevent main processor I103 from taking the delayed trap on the assist instruction. 40 If main processor 103 ascertains in step 325 that the emulation signal i s still asserted, main processor 103 t k a software emulation trap, and emulation trap aa handler 157 is run to emulate the assist instruction in a step 531. 45 Emulation trap handler 157 determines from the assist instruction which assist was mapped and which operation was desired, in order to jump to appropriate emuiation d e for emulating the assist instruction. Emulation trap handler 157 wastes no time in re-fetching the assist 50 instruction or in determining the address of the assist instruction or the address of the associated data word, since pertinent values have already been saved in the interrupt parameter registers among plurality of registers 119. Without the interrupt parameter registers, this 55 information would no longer be present in processor 103, if processor 105 were a pipelined processor. FIG. 6 is a block diagram showing one possible type of assist control bus 159, depicted i FIG. 1, in greater n detail. Main processor 103, SFU 107, and COP 109 are 60 connected to memory system 111via data bus 105. Main processor 103, SFU 107, and COP 109 are also connected to each other via assist control bus 159. Assist control bus 159 comprises a signal "assist initiate" 602, abbreviated AINIT, a signal "assist data transfer" 604, 65 abbreviated ADTR, a signal ``assist emulate" 606, abbreviated AEMU, a signal "assist exception" 608, abbreviated AEXC, a signal "assist nullify" 610, abbrevi-

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ated ANUL, and a signal "assist ready" 612, abbreviated ARDY. AINIT 602 is a signal from main processor 103 for timing and identifying "assist cycles." ADTR 604 is a signal from main processor 103 for identifying whether a assist cycle is a data transfer cycle or a command n cycle. A W Y 612 is a response signal from an assist for indicating that the assist is ready to continue. AEMU 606 is a response Signal from an assist for indicating that the assist is present in the configuration, and therefore does not need to be emulated in software. AEXC 608 is a response signal from an assist for indicating that an operation could not be successfully completed. and that an exception trap should be taken to perform any necessary handling. A W L 610 is a response signal from an assist for indicating that a next instruction should be nullified. A W L 61Qis typically used in conjunction with having the assist test a condition, and using A W L 610 to nullify a branch instruction should the condition be met. If processor field 129 indicates to control unit 115 that instruction 127 is an assist instruction, main processor 103 places instruction 127 onto data bus 105 for a clock cycle. Instruction 127 is mapped to a particular assist, and the particular assist, if present and alive, is expected to recognize a particular value of map field 133 within instruction 127. The clock cycle is called a commmd cycle. Main processor 103 asserts AIMIT 602 for the first half of the command cycle. During the command cycle, rnai0 processor 103 deasserts ADTR 604 to indicate that an assist instruction, rather than a data transfer, is coming across data bus 105. A clock cycle, calted a response cycle, follows the command cycle. On a falling edge of the response cycle, main procmor 103 samples AEMU 605,ARDY 612, AEXC 608, and ANUL 610. If map field 133 maps instruction 1 7 to an assist that is absent or failed, then 2 no assist recognizes map field 133, and AEMU 606 remains asserted. If AEMU 606 is asserted, main processor 103 rakes an emulation trnp, and the assist instruction is emulated in software. If map field 133 maps instruction 127 to an assist that is present and alive, the assist deasserts AEMU 6%. If the assist asserts ARDY 612, the assist is indicating to main processor 103 that values of AEXC 608 and ANUL 610 are also valid. The assist asserts ARDY 612 to indicate that the assist is ready to continue with a data transfer cycle. If the assist is present, but not ready to continue, the assist deasserts both ARDY 612 and AEMU 606. If ARDY 612 is degsserted during the response cycle, main processor 103 executes one or more wait cycles. At the middle of each wait cycle, main processor 103 samples ARDY 612. Wait cycles continue and main processor 103 continues sampling until ARDY 612 is asscrrted by rhe assist. Following any wait cycles, main processor 103 asserts ADTR 604 throughout one or more data transfer cycles to indicate that a data transfer, rather than an assist instruction, is coming across data bus 105. Main processor 103 asserts AINIT 602 for a first half of the first data transfer cycle. When instruction 127 is a "store from SFU and operate" instruction mapped to S W 107, SFU bus interface 139 drives data specified by assist field 131 onto data bus 105. Processor bus interface 125 latches onto the specified data, and moves the data to register 163, specified by processor field 129.

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When instruction 127 is a "load to SFW and operate" instruction mapped to SFU 107, processor bus interface f25: drives data stored in register 163,specified by processor field 1 9 onto data bus 105. SFU bus interface 2. 139 latches onto the data and moves the data to SFU 5 functional unit 137. Instruction 127 may dir*ectthat two words are to be moved from main processor 103 to SFW 1M. The two words may be moved in one data transfer cycle, provided data bus 105 is sufficiently wide, or the two words 10 may be moved in two data transfer cycles, if data bus 05 can only transfer one word per cycle. When instruction 127 is a "store from COP" instruction mapped to COP 109,word 169 is moved from COP functional unit 145 to memory address 191. Memory 1s transaction timing is similar to memory transaction timing for a basic instruction that stores a word to memory address 151 from main processor 1W. P~OCXSOT functional unit 117 translates a location specified by processor field l 2 into memory address 151. Main 2o .9 p r v r 103 performs virtual memory addressing calculahons and virtual memory protection checking. Processor bus interface 1 . drives memory address IS1 25 onto data bus 105 during a f m t data transfer cycle. In a second data transfer cycle, COP bus interface 147 25 drives a word onto data bus l M , where the word is stored in memory system 111. COP bus interface 147 samples memory control bus 155 in order to know when word 169 may be removed from data bus 103. If memory system 111 is not ready, memory wait cycles are When instruction 127 is a "load to COP" instruction mapped to COP 109, execution is simiiar to execution for a "store from COP" instruction, except that word 169 is moved from memory address 151 to COP functional unit 145. When instruction 127 is a "load double word to COP" instruction mapped to COP 109, execution is similar to execution for a "load to COP" instruction, except that two words are transferred rather than one. When instruction 127 is a "store double word to COP" instruction mapped to COP 109, execution is similar to executioa for a "store to COP" instruction, except that two words are transferred rather than one. A final data transfer cycle may be foliowed by a single recovery cycle. The single recovery cycle provides data hold time and prevents bus contention with a following processor cycle. Response cycles for assist hstructions which do not move any data, such as COP instructions 403,are also followed by a single recovery cycle. We claim: I, A computing device, comprising: a bus which carries data; an assist, which can be coupled to the bus and which can be uncoupled from the bus, including a first functional means for executing an assist instruction; a main processor, coupled to the bus, including a second functional means for executing a set of basic instructions; a system memory which contains emulation code allowing the emulation of the assist instruction; and, a communication means, coupled to the main pro. ceswr and coupled to the assist when the assist is coupled to the data bus, for enabling the main processor to determine if the assist is able to
inserted.

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execute the assist instruction, wherein the main processor, via the data bus, transfers the assist instruction to the assist when the assist is able to execute the assist instruction and wherein the main processor, using the emulation code within the system memory, executes the assist instruction when the assist is unable to execute the aspist instruction. 2. A computing device as in claim 1, wherein the assist instruction and its address are saved in registers in the main processor. 3. A computing device as in claim 2, wherein a data offset address and a Virtual space identifier for the assist instruction are saved in registers in the main processor. 4. A computing device as in claim 1 wherein the main processor includes a configuration register means for indicating whether the computing device has been configured 90 that the assist is coupled to the bus. 5. A computing device tis in claim 4 wherein the emulation code includes an emulation trap sequence which directs the processor to emulate execution of the assist instruction when the configuration register indicates that the computing device has been configured s o that the assist is not coupled to the bus and been configured so that the assist is not coupled to the bus, and when the assist indicates it is unable to execute the assist instruction. 6. A computing device, comprising: a bus which CBIliea data; a fmt assist which executes a first field of a first instruction, including: a first controlling means for controliing the first field, a fmt functional means, responsive to the first controlling means, for executing the first field, and, a first interface means for moving data between the first functional means and the bus; a memory system, including: a plurality of memory locations which store data, and, a second interface means for moving data between a first memory location and the bus; and, a main processor which executes a second field of the first instruction, including: a second controlling means for decoding the second field and for controlling the first and second interface means, thereby controlling data move'ment via the bus between the first memory location and the first functional means, wherein the main processor performs address calculations when data is to be moved between the first assist and the memory system. 7. A computing device as in claim 6, wherein the main processor performs virtual memory addressing when data is to be moved between the first assist and the memory system; and wherein the main processor performs memory protection checking when data is to be moved between the first assist and the memory system. 8. A computing device as in claim 6, further comprising: a second assist which executes a third field of a second instruction, including: a third controlling means for controlling the third field,

10

a second functional means, responsive to the third controlling means, for executing the third field, and, a third interface means for moving data between 5 the second functional means and the bus; wherein the main processor further includes: a Set of registers which store data, and a fourth interface means for moving data between the bus and a re@ster from the pluality Of 10 registers; and, wherein the second controhg meam controls the fourth interface means and the third interface mM thereby controlling data movement the via bus between the fmt register and the second fwc- 15 t i o d means. 9. A computing device as in claim 8 additionally comprising: a communication means,coupled to the main process, for allowing the main processor to determine if a 20 third assist is abIe to execute a third instruction, wherein the main processor via the bus transfers the third instruction to the third assist when the third assist is able to execute the third instruction and 25 wherein the main processor emulates execution of the third instruction by executing a series of basic instructions when the third assist is unable to execute the third instruction. 'O' A computing device as ffl 'Iaim 3 0 by means of a map field within the third instruction, the third assist is able to recognize the third instruction as being addressed to the third assist. 11. A computing device as in claim IO, wherein the main processor, by checking 35 a major op field within the third instruction, is able to distinguish the third instruction from a plurality of basic instructions.

11

4,763,242

sent from the main processor to the fourth assist inchdes: a data movement field which directs data movement between the fourth assist and a location; and, a functional op field which directs the fourth assist to perform a functional operation. 13. A protocol device which allows communication between a processor a d a plurlity of wherein the plurality of assists includes a first assist, the protocol device comprising: amemorysystem; a bus, coupled to the memory system, to the main p-, rr and to each assist in the plurality of as~bts, bus being used to transfer data and inthe structions from the main processor to assists in the plurality of assists; a first control means, coupled to the main processor and to each assist from the plurality of assists, for indicating when the bus is carrying data as opposed to instructions; a first rapon* m a s vcoupled to the main processor and to each assist in the plurality of assists, for allowing the first assist to indicate its presence to the main processor when a first instruction field within a fmt instruction indicates the f i t instruction is addressed to the first assist; a second response means, coupled to the main processor and to each assist in the plurality of assists, for allowing the first assist to indicate its readiness to transfer data; wherein when the first assist becomes detached from the bus and when the fust assist does not indicate its presence to the main processor via the first response means, the main processor talres a trap and executes the fmt instruction.
* * * * #

12. A computing device as in claim 11 additionally comprising a fourth assist, wherein a fourth instruction

12

45

55

65

UNITED STATES PATENT AND TRADEMARK OFFICE

~~~~IFIC
4,763,242 August 9, 1988 Ruby E. Lee and Richael J.

PATENTNO. DATED

:

INVENTOR(S) :

It is certified that error appears in the above-identified patent'and that said Letters Patent is hereby corrected as shown below:

C o l m 7 , Line 56, " i f processor 105 were a pipelined" should read

--

i f processor 103

re a pipelined ---;

10, Lines 26 through 27

, "bus and

been configured so that the

assist i s n o t coupled t o the bus, and" should read

-- bus and

---;

Column I I , Line 19, ' in process''

should read

---

i n processor

---.