Goodard v. Google, Inc.

Filing 158

Goodard v. Google, Inc.

Doc. 158 Att. 7

Dockets.Justia.com

nited States
Ueda et al.
14 PROCESSOR CAPABLE OF EXECUTING 51 ONE OR MORE PROGRAMS BY A PLURGLI" OF OPERATION UNITS
[75]

pi]

[45]

Patent Number: Date of Patent:

4,821,187
Apr. 11, 1989

4,507,728 3/1985 Sakamoto et ai.

..................364/203

Inventors: Hirotada Ueda, Kokubunji; Hitoshi Matsushima, Tachikawa; Yoshimune Hagiwam, Hachioji; Kenji Kaneko, Sagamihara, all of Japan

Primary Examiner-Gareth D. Shaw Assistant Examiner-Debra A. Chun Attorney, Agent, or Firm-Antonelli, Terry & Wands
1571 ABSTRACT A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the fxst operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.

1731 Assignee: Hitachi, Ltd., Tokyo, Japan
[21] Appl. No.: 794,449 [22] Filed: Nov, 4, 1985
Japan

1301

Foreign Application Priority Data

NOV. 1984 [JP] 2,

................................

I511 Int. (3.4 E521 U.S. cf. [58] Field of

.........................
12/1971 1/1977 5/1979 2/1981 2/1984

.........................

364/200 364/200 MS File

.... G06F 9/28

59-230247

1561

References Cited U.S. PATENT DOCUMENTS
3,631,405 4,W1,788 4,156,279 4,251,862 4,430,707

Roff et al. ....... Patterson et ai Wilbite ................................ Murayama .........................

Kim

364200 364/200 364/200

9 Claims, 6 Drawing Sheets

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Sheet 1 of 6

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32-27

Apr. 11,1989

Sheet 2 of 6
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Sheet 4 of 6

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4,232 1,187

PROCXSSOR CAPABLE OF EXECUTING ONE OR MORE PROGRAMS BY A PLURALITY OF OPERATION UNITS
5 BACKGROUND OF T H E INVENTION It has been known to connect a plurality of processors and parallelly operate them in order to increase the processing speed of a data processing apparatus. For example, the Intel "Component Data Catalog" 1981, 10 pages 7-5 1 to 7-57 and 7-65 to 7-75 shows a configuration in which an input/output processor 8089 or a numeric operation processor 8087 is connected to a CPU processor 8086 or 8088 for parallel operation in order to increase the processing speed. When the input/output 15 processor 8089 is started by the CPU, it independently processes in accordance with its own program. This type of connection requires communication between the processors for indicating the start and the end of processing. Accordingly, this configuration is suited to 20 highly independent parallel processing, but where high speed and frequent processings are required, the execution of the program for the required communication between processors causes an increase in overhead and 25 the processing speed is lowered. The numeric operation processor 8087 essentially foIlows the CPU as opposed to the processor 8089 and merely shares a portion of instructions (floating point operation or special function operation) of a single pro0 gram which the CPU serially fetches. This type of con- 3 nection is superior in that it does not include an overhead due to a communication program. However, in this configuration, instructions for the numeric operation processor 8087 are incorporated in a program for the CPU processor 8086 in addition to 35 instructions for the CPU processor 8086, and when the CPU processor 8086 detects an instruction for the numeric operation processor 8087, it sends an instruction decode signal to the numeric oueration urocessor 8087 to leave $ocessing for that in&uction io the numeric @ operation processor 8087. As a result, if the execution of the instruction for the 8087 processor is delayed for some reason, the execution of the instruction for the CPU processor 8086 is also delayed. Accordingly, where there is a possibility that the 45 processing in one of the processors is delayed, it is desirable that the processing in one processor and the processing in the other processor are executed by separate programs,

L structions stored in the first program memory control the fust and second operation units and the instructions are executed by parallel operation of those operation units. In a multi-program mode, the first operation unit is under the control of the fist control means while the second operation unit is .isolated from the first control means and under the control of the second control means so that the microinstructions stored in the first program memory control the first operation unit and the microinstructions stored in the second program memory control the second operation unit, Accordingly, in this mode, high speed processing i s attained by parallel run of the two independent programs. The switching from the normal mode to the multi-program mode is effected by a specific microinstruction stored in the first program memory. The switching from the multi-program mode to the normal mode may be effected by another microinstruction stored in the frst program memory, or by a specific microinstruction stored in the second program memory. In the processor thus configured, those instructions of two non-parallelly executed processings which can be processed synchronously to each other can be executed by the two operation units under the control of one program. Where there is a possibility that one of the processings is delayed for some reason, the two operation units independently execute the instructions under the control of the two programs.

n

BRIEF DESCRIPTION OF T H E DRAWINGS FIG. 1 is a block diagram of one embodiment of a processor of the present invention, FIG. 2A shows a format of a microinstruction which is stored in a Erst program memory 3 and controls first and second operation units, FIG.2B shows a format of a microinstruction which is stored in the first program memory 3 and controls the first operation unit, FIG. ZC shows a format of a microinstruction in a normal mode, FIG. 2D shows a format of a shift instruction from the normal mode to a multi-program mode, FIG. 2E shows another format of the shift instruction from the normal mode to the multi-program mode, FIG. 2F shows a format of a jump instruction, FIG. 2G shows a format of a shift instruction from the multi-program mode to the normal mode, FIG. 2H shows a format of a forced return instruc50 tion from the multi-program mode to the normal mode, SUMMARY OF THE INVENTION FIG. 3A shows a format of a microinstruction stored in a second program memory 4, It is an object of the present invention to provide a FIG. 3B shows a format of a normal return instrucprocessor which selectively executes a plurality of protion from the multi-program mode to the normal mode, grams or one program by a plurality of operation units FIG. 4 is a block diagram of the first operation unit 1 to execute the programs with a small overhead. 55 of the processor of FIG. 1, In accordance with the present invention, there are FIG. 5 is a block diagram of the second operation unit provided fust and second operation units, a first pro2 of the processor of FIG. 1, gram memory for storing first microinstructions for FIG. 6 is a block diagram of another embodiment of controlling the fmt operation unit and second microinstructions for controlling at least the second operation 60 the processor of the present invention, and FIG. 7 is a block diagram of a further embodiment of unit, a second program memory for storing third microthe processor of the present invention. instructions for controlling the second operation unit, first control means connected to the fist program memDESCRIPTION OF THE PREFERRED ory for controlling the first and second operation units, EMBODIMENTS and second control means connected to the second 65 FIG. 1 shows one embodiment of the present invenprogram memory for controlling the second operation tion. A first operation unit 1 and a second operation unit unit. In a normal mode, both operation units are under control of the first control means so that the microin2 process data and calculate addresses, A first program

memory 3 stores microinstructions which control only The control field 33 includes control information for an overall control including bus switching and input/outthe first operation unit 1 and microinstructions which put sequence control. The control field 33 is divided control both the first and second operation units 1 and 2. The microinstructions are read out one at a time in into the first control field 33-1 and the second control accordance with a first program counter 5. A second 5 field 33-2 and contains bus control insrructions. The first control field 33-1controls the first operation unit 1 program memory 4 stores microinstructions which control only the second operation unit 2.The microinstrucand the second control field 33-2 controls the second tions are read out one at a time in accordance with a operation unit 2 . second program counter 6. A first control circuit 7 In a normal instruction in the normal mode, as shown n updates or modifies the first program counter 5 in re- 10 i FIG. 2C, a leading bit 32-1 in the second operation field 32 and a second bit 32-3are "0" and remaining bits sponse to a control field 33 of the microprogram in32-2designate an operation of the second operation unit struction stored in the first program memory 3. It also decodes the instruction stored in the first program mem2 . ory by a decoder 71 and supplies a decode signal to the FIG. 2 D shows a shift instruction from the normal first operation unit 1, a bus switch 52,the second opera- 15 mode to the multi-program mode. In this instruction, the leading bit 32-1 of the second operation field 32 is tion unit 2, a switching circuit 92 and a two port memory 50 to control the operation in the first operation unit "l", the second bit 32-3 is "0", and the remaining bits 1, the switching of the bus switch 52, the operation in 32-2indicate a start address of the second program to be started. the second operation unit 2 and the two-port memory 50. A second control circuit 8 updates or modifies the 20 FIG. 2 G shows a shift instruction from the multi-proo gram mode to the normal mode. In this instruction, the second program counter 6 in response t a control field 42 of the microprogram instruction stored in the second leading bit 32-1 in the second operation field 32 is "O", program memory 4. It also decodes the instruction the second bit 32-3 is "I" and the remaining bits 32 are stored in the second program memory 4 by a decoder 71 not used. and supplies a decode signal to the second operation 25 FIG. 3 A shows a format of the microinstruction stored in the second program memory. A n operation unit 2, and the switching circuits 91 and 92 to control field 4 designates an operation of the second operation 1 the operation in the second operation unit 2 and the unit 2 and a control field 42 is similar to the control , switching of the switching circuits 91 and 92. A discrimination circuit 10 in the first control circuit field 33 of the microinstruction stored in the first pro7 controls the setting of the second program counter 6 30 gram memory. and the switching of the switching circuit 9 in response The blocks shown in FIG. 1 are now explained in to a multi-program mode shift instruction or a forced detail. FIG. 4 shows a detail of the frrst operation unit 1. return instruction in the microprogram stored in the first program memory 3. The instructions stored in the Numeral 121 denotes an arithmetic logic unit (ALU) first program memory 3 are sequentially read out by the 35 which carries out addition/subtraction and shift. Data stored i registers 122 or data supplied from data bus n first program counter 5. The instructions stored in the 113 are supplied to the ALU 121. One of the inputs second program memory 4 are sequentially read out by . thereof is selected by a multiplexer (MPX) 123 by a the second program counter 6 A two-port memory SO i s connected to the first operation unit 1, the second multiplexor control signal 334.The data to be supplied operation unit 2, the first control circuit 7 and the sec- 40 to the ALU 121 is also selected by a register selection signal 333. By designation by the register selection sigond control circuit 8, and it can be accessed from either one of the operation units 1 and 2. Control signals are nal 333 and a register write signal 337,output data from transmitted between the operation units and the control the ALU 121 or data from the data bus 113 is written into the selected register. The selection is made by a circuits through control buses 111 and 211, addresses are transferred through address buses 112 and 212, and 45 multiplexer (MPX) 124 which is controlled by a multiplexer control signal 331. data are transferred through data buses 113 and 213. The switching circuit 9 selects a second operation The output data from the ALU 121 is supplied t the o data bus 113 through a tristate control circuit 126.This field of the microinstruction stored in the first program is controlled by a control line 338. A bus control circuit memory or an operation field 41 of the microinstruction stored in the second program memory and supplies the 50 127 is switched by the signal 338 to reverse the direction selected operation field to the second operation unit 2. of the input/output of the data bus. The registers 122 are connected to a multiplexer It also selects a second operation control field 32-2 of the microinstruction stored in the first program memOVfPX) 125,and data in one of the registers selected by ory or a control field 42 of the microinstruction stored a multiplexer controi signal 332 is supplied to an address in the second program memory and supplies the se- 55 bus 112. The multiplexer control signals 331, 332 and ltxted control field to the second operation unit 2 Nu. 334, the register selection signal 333, the register write signal 337 and the control signal 338 are produced by meral 51 denotes an input/output port through which data is exchanged with an external device. the decoder 7 in the first control circuit 7. FIG. 2 A shows a basic format of the microinstruction The second operation unit 2 has the Same circuit which is stored in the first program memory and con- 60 configuration as the first operation unit 1 as shown in trols the first and second operation units. FIG. 2B FIG. 5, Multiplexer control signals 331A,332A,334A, shows a format of the microinstruction which is stored register selection signal 333A, register write signal 337A,and control signal 338A are produced by the first in the first program memory and controls only the first operation unit. The present embodiment relates to a control circuit 7 Multiplexer controI signal 331B,332B, . processor for executing horizontal microprograms. The 65 334B,register selection signal 333B, register write sigfirst operation field 31 designates an operation of the nal 337B and control signal 338B are produced by the second control circuit 8. In FIG. 5, numerals with suffirst operation unit 1, and the second operation field 32 designates an operation of the second operation unit. fixes A or B such as 331A and 331B denote the signals

3

4,821,187

4

corresponding to those without suffixes shown in FIG. 102, it supplies the status word signal 502 to the control circuit 7. The status word signal 502 is supplied to the 4. comparator 72 in the first control circuit 7 and is used as A detail of the first control circuit 7 shown in FIG. 1 one of the conditions of a conditional jump in the microis now explained. The decoder 71 decodes the first control field 33-1 and the second control field 33-2 in 5 instruction in the first program memory. When the control signal 101 applied to the switching circuit 92 is the control field 33 and produces the multiplexer conthe shift signal to the multi-program mode, the switchtrol signal 331,33lA, 332, 332A, 334 or 3%A, the repister select signal 333 or 333A, a jump signal 335 or 335A ing circuit 92 invalidates the control signal 211-1 and validates the control signal 211-2. When the control indicating a jump instruction, or a jump condition Signal 336 or 336A for the jump instruction, in accordance 10 signal 101 is the return signal or when the return instruction is supplied from the control line 102, it valiwith the decoded instruction code. It also produces the dates the control signal 211-1 and invalidates the cogregister write signal 337 or 337A and the control bus 111 or 211-1. For the jump instruction, a comparator 72 trol signal 211-2. The multiplexer MPX 62 functions to produces an equal signal 340 when a status word signal select the address to be loaded to the second program So1 from the first operation unit and a status word signal 15 counter. When the jump signal 205 is issued, the operation field 41 of the microinstruction stored in the second 502 from the second operation unit are equal to the jump condition signal 336. The equal signal and the program Pemory is selected and it is loaded into the second program counter, when the control signal 101 is jump signal 335 are outputted from an A M ) circuit 73 issued, the second operation field 32-2 is selected of the as a program counter load signal 105, which is a load signal to the first program counter 5. When this signal 20 microinstruction stored in the first program memory is selected by the MPX 62 and it is loaded to the second 105 is supplied, the first program counter 5 loads a program counter. jump-to address coded in the first operation field 31 as a new content of the program counter as shown in FIG. The operation of the present invention is now explained. In the normal mode, the second operation geld 2F. That is, a jump operation is canied out. When the program counter load signal 105 is not supplied, the first 25 32 of the microinstruction stored in the first program memory is supplied to the second operation unit 2, the program counter 5 increments. Thus, in a normal course first operation field 31 is supplied to the first operation of operation, the instructions are sequentially read out unit 1, and the microinstructions which are sequentially and executed. The second control circuit 8 of FIG.1 is read from the first program memory 3 by the first proidentical to the fvst control circuit 7 except that the status word signal S 1 is not supplied to the comparator 30 gram counter 5 control both the first operation unit 1 O and the second operation unit 2. 72. The discrimination circuit 10 monitors bits 32-1 and When the shift instruction to the multi-program mode 32-3 and, when they are "IO", that is, identify a multiis issued during the execution of the microinstruction program shift instruction, it issues a control signal 101 stored in the first program memory, the mode is shifted for shifting to set the bits 32-2, that is, the start address of the microprogram stored in the second program 35 to the multi-program mode and the first operation unit memory into the second program counter 6 through the 1 and the first control circuit 7 execute the microinstructions fetched from the first program memory 3 by multiplexer (MPX) 62 and switch the switching circuits the frrst program counter, 5, and in parallel therewith, 9, 91 and 92. When the bits 32-1 and 32-3 are "Ol", that is, the shift instruction from the multi-program mode, to the second operation unit 2 and the second control the normal mode the discrimination circuit 10 issues the 40 circuit 8 executes the microinstructions fetched from the second program memory 4. control signal 101 for return to switch the switching The return from the multi-program mode to the norcircuits 9, 91 and 92. The switching circuit 9 receives the control signal mal mode i s now explained. There are two cases. In one case, the mode is returned to the normal mode when the 101 from the discrimination circuit 10 and the control signal 102 from the second control circuit 8. When the 45 execution of the microinstructions stored in the second control signal 101 is the shift signal, it wiI1 invalidate the program memory is completed. In the other case, the mode is forcibly returned to the normal mode during second operation field 32 and the second operation field of 33-2 of the first program memory and validates the the execution of the microprograms by a reason such as a detection of a fault in the external circuit. The former operation field 41 and the control field 42 of the second program memory. Until the shift signal is supplied, it 50 is called a normal return and the latter is called a forced return. operates in the opposite manner. When the control signal 101 is the shift signal (return For the normal return, an instruction (normal return instruction) from the multi-program mode to the norinstruction) for instructing the return to the normal mode is prepared in the instruction sets of the micropromal mode, or when the return signal i s supplied from the control line 102, the switching circuit 9 validates the 55 gram stored in the second program memory, and it is second operation field 32 and the second operation put at the end of the started program stored in the second program memory. For example, as shown in FIG. control field 33-2 of the first program memory and 3B, the normal return instruction code is put in the invalidates the operation field 41 and the control field 42 of the second program memory. In the normal mode, control field 42. the second operation control field 32-2 decoded by the 60 For the forced return, an instruction is prepared in decoder 71 in the fxst control circuit 7 switches the bus the program stored in the first program memory as of the second operation unit 2 through the switching shown in FIG. 2H. There are many methods for the second program to circuit 9. When the control signal 101 applied to the switching circuit 101 is the shift signal to the multi-probe executed in the normal mode at the end thereof. If gram mode, the switching circuit 91 stops the supply of 65 the first program is structured such that the second the status word signal 501 to the control circuit 7, and program is executed in the normal mode at an anticiwhen the control signal 101 is the return signal or when pated end time of the processing even if the completion the return instruction is supplied from the control line of the second program is somewhat delayed, the in-

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structions in the first program may be merely executed dance with the microprogram stored in the first program memory, and in parallel therewith, the second sequentially. In this case, the frst program may be structured such that the normal return instruction is not operation unit 2 writes the input data supplied through the input/output port 51 into the two-port memory 50 used but the forced return instruction is executed at the anticipated processing completion time. Alternatively, 5 in accordance with the microprogram stored in the the end of the second program may be indicated to the second program memory. Accordingly, in this mode, even if queuing is necessary for data processing, the first program. For example, as shown in FIG. 7, a flag 80 is provided, and an instruction for setting the flag 80 queuing is carried out by the microprogram stored in the second memory so that the data can be correctly (which is decoded by the decoder 71 in the first control circuit 7 and applied to the flag 80 as a flag set signal 10 received. The microprogram stored in the first program 801) and a jump signal conditioned by the reset status of memory can process the data at the maximum speed irrespective of the queuing. This mode is particularly the flag 801 which is applied to the comparator 72 in the effective where an image is read by a Scanner which first control circuit 7 as a flag status signal 802 to control the jump) are prepared in the instruction set stored generates data at an externally determined timing and in the frst program memory. On the other hand, an 15 the data is sequentially processed. instruction to reset the flag (which is decoded by the In a second example, it is assumed that the data in the two-port memory 50 is to be processed at a high speed second control circuit 8 and applied to the flag 80 as a and an address calculation therefor is complex. Where flag reset signal 803) is prepared in the instruction set stored in the second program memory. By using those the image is inputted while it is pre-processed and then instructions, the mode is shifted to the multi-program 20 is further processed, a data arrangement is of two or mode after the flag has been set for the microprogram more-dimension structure and a complex address calculation is required in many c w . When a predetermined stored in the first program memory, and the conditional jump inStNCtiOn is executed at an appropniate interval. number of pixels have been inputted in the multi-praOn the other hand, the flag reset instruction and the gram mode, the processor is set to the normal mode and normal return instruction are put at the end of the mi- 25 the bus switch 52 is switched to the bus 212. Under this configuration, while the first operation unit 1 processes croprogram stored in the second program memory. Thus, at the end of the microprogram stored in the the data read from the two-port memory, the second second program memory, the flag is reset and the operation unit 2 parallelly calculates the address of the data to be read next from the two-port memory. switching circuit 9 is switched. Then, as the microprogram stored in the first program memory detects it, it 30 The second example is suitable to the processing in jumps to the instruction to be executed in the normal the normal mode and not suitable to the processing in mode and the mode is returned to the normal mode. As the multi-program mode, because, in the multi-program a result the program is executed in the normal mode mode, the two operation units cannot synchronize the immediately after the execution of the program stored operations (data processing and address calculation) to in the second program memory. Alternatively, the re- 35 each other. For example, where the first operation on setting of the flag may cause interruption to the prounit 1 which is operating the data decodes the condition gram stored in the fmt program memory to cause the and jumps accordingly, the number of steps of program jump. Further alternatively, an interruption instruction execution changes significantly depending on the presto the microprogram stored in the first program memence or absence of the jump. It is necessary to indicate ory may be prepared in the instruction set stored in the 40 to the second operation unit 2 to advance or retard the second program memory and it may be put at the end of calculation of the next address by the second operation the microprogram stored in the frst program memory. unit 2. To this end, it is necessary to use the multi-program mode shift instruction for each address calculation The selection of the normal mode and the multi-program mode is explained. In FIG, 1, the buses 112 and or to include such an instruction in the program that the 113 connected to the first operation unit 1 and the buses 45 first operation unit 1 reads out and decodes the flag set 212 and 213 connected to the second operation unit 2 by the second operation unit 7 (for example, a portion of the two-port memory 50 is normally set to "0" and it is are connected to the fmt and second par& respectively, of the hvo-port memory 50. The control buses 111 and set to "1" when the flag is set). The inclusion of such or 112 are connected to the two-port memory 50 through extra instruction delays the execution of the entire prothe first control circuit 7 and the second control circuit 50 gram. 8, respectively. Accordingly, each operation unit can When compared with a case where the data processing and the address calculation are alternately carried freely access the two-port memory 50. The buses 212 and 213 connected to the second operation unit 2 are out by the signal operation unit, the throughput is imalso connected to the input/ output port 5 1 so that the proved as much as two times by a simple estimation, In second operation unit 2 can exchange data with an 5 5 the single operation unit system, the registers are short external device. The bus switch 52 connects either one when the data processing and the address calculation of the address buses 112 and 212 to the first port of the are switched and hence the processed data must be temporarily buffered to the memory. Accordingly, it is two-port memory 50. The switching of the bus switch 52 is controlled by the output 339 from the first control considered that the throughput is improved by more circuit 7 in accordance with a particular code in the 60 than double, microinstruction stored in the first program memory. The switching circuit 9 has been shown as an indeIn a first example, it is assumed that data entry from pendent circuit, although it may be a portion of the first an input device and data processing in the two port control circuit 7 or other circuit. Further, third and fourth switchable operation units and program control memory 50 are to be carried out paralleliy. To this end, the processor is set to the multi-program mode, and the 65 units may be added. bus switching circuit 52 is switched to the bus 112. As a modification of the muiti-program mode shift instruction, a code indicating the shift to the multi-proUnder this configuration, the first operation unit 1 program mode may be put in the control field 33 of the cesses the data in the two-port memory 50 in accor-

7

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instruction stored in the first program memory, as 2. A processor according to claim 1, wherein said switching means includes means for responding to a shown in FIG. 2E.In this case, as shown in FIG. 6,the discrimination circuit 10 is omitted and the first control first shift microinstruction in said first program to thereafter select the third control signals, for responding to a circuit 7 generates a control signal 101 to start the program stored in the second program memory. The con- 5 second shift microinstruction in said first or second trot signal 101 is generated from the decoder 71 in the program to thereafter select the second control signal, first control circuit. for supplying the selected second or third control sigAs a modification of the normal return instruction, a nals to said second operation means, and for responding to said fust shift microinstruction in the first program to specific bit in the operation field of the microinstruction stored in the second program memory may be used to 10 supply a signal to start processing under control of the instruct the normal return. In this case, a second dissecond program by said second operation means. 3. A processor according to claim 1, wherein each of crimination circuit (not shown) which monitors the said microinstructions which control at least said secspecific bit to generate the control signal 102 is proond operation means in the first program has first and vided. As a modification of the forced return instruction, as 15 second fields for controlling the first and second operashown in FIG. 2H,a code for indicating the forced tion means, and said first control means includes means return may be put in the field 33 and the first control for decoding the first and second fields of the microinstructioins which control said second operation means circuit 7 may detect it to control the return operation. The field assignments of those instructions change and for producing the first and second control signals, slightly from instruction to instruction. For example, as 20 respectively. shown in FIG. 2F, the jump instruction includes the 4. A processor according to claim 2, wherein the code indicating the jump in the control field 33, and a second shift microinstruction is a microinstruction in jump-to address in the first operation field 31. said second program, and said second control means In the present embodiment, the microinstruction includes means for informing end of selection of the which has the fust and second fields to control the first 25 third control signals to said first control means in response to the second shift microinstruction. and second operation units is used as the microinstruction of the first program memory. By using such an 5. A processor according to claim 4, wherein said instruction, the first and second operation units can be informkg means includes fkdg means set in response to controlled in each cycle and the processing speed is the second shift microinstruction, and said first control increased. The present invention is also effective for 30 means includes means for selecting a microinstruction to be fetched next from the first program in response to vertical microinstructions having fields for controlling the output of said flag means. only one of the first and second operation units. 6. A processor according to claim 2, wherein said We claim: switching means includes means for thereafter selecting 1. A processor comprising: first and second operation means for processing data; 35 the second control signals in response to a third shift first memory means for storing a first program inmicroinstruction in the first program. 7. A processor according to claim 2, wherein said cluding microinstructions which control only said first operation means and microinstructions which second control means includes means for sequentially control both said fmt and said second operation reading out the microinstructions in the second pro40 gram from a microinstruction having an address desigmeans: second memory means for storing a second program nated by the first shift microinstruction. including microinstructions which control only 8. A processor according to claim 2, wherein said second operation means; said first and second operation means include means for producing f i s t and second branch condition first control means connected to said first memory judge signals as results of the operations by said means for sequentially reading out the microin- 45 structions in said first program, for decoding the first and second operation means, respectively, said read out microinstructions, for supplying first confirst control means includes first compare means trol signals to said frrst operation means to control for receiving the first and second branch condition said first operation means when the read out microjudge signals and for determining if the first or instructions are the microinstructions which con- 50 second branch condition judge signal satisfies the trol the first operation means, and for supplying branch condition designated by one of the microinsecond control signals to control both of said first structions in the first or second program, and said second operation.means when the read out said second control means includes second compare microinstructions are the microinstructions which means for receiving the second branch condition judge signal and for determining of the second control both said fxst and said second operation 55 means; branch condition judge signal satisfies the branch second control means connected to said second memcondition designated by one of the microinstrucory means for sequentially reading the microintions in the second program, and structions in said second program, for decoding the said third switching means includes means responsive microinstructions and for supplying third control 60 to the first one of the microinstructions in the first signals to control only said second operation program and the second one of the microinstrucmeans; and tions in the second program for selectively supplying the second branch condition judge signal to one switching means connected to said first and second of the first and second comparator means, said control means and responsive to a shift microinmeans supplying the second branch condition struction for selecting said second or third control 65 signals and for thereafter supplying the selected judge signal to the second compare means for a period from the reading of the frst one of the micontrol signals only to said second operation means. croinstructions to the reading of the second one of

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the microinstructions and for supplying the second branch condition judge to said first means For a period other than said period. 9. A according to claim further comprising third memory means connected to said first and 5 second operation means for parallelly performing a first

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data transfer between said first operation means and said third memory means and second data transfer between said second operation means and si third memory ad means.
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