Goodard v. Google, Inc.

Filing 158

Goodard v. Google, Inc.

Doc. 158 Att. 8

Dockets.Justia.com

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Portanova et 4 .
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Patent Number: Date of Patent:

4,992,934
Feb. 12, 1991

Microprocessor System", IEEE Compurer, Oct. 1986. pp. 71-81. Rasset. T. L., Niederland, R.A,. Lane. J. H., Geideman. [75] W. A., "A 31-bit RISC Implemented i n Enhancemen[-Mode J E T GaAs", JEEE Compurer. Oct.. 1986, pp. 1731 60-68. Meng, "Airborne Architecture Standard Holds On". [2l] Digital Design. Oct. 1986, pp. 24, 25. [22] Silvey, A., Milutinovic, Mendoza-Grado, V., "A Survey of Advanced Microprocessors and HLL Computer Related U.S. Application Data Architectures", IEEE Cornpurer, Aug. 1986, pp, 72-85. Colwell, R . P.. Hitchcock, 111, 6.Y.. Jensen. E. D., [63] Continuation of Ser. No. 941.450, Dec. 15, 1986. Sprunt, H. M. Brinkley, Kollar, C , P., "Computers, GOdF 9/40 [SI] Xnt. C l . 5 Complexity, and Controversy", iEEE Computer, Sep. [52] U.S.Cl ................................ 3W232.23; 1985, pp. 8-19. 364/232.3; 364/240.2 Ohr, S., "RISC Machines", Elecrronic Design, Jan. 10. 0 [58] Field of Search ... 361/200 MS File, 9 0 MS File 1985, pp. 175-190. [561 References Cited Patterson, D. A., "Reduced Instruction Set Compurers", Communications ofthe A C M . Jan. 1985, vol. 28. U.S. PATENT DOCUMENTS NO. I. pp. 8-21. 4,434,462 2/1984 Guttag et a1 364/200 Hennesy, J. L., "VLSI Processor Architecture", IEEE 4,498,135 2/1985 Caudel ..,. 364/200 Tranrnctions on Computers. vol. C-33. ;Vo. 12. Dec. 1984. 4,514,801 4/1985 Caudel et 364/200 pp. I221-i245. 4,514,805 411985 McDonou .............. 364/2110 Ungar, D., Blau, R., Foley, P., Samples, D., Patterson. 4,569,016 2/1986 Hao et ai. ...... 364/2cO 4,577,282 3/1986 Caudel et al. . 364/200 D., "Architecture of SOAR: Smalltalk on a RISC". 4,587,612 VI986 Fisk et al. ...... 364/200 11th Annual Symposium on Computer Architecture. 4,589,065 Vt986 Auslander et al. 364/200 Jun. 4-7, 1984, Ann Arbor, Mich. 4,589,087 VI986 Auslmder et al. 3 ~ 7 6 8 Wulf, W. A., "Compilers and Computer Architecture". 364/2(10 4,608,634 8/1986 Caudel et al. ....... IEEE Compurer, Jul. 1981, pp. 41-47. 4,638,426 111987 Chang et al 364/200
4,719.568 ]/I988 Carrubba et al. 4,727,480 2/1988 Albnght et al.

REDUCED MSTRUCTION SET C O M P W N G APPARATUS AND iMETHODS Inventom Gregory A. Portanova; Brian J. Spmgue, both of Enfield, Conn. Assignee: United Tecbnologies Corp~ation, Hartford, Conn. Appl. No.: !W4,055 Filed: Mar. 30,l

...................364/200
364/2W

OTHER PUBLICATIONS A VSLI RISC, by Patterson et ai, lEEE ComDuter, Sep. 1982. pp. 8-18. The 801 Minicomputer, by Radin, IBM J. Res. Develop., vol. 27, No. 3, May 1983, pp. 237-246. Byington, L., Theis, D., "Air Force Standard 1750A ISA Is the New Trend,,, comparrep, 1986, pp. 50-59. a l ~ an ~ ~ a ~circuit E~ ~ ~~ ~ ~ , E]ec[ronic on i ~~P., Design. Oct. 30, 1986. Tab&, D,, "Which System 1s a RISc?", IEEE Cornpurer. Oct. 1986, pp. 85, 86. Fox, E. R., Kiefer, K.J.. Vangen, R. F., Whalen, S. P., "Reduced Instruction Set Architecture for a GaAs

Primary Examiner-Michaei R. Fleming Assistonr Exominer-Debra A. Chun Attorney, Agent, or Firm-Francis J. Maguire, J r . [571 ABSTRACT A reduced instruction set computer (RISC) with a Har. is disclosed. The RISC may bc vard signed to be used simply as a RISC or may be desipncd to be used to emulate a complex instruction set corn. puter (CISC). Or, it may be designed for use as either A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulstiOn C o d e iS Written concurrently with design and fahrtcation and also subsequent to fabrication.
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issue. Colwell et al point out that RISC theory connotes a willingness to make design trade-offs freely and consciously across architecture/implementation, hardwarehoftware and compile-time/run-time boundaries in order to maximize performance, as measured in some specific context. According to this thinking, although the RISC and CKSC acronyms seem to imply that any machine can be classified as one or the other, in actuality RISCs and CXSCs should be thought of as being at different corners of a continuous multi-dimensional design space. Thus, the need is not for one exclusive of the other but for the formulation of a set of techniques drawn from CISC experiences and RISC tenets, which can be used by a designer in creating new systems. Notwithstanding the above, it will be understood that the number of instructions is an important criterion for categorizing an architecture as a RXSC or CISC. Therefore, the RISC disclosure and claims which follow, which formulate such techniques, should be understood as failing in the category of a design philosophy for a computer with, in fact, a reduced instruction set, without limitation to a RISC having some nr all of the attributes of a RISC machine, so well described by Colwell et al. fn other words, the disclosure which follows draws on some RISC concepts other than a reduced instruction set and is not necessarily located at the RISC "corner" of the "design space." The military has defined a standard 16-bit complex instruction set architecture (MIL-STD-1750 and 11s progeny) for airborne computers. The purpose of the standard is to establish a uniform instruction set archttecture for specifying Air Force avionic weapon s p tems without defining spcific implementation details of a computer. Thus, it only defines the complex instruc. tion set architecture and system-unique requirement\ are left for later definition for each specific compuicr Its application is not restricted to any particular avioniC function or specific hardware implementation. Genu. ally, the standard may be applicable, without limitatinn. to computers that perform such functions as moderarc accuracy navigation, computed air release potnt\. weapon delivery, air rendezvous, stores management. aircraft guidance, and aircraft management. The dr1750" may be used throughoui scription "MIL-STDthis document to describe the original standard and ail its progeny, except where specific revisions are described, and it should therefore be understood in that sense. The expected benefits of the MIL-STD-1750 standard instruction set architecture are the use and re-use of avaitable support software such as compilers and instruction level simulators. Other benefits may also be achieved such as: (a) reduction in total support software gained by the use of the standard instruction set architecture for two or more computers in a weapon system, and (b) software development independent of hardware development. The military standard defines the functional operation from a programmer's perspective. I t defines data formats, instruction formats, instruction mnemonics, instruction operations, addressing modes, programmer accessed regsters, interrupt structure, etc. Since it does not define specific implementations, it is vendor and technology independent. As mentioned, its use is expected to promote :he use of standard software support

REDUCED INSTRUCTION SET COMPUTING APPARATUS AND METHODS
06/941,450, filed Dec. 15, 1986, now abandoned.

one of the primary issues in the RISC literature, the best generalization of RISC theory g w s well beyond this

This is a continuation of application Ser. No. 5 DESCRIPTION

The present invention relates to computers and, more IO particularly, to reduced instruction set computers (RISC). 2. Background Art Complex Instruction Set Computer (CISC) proponents increasingly use very large scale integration to 15 construct highly complex microprocessor hardware to do functions previously done by software alone. This is the result of software becoming increasingly expensive and hardware (VLSI) increasingly cheaper. By using cheaper and more complex hardware, the CISC de- 20 signer reasons, the higher level language can become simpler and hence easier to use and the software development cost goes down. RISC proponents, on the other hand, create simpler microprocessors where more functions are done by 25 software. Such machines are based on the insight that the vast majority of functions executed in any given program tend to be rather simple functions such as load, store, compare, branch, integer arithmetic, logic shifting, etc., that can all be designed for execution in one 3 0 machine cycle. instead of having microinstructions for interpreting the architecture of the particular CISC for each complex function to be performed, the architectural approach in RISC is to have a reduced instruction set designed for direct execution by hardware. Thus, 3s there is no interpretation required since the microprocessor architecture exactly matches the micro-architecture which, in this case, is just code, Le., there is no laborious programming involving the setting of ones and zeros in microcode for setting control lines. Every- 40 thing is done automatically by functions implemented exactly in code. There can be many aspects 10 a RISC design a p proach. An admirable attempt to describe such aspects, drawn from diverse sources, was made in the IEEE, 45 Campurer magazine of September, 1985, pp. 8-19 by Robert P. Colwell et a1 in an article entitled "Computers, Complexity, and Controversy." The aspects described included: ( I ) "Singlecycle operation" for facilitating the rapid execution of simple functions that domi- 50 nate a computer's instruction stream and promoting a low interpretive overhead; (2) "Load/store design'' following from a desire for single-cycle operation; (3) "Hardwired control" providing for the fastest possible single-cycle operation since microcode leads to slower 5 5 control paths and adds to interpretive overhead; (4) "Relatively few instructions and addressing modes" facilitating a fast, simple interpretation by the control engine; ( 5 ) "Fixed instruction format" for easing, with consistant use, the hardwired decoding of instructions, 60 which again speeds control paths: and (6) "More compile-time effort" offering an opportunity to explicitly move static run-time complexity into the compiler. As pointed out in the above quoted article, a common miscanccption about RISC and CISC, probably due to 65 their acronyms, is that the domain for discussion should be restricted to selecting candidates for a machine's instruction set. Although the number of instructions is

1. Technical Field

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tools, the reduction of total support software in multivendor military systems and software development independent of hardware development. The MIL-STD-1750 register set includes sixteen 16bit general purpose registers (RO, . . . RF), a 16-bit status 5 word (SW). a 16-bit instruction counter (IC), a 16-bit mask register (MK). a 16-bit interrupt register (PI), and a 16-bit fault register (FT). The data formats supported include byte (upper, lower), 16-bit fixed point singIe precision (16-bit 2's 10 complement), 32-bit fixed point double precision (32-bit 2's complement), 32-bit floating point (24-bit 2's complement mantissa: 8-bit 2's complement exponent), and 48-bit floating point extended precision (48-bit 2's complement mantissa; 8-bit 2's complement exponent). 15 The MIL-STD-1750 instruction set is a complex instruction set which has been implemented by several companies. so far, using CISCs. For example, Fairchild, MacDonnell-Douglas and Performance Semi-Conductor among others, have all marketed MIL-STD-1750 20 CISC machines. DISCLOSURE OF THE INVENTION An object of the present invention is to provide a simple microprocessor. The microprocessor provided may be viewed as a reduced instruction set computer (RISC), or simply as a signal processor having a simple architecture. The word "RISC' will be used frequently throughout the specification in connection with this object of the present invention. Another object of the present invention is to provide a reduced instruction set computer (RISC) having single-cycle operation for most instructions. Stili another object of the present invention is to provide a RlSC load/store design which follows from the above object of single-cycle operation. Still another object of the present invention is to provide hardwired control for fast singlecycle operation. Still another object of the present invention is to provide relatively few instructions and addressing modes to facilitate a fast, simple interpretation by the control engine. Still another object of the present invention is to provide a fixed instruction format which may be used consistently to ease the hardwired decoding of instructions which in turn speeds control paths. Still another object of the present invention is to provide a simple RISC architecture useable with numerous possible reduced instruction sets. Still another object of the present invention is to provide a reduced instruction set which is conducive to the implementation of such a simple RISC architecture. Still another object of the present invention is to provide a signal processing method using a reduced instruction set for emulating a complex instruction set. Still another object of the present invention is to provide a reduced instruction set signal processor capable of emulating a MIL-STD-I750 instruction set. Still another object of the present invention is to 750 provide a MIL-STD-I microprocessor with which the user may define functions by writing RISC code subroutines for off-chip storage and callup. Still another object of the present invention is to provide a reduced instruction set signal proccssor for use in efficiently emulating a complex instruction set. Still another object of the present invention is to provide a method of designing a signal processor which

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responds to complex instructions but executes them using groups of reduced instructions. Still another object of the present invention is to provide such a method for quickly designing a signal processor in which the architecture of the reduced instruction set signal processor may be designed and reduced to hardware ("silicon") while the programming for the code emulation of the complex instruction set (in reduced instructions) is concurrently carried out. In other words, this object of the present invention i s to provide a reduced instruction set signal processor for emulating a complex instruction set which signal processor has a quick design cycle. According to a first aspect o f the present invention, a reduced instruction set computer (RISC) having a Harvard architecture, Le., having separate data and instruction buses is provided. According to a second aspect of the present invention, the RISC is designed for use as an emulator of a complex instruction set computer (CISC). The RISC responds to complex instructions received over its operand or data bus by addressing, over the RISC instruction bus, a corresponding one of a plurality of groups of R E X instructions, each corresponding to one of the complex instructions. Once the first instruction of the group corresponding to the received complex instruction is addressed and executed, the remainder of the associated reduced instructions in the particular group may be addressed and executed in sequence until all the instructions in the group have been completely executed. In this way, the complex instructions are emulated in hardware using groups of reduced instructions. The reduced instructions are received over the instruction bus of the RlSC machine. In further accord with this second aspect of the present invention, the reduced instruction set computer having the Harvard architecture is designed for use not only as a reduced instruction set signal processor for emulating a complex instruction set computer, but also as a reduced instruction set signal processor operating in a reduced instruction Set operating mode using the instruction bus, as before, for RISC instructions but, in this mode, using the data bus only for operands. This can be characterized as the RISC operating mode. By selecting which mode one wishes to be in, one may select either the RISC or the complex instruction emulation mode and operate as selected. In still further accord with the second aspect of the present invention, the plurality of groups of reduced instructions are stored in a memory store external to the signal processor. As mentioned above, the instructions within a group are stored sequentially for execution. In other words, the addressing of the first reduced instruction in a group is quickly followed by the sequential execution of each of the other reduced instructions in the group. In still further accord with the second aspect of the present invention, the complex instruction set emulated is a MIL-STD-I750 instruction set. According to a third aspect of the present invention, a method of designing a signal processor responsive to complex instruction set instructions comprises the steps of first designing a reduced instruction set signal processor having separate data and instruction buses for use as a reduced instruction set signal processor and, second, designing the reduced instruction set signal processor to emulate the complex instruction set, whereby the data bus of the RISC machine is used for both incoming

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complex instruction set instructions and bi-directional data relating thereto. The RISC instruction bus is used for addressing and receiving reduced instruction set instructions only. A plurality of reduced instructions are executed for each incoming complex instruction 5 received. In this way, the hardware can be designed and reduced to practice while the emulation code is concurrently being written. In still further accord with the first aspect of the present invention, a signal processor architecture has an IO arithmetic logic unit (ALU) responsive to a first input signal and to a second input signal for performing a logical operation upon the two input signals and for providing an ALU output signal indicative of the result of the logical operation. It also has an accumulator 15 which is responsive to the ALU output signal, for storing it and providing it back to a '73" multiplexer (BMUX) which selects from among three different signals, including the accumulator output signal, for providing the second ALU input signal. Another one of 20 the inputs to the BMUX is a RlSC instruction counter output signal which constitutes an address of an instruction to be executed or manipulated by the ALU. The third input to the BMUX is the output of a destination register which is responsive to any one of a number of 25 registers in a register tile. The destination register output signal may instead be provided as data on the operand bus. The instruction counter may receive starting instruction addresses from the ALU and may be regularly clocked for sequential incrementing of addresses. 3 0 The ALU output signal may also be provided to the register tile which contains a number of registers also responsive to incoming operand signals from the data or operand bus. The register file stores either the ALU output signal or the operand signal in seiected storage 35 registers as decoded from the incoming instruction. The register file provides register outputs to the destination register and ,the source register. The source register stores the signal received from the register fite and provides it to an "A" multiplexer (AMUX) or as an .K) output to the operand address bus. The AMUX is alw responsive to RISC instructions received from the RISC instruction bus as previously addressed by the RISC instruction counter. The AMUX provides the first input signal to the ALU. A hardwired control unit 45 decodes incoming complex instructions and provides all the necessary controI signals for operating the above described architecture in the proper sequences. The hardwired control unit decodes instruction signals for: (i) addressing sequentially stored instructions so by providing an incrementing signa1 to the RISC instruction counter during a first quarter of each machine cycle; (ii) providing, during a second quarter of selected machine cycles, control signals to a register tile for selecting storage registers in the regster file to have 5 5 their signal contents operated on by the ALU and for providing, during the second quarter, the selected register signal contents for storage in the source and destination registers; (iii) providing, during a third quarter of selected machine cycles, enabling signals for enabling 60 the operand address and data buses in response to an instruction to load or store data from memory to the o register file or t memory from the register file; (iv) providing, s w i n g during a third quarter of selected machine cycles, a first select signal to the AMUX for 65 selecting between the source output si& and the instruction signal for provision as said first input signal for the ALU; (v) providing, starting during the third quar-

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fer of selected machine cycles, a second select signal to the BMUX for selecting between the destination output signal, the accumulator output signal and the instruction address signal for provision as the second input signal for the ALU: (vi) selecting, starting during the second quarter of selected machine cycles, an Operation to be performed by the ALU by providing an ALU operation select signal to the ALU; (vii) storing, during a first quarter of selected machine cycles, the ALU output signal in the register file, the accumulator, or the instruction counter by providing an ALU output select signal to the appropriate register; and (viii) providing shift signals, during an extended fourth quarter of selected machine cycles, for performing shift, multiplication and division operations. In still further accord with the second aspecr of the present invention, such a RISC signal processor further comprises a complex instruction set program register responsive to complex instruction signals provided relating to an application program written with complex instructions received over the data bus for storing and providing such complex instruction signals to the control means for decoding and providing a reduced instruction set address signal to the RISC instruction counter for addressing the first instruction signal of a group of sequentially stored reduced instruction set signals. Each such group addressed is one of a plurality of such groups, each designed for emulating one of the complex instructions in the complex instruction set. A complex instruction set program address counter is responsive to an incrementing signal for addressing the next complex instruction in the application program in sequence, or iS responsive to an ALU output signal for storing and providing an exception complex instruction address signal. In still further accord with the second aspect of the present invention, the complex instruction signals received are decoded by the control means and are sequentially addressed by providing the program counter with the incrementing signal during a first quaner of selected machine cycles. The control means also provides the reduced instruction set address signal for beginning a group of such reduced instructions to the RISC instruction address counter during a third quarter of selected machine cycles. It also enables the complex program register during a fmt quarter of selected machine cycles to receive, store and provide the complex instruction signals. The first aspect of the present invention provides a simple architecture which m a y be designed and used simply as a RISC machine, without any reference whatsoever to any emulation of a CISC. Of course, as explained in the Background Art section, such a simple architecture can have RlSC attributes and CISC attributes at one and the same time and it is therefore difficult to make a hard and fast boundary between the two. Therefore, it will be understood that the present architecture is located in the design space between the two extremes and is not really strictly characterizable as either except in the broad "reduced instruction" sense, discussed above. The "reduced" instruction set disclosed in the specification is particularly well suited for execution on the disclosed architecture. However. it will be understood that other RISC instruction sets may be formulated for execution on the architecture disclosed. Nevertheless, the simple architecture provided takes several different RISC architectural approaches which,

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without limitation. will be described. First, all instructions except the shift. multiply and divide instructions are executed within a single "two-clock" machine cycle. Operands are register-to-register, with only LOAD and STORE accessing memory. This simplifies internal control. All RISC instructions are executed using hardwire control. NO microcode is used. orsly 32 instruction operations are implemented. Addressing is limited to register indirect and immediate modes. The instruction format iS simple and does not cross word boundaries. In addition t the RISC architecture disclosed herein, o a panicularly useful design methodology is dixlosed, according to the third aspect of the present invention, by which a CXSC may be emulated, in the sense that the signd processor is actually =vnsive to the complex instructions received from the complex instruction set; each such complex instruction received by the RISC machine triggers the addressing Of a particular POUP of reduced instructions preformulated for executing each such instruction by way of emulation. Thus, for each complex instruction emufated, there exists a group of reduced instructions stored for call up and execution in hardware' This approach permits the RISC architecture l o be designed quickly for a hardware embodiment, e.g., as a gate array, while at the same time the emulation code is being developed. Thus, if the designer wishes to design a cIsche may quickly obtain his objectives by first deigning a RISC, proceeding reduce it to '.silicon,3,while at the Same time continuing development ofthe emulation code for emu. lating the complex instruction set, It is est,mated that less than 10% ofthe COSt of designthis approach ing a CISC as a pure CISC, and with supe..or results. One of the primary cost savings are related to reduction of the design jeopardy by CISC designers in the form of several design cycles. n sdesign approach provides the advantage of i quick turnaround because of the concurrent reduction of the hardware to "silicon" while, at the =me time, the But speed is not the emulation code i s being only advantage. Once a hardware design is reduced to "silicon" the design process is completed with respect thereto and no funher changes can be made, Design errors are almost inevitably &=overed at this stage, requiring another costly design cycle with the possibiiity of additional errors being uncovered later even after the m o n d design. This is an extremely costly process both in terms of time and money. The present invention permits the circumventing of this problem by designing an extremely simple architecture in hardware which although also being subject to hardware design "prob. lems" may nonetheless be susceptible to correction using the emulation code to bypass hardware problems. As is known in the a n , during the design process, a function may be effected by the designer, in a given signal processor, in usually more than one way. Thus, if one is attempting to emulate a CISC using a RISC machine one may design the RISC and, in the event of a "glitch" in the hardware design which does not permit a complex instruction to be executed in rhe manner first contemplated in the original design, the designer can change around the emulation code to emulate the "problem" complex instruction in another manner. Thus, the present approach provides the flexibility to tolerate hardware design glitchn. The design methodology for implementation of a complex instruction set computer using RISC, disclosed herein, splits the task of designing a CISC between

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hardware and software. The design efficiency comes from the efficiency of the software. In the prior art, all functions were on one chip. The present disclosure teaches the use of a "two-chip solution" in which the control function is separated from the implementing function. The simple machine disclosed herein speeds [he hardware design process and &o permits the Concurrent design of emulation code. The design jeopardy experienced in the prior art, i.e,, being expa& to WVera1 hardware iterations &fore getting the design to operate properly is avoided, The second wpwt of the present invention provides a RISC machine executing RISC arranged in groups for emulating a CISC. An embodiment of this a s F t may provide the capability of running a RISC machine either as a pure RISC machine with a Harvard architecture in a pure RISC mode, or as a RISC machine executing RISC code arranged in groups for emulating a cIsc.In either case, each such group of may be executed in response to a complex instruction 1o which it corresponds. Once the initial address of the group is piaced on the RISCaddress bus the other members of the reduced instructions in that group are executed in sequence, The approach of having a CISC emulated by means groups of RISC code and the novel approach of having the RISC machine run just as a RISC Or as an provide powerful processing tools according to a reduced instruction set Same time providing the capa" at phitosophyv bility to emulate a complex instruction set using the reduced instruction set architecture. This aspect of the present invention, when used in this way, is indeed a powerful The abiiity of the user to develop his own. userdefined functions to be executed in RISC code is another powerful feature of the reduced instruction set as taught the second asprocmr pect Of the present invention. Ordinarily, a MIL-STD1750 CISC manufacturer would require its customers to order custom-made, sFial1Y developed MIL-ST'D1750 microprocessor chips if that customer wishes to impiement a userdefined function, as permitted by that military standard. (MIL-STD- 1750A implicitly permits user-defined functions while MIL-STD-1750B expressly Provides for such functions). The Present invention provides the user with the capability of defining any number of such userdefined complex instructions for execution in RISC Code after the chip 1s bought; these may be designed by the customer simply using the RXSC instruction set associated with the RISC machine and stored separately in a memory storage device, such as a PROM, for use with the RISC microprocessor. The complete RISC instruction s e t must of course be explained to the customer in the product literature provided at the time of purchase of the MIL-STD-1750 microprocessor to enable him to write user-defined functions. In addition to all of the above teachings of the first aspect of the present invention, a specific reduced instruction set is taught along with the specific RISC architecture which is of course, as previously mentioned, particularly useful for implementing that instruction set as well as many other possible similar instruction sets. The specific RISC architecture disclosed i also extremely useful for the purpose of emulating s MIL-STD-1750 instructions as per the second aspect, as taught below.

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These and other objects, features and advantages of the present invention will become more apparent in light of the detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawing. 5

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FIG. 1 is an illustration of a RISC 10, according to the first aspect of the present invention; FIG. 2 is an ilhstration O a RlSC 10, according to f the first aspect of the present invention, used along with a separate memory Store 20 containing groups of RISC instructions, each group for emulating a complen instruction received from a source of complex instructions over the data bus 18, according to the second aspect of the present invention; FIG. 3 is a more detailed illustration of a RISC 10, according to the first aspect of the present invention, as illustrated by lightly drawn 1 i w ~ (the heavily drawn lines provide additional hardware necessary for implementing a RISC which may emulate a CISC, according to the second aspect of the present invention); FIG. 4 illustrates various waveforms corresponding to the voltage levels of various signals on lines illustrated in FIG. 3: FIG. S is a more detailed illustration of the register file 74 of FIG. 3; FIG. 6 is a detailed illustration of the MUrCe module 78 of FIG. 3; F ~ is~a more detailed illustration of the destina, tion module 76 of FIG. 3: FIG. 8 is a detailed illustration of the accumulator module 140 of FIG. 3; FIG, 9 is an illustration of a prior art design implementation of a CISC in which all instructions are implemented using single level control; FIG. 10 is an illustration of a prior a n approach to the design of a CISC in which ail instructions are impiernented using two-level control: FfG. 11 is an illustration of a prior a n ~ [ S C deign approach in which m a t instructions are implement& using two-level control with the remaining instructions implemented using software; FIG. 12 is an illustration of a CISC implaentation l using a design approach in which d instmctions use two-level control, according to the third aspect of the present invention: and FIG. 13 is an illustration of the steps which may be camed out in designing and fabricating a RISC for emulating a CISC. according to the third aspect of the present invention.

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BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is an illustration of a simple signal processor 55 10, according to the first aspect of the present invention, which may be broadly characterized as a reduced instruction set computer (RISC) and which would normally, without limitation, take the form of a microprocessor. The novel RISC of the present invention has 60 a Harvard architecture, Le., meaning the instruction and data buses are separate. A RISC instruction address bus 12 is used to address reduced instructions which are then received over a reduced instruction bus 14 by the RISC 10. An operand a d d r w bus 16 is used to address 65 data which is either received or provided by the RISC 10 over a data bus IS, which may be bi-directional. As discussed above, in the Background A n section, the

acronym "RISC" is used herein in the broadest sense of a reduced instruction set machine. The use of a Harvard architecture is distinct from a multiplexed instruction/dafa bus approach as used in the prior CISC art in which such a von Neumann architecture has been the preferred approach. The Harvard architectural approach pennits the RlSC to operate at a much faster speed due to the fact that instructions and data may be accessed at the Same time. This i s in keeping with the above discussed general R[SC approach of mmimizing performance. FIG. 2 is an illustration of a RISC 10. similar to the RISC 10 of FIG. 1, and having the %me Harvard architecture, The RISC 10 of FIG. 2 is associated with a memory storage device m, such as a programmable read only memory (PROM) which when used together, accord,ng the second aspect ofthe present inventton, may emulate a complex instruction set computer ((-1s~). ne ~ S C and the PROM 3 may together R 10 be thought of as a ,,two-chip*j22 of or +~solution,q the concept of using a RISC emulate a CISC. The two-chips 22 are in fact a CISC. This turns approach, as disclosed be a highly above, from both the designer and user perspectives. Complex instructions in rhe form of signals are provided Over a signal line 24 the data bus 18 by u,hich they are transmitted the RISC lo. The Of complex instructions 2 is not relevant to the present 4 invention but would generally consist of some application program which is to be executed by the "CISC" 22. Complex instructions are sequentially received in this manner and decoded by the RISC 10. For each such complex instruction received, an initial starting address is provided on the RISC instruction address bus 12 to the PROM 20 where a group of RlSC instructions, conesponding to the panicular ClSC instruction being emulated, me sequentiaily stored. The first RISC instruction addressed in the PROM 20 is then placed on the RISC instruction bus 14, typically for an entire machine cycle. After the instruction has been safely delivered to the RISC 10 for storage or execution, the RlSC 1 wil1 next increment the address on RISC in0 stnrction address bus 12 for accessing the next sequentially Stored emulation instruction for placement On InStrIICtiOn bus 14. This PrOCeSS COntinUeS Until the entire group of RISC instructions (stored in PROM 20 for emulating the particular clsc instruction received over data bus 18) has been executed by way of emulation. A given instruction among others. involve a memory load/store operation in which the data bus 18 I S used to load or store operands by way of data bus 18 and an extension 26 thereof (which merely indicates a path to a data source or destination).
A RlSC

10

o i n t e d s of a RISC 10, similar t the RISCs illustrated in FIGS. 1 and 2. The lightly drawn lines of FIG. 3 correspond to a RISC 10 of FIG. 1, without the CISC emulation aspect of the present invention. FIG. 3 will first be described in terms of these more lightly drawn lines, in order to first fully explain the operation of a RISC embodiment of the first aspect of the present invention. The more heavily drawn lines will then be described in detail in order to fully describe an embodiment of the second aspect of the present invention, i.e., a RISC used to emulate a CISC, as illustrated in FIG. 2.

FIG. is a simplified block diagram illustration of the 3

A control unit 30 provides the internal control signals (not shown far the sake ofsimplicity) for the RISC 10. Among the functions controlled by such control signals is the fetching of the next RISC instruction to be execut&. This is accomplished by incremenring an instruc- 5 tion counter 32, used `to hold a RISC instruction address, for loading a RISC instruction stored at that address into an instruction register 34. The instruction register 34 is actually made up of two registen, a "pine" O r primary register for initially receivingandstoring the 10 RISC instruction currently On the instruction bus 14 (during the current machine cycle) and another, secwas ondary, for holding the instruction On the instruction bus 14 dueng the previous machine cycle until the middle of the current machine cycle. The 15 pipe transfen its the secondary in the middle of each as described in detail below. F ~ 4, ~ illustration is there an , Referring now shown of the vatious waveforms corresponding to the 20 various control sign& provided by the control unit 30. It will be observed that. for illustrative purposes, the of FIG, are ,,frozen,, in time for various with each Other within a sing1e machine 25 cycle 38,which is split up into quarter machine cycles 40%42, @* A basic system "clock" waveform is shown in qO)' which may be Of any selected fieqb) shows a first quarter quency Or duty `lock signal " (cK1) which is useful for U, puWOses to be described in more 52 tCK2) which qc) shows a (ln this case, high) during the second quarter 42 Of each machine cycle. FIG. shows a waveform 5 4 ( C W during the third quarter 44 Of each machine 35 cycle. FIG. we) shows a waveform 56 (CK4) recurring during the fourth quarter 46 of each machine cycle, a @ which shows the ! timing of the loading of the "pipe" register in the instruction register %. Waveform 58 is shown with a w smail arrow at the rising edge of a change in V O h F from low to high Occumng at the Same time as the *sing of CK1 of waveform 50 of FIG*`%b), This indicates that the instruction present on RlSC inStruC3 tion lines 14 of FIG. (which will have been present, at 45 that p i n t In time, for a full machine CyCie) is now Wttled OUt and ready for ClOCking into the RISC iIlStrUCtion register pipe within the instruction register 34. Thus, a clock line 60, shown i FIG. 3, rises on the n *sing edge of CK1 at the beginning of each machine 50 Cycle. In other words, the contents O the instruction f register Pipe is chanced at the beginning of each machine cycle. After the instruction has been present in the "Pipe" register for two full quarter Cycles it i latched s from the "Pipe" into the ~ O n d a r instruction register, 55 y i.e.,at the beginning of CK3 as shown by a rising edge 62 of a waveform 64 in R G . ` E) Of COufse, it Will be % !. understood that the signal presented to the input ofthe secondary register during the second quarter 42 is present at the output of the secondary also during this set- 60 ond quarter 42. since the clock is low. Therefore. the opcode can begin to be decoded by the control during this second quarter period even though not yet latched. Thus, although the instruction in the `*pipe"is resident therein from the beginning of a machine cycle to its end, 65 the contents of the pipe are also copied into the secondary instruction register in the middle of each machine cycle. Therefore, the time that a given instruction is

11 __

4,992,934

present in the secondary register overlaps from the middle of one machine cycle to the middle of another. At the same time that the instruction on the instruction bus 14 is clocked into the instruction register 34 "pipe," the address on the instruction address bus 12 is normally incremented to the next sequential address as initiated by a control signal whose timing is shown in FIG. qh),waveform 68. having its Operative clocking (rising edge 70) timing coincident with the rising edge of CK1 at the beginning of each machine cycle. If, however, an exception inStrUCti0n .5 to be executed. it i Will be loaded with an out of sequence address. Another function of the control unit 30 IS to decode, in different ways, the instructions residing in the instruction register 34 "pipe" and in the secondary register of the instruction register 3 . 4 During the first quarter 40 of each machine cycle, the control unit 30 decodes the register field portion of the instruction just loaded into the pipe register of t h e instruction register 34. A line 72 indicates the transfer of information from the 3o for decoding Of the register Pipe to the fields. (The RlSC instruction format will be described in detail below. Suffice it to say at this point that for the embodiment shown, for a I &bit RISC register-to-register instruction format, the most significant bit5 are the opcode, the next five most significant bits are the destination field the last five bits are the wurce field). The decoded register field information may be used, while in the pipe, to identify a selected pair of registers in a register file 74 which are to be loaded into a destination register 76 and source register 78. Once the register fields are decoded, the proper pair of registers is selected, indicated by a select line $0 which is activatd during the second quarter 42 of the machine cycle. FIGS. a([) and 40) illustrate waveforms 82, 84, respectively, which indicate by their respective rising edges 84,88, that the selected registers in the register file 74 are clocked into the destination and source registers 76,78 at that time, i.e., at the mid-point of the machine cycle. At this point in time, as discussed above, the tnstruction in the pipe is latched into the secondary register in the instruction register While in the secondary register of the instruction register the owode is decoded for the pu'pose of detemining the to be perfamed, The destination fieid is also dw&ed again at this time for the p ~ f p o x determining the register or of within the register file 74 which is or are to written into with either the resuits of an internal operation or with an operand moved in from the data bus 18. Tfiw two alternative loading paths are indicated by a signal line 100 and a signal line 102. The signal line 100 represents the 32.bit output of an arithmetic-logjc unit (ALU) 104 which operates on, among others, signals provided by the destination and source registers 76, 78. For an operation in which the contents of destination and source registers 76.78 are operated on by the ALU 104, the output of that operation is provided on line 100 back into a register pair from which the destination register 76 was originally loaded. On the other hand, the information might instead be from the data bus 18 via a buffer 106, a signal line 108, an input/output (I/O) unit 110 and signal line 102. The I/O unit may be thought of, for the purposes described thus far, as simply a short circuit from signal line 108 to signal line 102, Le., it scrves no function relevant 10 the present level of disclosure. (It will, however, be important with respect to a subsequent level of disclosure in connection with a

12

.

MIL-STD-1750 embodiment of the present invention and is therefore included in FIG. 3 for that purpose). If the control 30 selects an operation for the ALU 104 which involves an ALU output signal on the line 100 into a register or register pair in the register file 74, as decoded from the secondary register in the instruction register 34, the output of the ALU is clocked into the selected register or register pair in the register file 74 at the beginning of the second quarter of the machine cycle as indicated by a rising edge 112 of a waveform 114 in FIG. k ) . This waveform represents the voltage q present on aclock line 116 shown in FIG.3 for clocking the register which is to be written into by the ALU 104. Thus, during the first half of each machine cycle, the control unit 30 decodes the instruction register 34 pipe to determine a pair of registers in the register file to be accessed for loading the destination and source registers 76,78 and decodes the secondary register in the instruction register 34 for the purpose of determining which register in the register file 74 is to be loaded with the input bus 102 or with output of the ALU from the previous machine cycle. T h e ALU output signal on line 100 or data on line 102 is loaded in the selected register or register pair on the rising edge of CK2 while the destination and source registers are loaded on the rising edge 25 of CK3. If the opcode decoded from the instruction in the secondary register in the instruction register 34 turns out to be a load/store instruction for loading or storing data from or to an external memory space, then there 30 will have to be an operand address output from the source register 78 onto the operand address bus 16 via a signal line 118 and a buffer 120. The control 30 will of course enable the buffer 120 for the purpose of passing the signal on line 118 over to the operand address bus 35 15. This will occur on the rising edge of CK3 as clocked on signal lines 117u and 117b. On a load operation, an operand will then appear on the data bus 18 from the memory which will be routed into the register file 74 via buffer 106, as enabled by the control 30, line 108, 40 I/O 110, and signal line 102. The destination field of the RISC instruction residing in the secondary register in the instruction register 34 is us&, as it was for an instruction relating to an ALU operation, for designation the register within the register file 74 into which the 45 operand is to be loaded. Again, this occurs on the rising edge of CK.2 as shown in waveform 114 of FIG. q k ) . On a store operation, an operand will be provided on the data bus 18 from the reaster pointed toby the destination field of the instruction which is loaded into the 50 destination register 76. Thusfar, the control unit 30 has been described performing its functions of fetching RISC instructions by incremeniing the instruction counter 32,decoding current instructions received in both the primary ("pipe") 55 register and secondary register of an instruction register 34 for performing various control functions internally within the RISC machine 10, including seIecting registers to be operated on within the register file 74 and storing them into source and destination registers 76.78, 60 and loading either an ALU output signal from the previous instruction into a selected register in the register file 74 or ioading an operand from the data bus 18 if the decoded operand indicates a load operation from mem65 ow. The next control function to be described is the selection of inputs to the ALU 104 through a pair of multiplexers 124, 126. The first multiplexer 124 provides a

13

4.992.934

first input signal 128 to a first input of the ALU 104. The second multiplexer 126 provides a second input signal on a line 130 to a second input of the ALU 104. These input signals are selected by means of select lines 132. 134 from among several different input signals to each multiplexer. The select lines are provided by decoding the secondary instruction register and are present by the time of occurrence of the rising edge of CK3. In other words, when the destination and source registers 76, 78 have been loaded with the selected registers then the multiplexers will be selected. If the destination and source registers 76, 78 are selected for having their contents operated on by the ALU 104 then thew contents will be transferred via lines 118 and 136 and through the respective multiplexers 124, 126 into the proper inputs of the ALU for having the proper operation executed. The control unit 30 also selects the operation to be performed by the ALU by decoding the opcode while it resides in the secondary instruction register. This would normally occur sometime after the rising edge of CK3. The ALL! is capable of the standard repertoire of operations including ADD, AND, OR. and EXCLUSIVE OR. Once the output of the multiplexers have stabilized the operation is then stabilized in hardware to provide a stable output on the line 100. For the RISC 10 illustrated in FIG.3, at the present level of disclosure, Le.. in connection with the first aspect of the present invention, each of the multiplexers 124, 126 is responsive to only two separate signals. Additional signals will be described later in connection with another level of disclosure for describing the second aspect of the present invention. The other inputs to the multiplexers, for the RISC level of disclosure, are connected with the RISC instruction and instruction address buses. Thus, multiplexer 124 is responsive to an instruction signal on a line 136 from the control unit 30. This would correspond to an immediate data field residing in the secondary register of the instruction register 34 which would be transferred into the multiplexer 124 during the third quarter 44 of the particular machine cycle in which it was desired to perform an operation on a RISC instruction. These would be few and far between, however, as compared to for example. the normal internal operations in which data is manipulated rather than an immediate data field (in the instruction). Register-to-Immediate instructions will be described below, in connection with the description of the RISC instruction set. The multiplexer 126 is also responsive. at this level of disclosure, to a RISC instruction address signal from the instruction address bus 12. Such addresses may also be manipulated from time to tme. Thus, the control unit 30 selects inputs to the ALU through the multiplexers 124, 126 for operation therein. according to the opcode. It also selects, according to the opcode, the particular operation to be performed on the input signals by the ALU. The operation is performed by hardwired logic which produces a stable output signal o n the line 100 after the inputs become stable. This normally takes place during the latter half of the machine cycle and on into the first quarter of the' next machine cycle. The output of the ALU is not loaded into the intended destination until the rising edge of the second quarter of the next machine cycle, i.e., corresponding to rising edge 112 of waveform 114 in FIG. 4(k). The destinations for the ALU output signal on line 100 may be a register in the register file 74, the instruction counter 32 or an accumulator 140. The accumulator is for the purpose of performing shift, multiply

14

operations (where a bit is changed). A 32-bit word from and divide operations and is also loaded with the output the BIT decoder 188 is split into a most significant half of the ALU on the rising edge of C K 2 during selected on a line 192 and a least significant half on a linq 194 for machine cycles, as is done with the loading of register files with ALU output signals following the ALU operpresentation to the first and second mulriplexers 180, 182, respectively. The first multiplexer selects the most ation. significant half output of a register file or selects a BIT The control unit 30 also updates sysrem status and field on a BIT instruction. I t also sign extends bit 16 checks for exception program flow (interrupts, calls, jumps). Appropriate control signals are provided to the output of the register file (forces to all ones or zeros). various functional entities shown in FIG. 3 in such The second multiplexer 182 selects the least significani half output of the register file or selects the BIT field on cases. BIT instructions. It also swaps the lower 8-bits and Referring now to FIG. 5, a more detailed illustration upper 8-bits on BYTE SWAP instruction. of the register file 74 of FIG. 3 is there shown. The The selected most significant half on a line 168a and internal data bus 102 is shown provided to a first 3:l multiplexer 150 and to a second 3:l multiplexer 152 the selected least significant half on a line 1686 is prowhich selects between the internal data bus 102 and the vided to the source register 78 which, as described ALU output signal on the line 100, which is split in before in connection with FIG. 3, is a temporary regisFIG. 5, between a most significant half of the ALU ter used to hold the derived source data field, prior to performing an ALU operation thereon. The source is output on a signal line 1ODa and the least significant half of the ALU output on a signal line 1006, Each of these also used to provide an operand address prior to loading lines 1o00, 1006 are also presented to both the first and u) or storing a register to or from memory. This is illustrated in FIG. 3 in which the output line 118 is provided second multiplexers 150, 152. The control unit 30 of FIG. 3 controls which multiplexer 150, 152 and which to a buffer 120 which in turn provides the operand path 100, 102 feeds the registers. address signal on a line 16 to the operand memory The register file 74 itself comprises a group of 20 space. As mentioned, the output signal 118, if not pergeneral purpose registers. The register file can be 25 forming an operand addressing function, is provided to loaded with either ALU data from the signal line 100 or a multipiexer 124 along with an instruction line 136 for providing a fint input signal 128 to the ALU 104. as operand data from the signal line 102 (originating on the data bus 18). RISC instructions perform operations on better shown in FIG. 3. these registers. FIG.5 shows the registers split into two Referring now to FIG. 7, an illustration is there progroups, a first ("even") group 740 (RpR14 & A0 & AZ), M vided of a destination module, similar to the destinalton is responsive to an output signal on a line 154 from the module 76 illustrated in FIG. 3. The output signal on first multiplexer 150 and comprises IO general purpose the line 166 from the multiplexer 158 in the register file registers. A second ("odd") group (R]-Rl5& A1 & A3) 74 is provided to a 32-bit shifter multiplexer 200 which of general purpose registers 74b is responsive to a secallows right shift, left shift or no shift on each clock ond signal on a line 156 from the second multiplexer 35 signal on 16 and 32-bit words. It shifts logically, arirh. 152. Any of the registers in either group 74a, 746 may metically, and cyclically. The output of the shifter mux provide its contents to a third multiplexer 158 or a Mo is provided on a line 202 to a destination register fourth multiplexer 160 over signal lines 162, 164. The 2W.This register may be thought of as a temporar? third multiplexer i s a 20: 1 multiplexer for providing an register used to hold the derived destination data field output signal 166 to the destination register 76 of FIG. 40 output of shifter multiplexer 200. The output of thc 3. The fourth multiplexer 160 is also a 20: 1 multiplexer destination register 204 is provided on the line 136 I C ) the multiplexer 126 for providing the second input kig. and provides an output signal on a line 168 to the source nal on the line 130 to the ALU 104 of FIG. 3. Thc register 78 of FIG. 3. destination module 76 is also used to provide operand In the embodiment of FIG. 3, the ALU is a 32-bit ALL' while the data and data address buses 18, 16, as 45 data prior to storing a register to memory. The desrrnawell as the instruction and instruction address buses 14, tion can also be shifted right or left 1-bit per c l x k and 12,are only 16-bit. Therefore, for the structure of FIG. is used to perform shift, multiply and divide operations 5, the internal data bus 102 is 16-bit, the most significant Referring now to FIG. 8, an illustration is there prohalf of the ALU signal output line lo00 is also 16-bits, as vided of an accumulator module 210 similar to the accuis the least significant half signal on line 1006. The multi- 50 mulator 140 shown in FIG. 3. The ALU output signal on the line 100 is provided to a 2:l multiplexer 212 plexer output lines 154, 156 are therefore also 16-bit as are all the general purpose registers 74u, 745. Each of which is also responsive to an accumulator register 216 the 2O:l multiplexers 158, 160 constructs a 32-bit word, output signal on a line 218. The multiplexer provides a the most significant half taken from one of the ten regis32-bit output signal on a line 220 to a shifter multiplexer ters in the group 74b and the least significant half taken 5 5 222 which permits right shift. left shift or no shift operafrom any one of the registers in either group 740 or 746. tions as required for multiplication, division. and &bit Thus, the destination and source output signals 166, 168 shifts (it is concatenated with the destination register). are 32-bit words. The output of the shifter multiplexer 222 is provided o n Referring now to FIG. 6, an illustration of a source a line 224 to the accumulator register 216. The accumumodule such as the source module 78 shown in FIG. 3 M) lator module 210 as a whole may a b b e used for temis there illustrated. The signal on line 168 is a 32-bit porary storage of data. It should be noted that the resignal and it is split into two 16-bit words at a point 174 sults of multiplication and division are formulated in the destination module 76 and the accumulator module 140 for presentation as an upper 16-bits on a line 176 and a or 210. lower significant half on a line 178 to, respectively, a fint 3:1 multiplexer 180 and a second 3:1 multiplexer 65 The signal processor of FIG. 3 has two basic instruc182. At a point 184 the least significant 5-bits of the tion formats that support 16 and 32-bit instructions. The 32-bit word on line 168 is provided on a line 186 to a operation code (opcode) consists of the six most signifiBIT decoder which selects the appropriate bit for all bit cant bits of the instruction. Table I shaws the opcode
'

15 --

4,992,934

16

matrix of thirty-two instructions. The opcode's upper 2-bits and next lower 3-bits select, respectively, the column and row for which an instruction is located. The two instruction fonnats are ( I ) register-to-register (RR);and (2) register-to-immediate (RI). The least sig- 5 niticant bit of the &bit opcode selects the format by which the instruction is to be interpreted. Each of the 32 instructions may be executed in each format, depending on the.sixth bit.

17

4,992,934

18
TABLE II-continued
Drstinatron and Source Field scleciian
When RS will
SCkt

fi"; S RD F
ollll
'.*"

field value
Illll

will
Iclctl

RD

Wlll vlcct

RS

RF
'&"

RF
cx~mlwn lieid lor IwrCc'

ACC

ACC

TABLE
00
My)

r

lo for the two halves of the register file 74 of FIG. 5.
10

Table 11 is an illustration of the organization selected TABLE 111

01

I1

011 100 IO1
110

001 010

Ill

MOV LR STR CALL MOVC 1NR OTR JCR

ADD ADDC AB ADDU SUB SUBB
SB

CMP

AND OR XOR NOT RBR SBR TBR LRI

MULS
SWAB

SLL SAR SCR

15

MOVB

STRI
20

DIV

Rcgrstei Pair XRO XR2 XR4 XR6 XR8 XRA XRC XRE XAO XA2

The register-to-register format IS a 1 &bit instruction consisting of a &bit opcode and two 5-bit regmer fields The register field can select any one of ( I ) 20 general registers, (2) ten general register pairs, or (3) one accumulator 25

The left-hand (16-Bits) column of the table corresponds to the ten registers 74u and the right-hand (16-Bits) column of the table corresponds to the ten registers 7#. [ oxxxxx 1 RD 1 J If IO 9 54 0 30 As mentioned previously, the registers can be selected for operation in pairs in order to form 32-bit words. The The register-to-register destination (RD) and saurce nomenclature for the register pairs shown in Table 111 (RS) field can be selected according to Table 11. and are also reflected in Table I1 for selection by the register field in the register-to-register instruction. The T P B L E I1 35 AO-A3 registers are generally used for holding intermeDcstmauon and Source Field rtlectwn diate results. B I ~ W h c n R D WhcnRS Bit WheoRD W n R S The Register Immediate format is a 32-bit instruction field wll Wlll field will Wlll consisting of a &bit opcode, one 5-bit register address, a value Wlcci rciecc value deet Xlax %bit code indicating an immediate instruction and a Mx)oo RO RO IMXX) XRO XRO oooO1 R i RI lWl XR2 XR2 40 16-bit data field.

I

MSB

w

e

I

Dcstraatron

I

Source LSB RS

1

aMl0 R2 aM11 R 3

00101 RS 00110 R6 00111 R7
OIMy)

ODIC0 R4

OllW 01101 OIL10

OIOIO OIOll

01001

R8 R9 RA RB RC RD RE

R2 R3 R4 85 R6 R7 R8 R9 RA RB RC RD RE

lo010 X R 4

lWll

IO102 lOll0 10111

IOIOI

11100 XAO I1101 XAZ 11110

llM0 A 0 llWI AI I1010 A2 11011 A 3

XR6 XR8 XRA XRC XRE

XR4 XR6 XR8 XU XRC XRE A0 AI A2

45

oxx xxx

RD

1l110

16-811
Irnrnedutie

A3

-

XAO XA2

"IMM

50

T H E RISC INSTRUCTION S E T REGISTER ADDR TRANSFER MODE MNEMONIC DESCRIPTION CPZNV .+I .. RR MOVRD.RS RD-RS ***** RR L R RD,RS I F ( R S = SP) THEN RS R S + I: R D @(RS): I F (RS I = SP) THEN R S @(RS1: RR STR RD.RS IFfRS = SP) THEN RS c R S - 1: R S WRD); IF (RS != SP)

-

-

REGISTERS AFFECTED RD RD.SP

-

19
-continued
ADDR MODE RR RR RR RR RR

4,992,934

20

THE RISC INSTRUCTION SET REGISTER TRANSFER MNEMONIC DESCRIPTION CPZNV CALL RD.RS

RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR

THEN RS @!(RD). RD-FC + 2 PC RS MOVC RD.RS RD- RS INR RD.RS @fRS). RD OTR RD,RS @(RS) RD. IF (SW = N) JCR N.RS THEN PC PC + RS. ELSE P C - P c + 1. ADD RD. RS RD RD + RS. ADDC RD.RS RD RD + RS + C, AB RD,RS RD7-0- RD7-o + RSi - 0. ADDU RD,RS R D - R D i R S . RD-RD+RS+l. SUE RD,RS RD RD + RS + C. SUBB RD.RS SB RD.RS RD7-0- RD7-0 * RS7-o TI. CMP RD, RS RD:R$; XOR RD.RS RD RD % R S RD c RS: NOT RD.RS RBR RD.RS RD c RD AND BIT(RS). RD RD AND BIT(RS1, SBR RD.RS ALU T B R RD.RS RD AND BlT(RSh LRI RD,RS RD (RS), RD R D S H I F f (RS). SLR RD,RS SAR RD,RS RD RD SHIFT (RS), SCR RD.RS RD RD S H I F T (RS), MULS RD,RS RD RD * RS, MOVB RD.RS RDi-o RS7-o, SWAB RD.RS RDIJ-8 RS7-a RSi5-8, RD7-o RD c RD / RS 6 DIV RD.RS STRI RD.RS

---

REGISTERS AFFECTED

.*I ..

OPZNO
*. . I .
* . I *

..*..

pc. SP
RD, SW RD, SP SP PC

CPZNV CPZNV CPZNV CPZN' CPZNV CPZNV CPZNV
OPZNOPZN' OPZN'

RD. SW RD. SW RD, SW RD, RD. RD, RD.
SW SW SW SW

sw

--

OPZNn
Q+v..

.....
e . .. . .e

RD. SW RD. SW RD RD

sw

-

OPZN' OPZN' OPZN*
. I . *

.*.."

RD RD, RD, RD, RD. RD RD RD

SW SW SW SW

.V

SET Each of the RISC instructions described below i s described for the register-to-register format. However, it will be understood that each has a register-to-immediate format counterpart which may be designated by the status of t h e sixth, or least significant bit of the opcode. The Move instruction (MOV) allows the contents of the source register (RS) to be moved to the destination register (RD). The Load Register instruction (LR) moves the contents of the memory location pointed to by RS to RD. I f RS is the Stack Pointer (SP), then the SP is incremented prior to the load. The Store Register instruction (STR) stores the contents of R D into the memory location pointed to by RS. If RS is the stack pointer, then the SP is decremented. The Call instruction (CALL) loads the contents of program counter plus two into the register pointed to by RD. The