Elan Microelectronics Corporation v. Apple, Inc.
Filing
214
Declaration of Jennifer Liu in Support of 212 MOTION for Partial Summary Judgment of Infringement of U.S. Patent 5,875,352 [Public Version] MOTION for Partial Summary Judgment of Infringement of U.S. Patent 5,875,352 [Public Version] filed byElan Microelectronics Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3-6 MFN, # 4 Exhibit 7, # 5 Exhibit 8, # 6 Exhibit 9, # 7 Exhibit 10, # 8 Exhibit 11, # 9 Exhibit 12, # 10 Exhibit 13, # 11 Exhibit 14, # 12 Exhibit 15, # 13 Exhibit 16, # 14 Exhibit 17, # 15 Exhibit 18, # 16 Exhibit 19, # 17 Exhibit 20, # 18 Exhibit 21, # 19 Exhibit 22, # 20 Exhibit 23-25 MFN, # 21 Exhibit 26, # 22 Exhibit 27 MFN, # 23 Exhibit 28, # 24 Exhibit 29-33 MFN, # 25 Exhibit 34, # 26 Exhibit 35-37 MFN, # 27 Exhibit 38 Part 1, # 28 Exhibit 38 Part 2, # 29 Exhibit 38 Part 3, # 30 Exhibit 39-45 MFN, # 31 Exhibit 46, # 32 Exhibit 47 MFN, # 33 Exhibit 48)(Related document(s) 212 ) (Liu, Jennifer) (Filed on 5/24/2011)
Pin Information
CYPRESS
PERFORM
This
chapter
describes
and
lists
CY8C21x34
the
illustrates
PSoC device
and
pins
pinout
configurations
Pinouts
1.1
P5cC
The CY8C21x34
pin
labeled
not
capable
of
device
with
11.1
is
1-1 16-Pin
No
in
variety
and
10
Digital
of
which
packages
connection
to
the
are
common
and
listed
analog
illustrated
the
following
Vss Vdd
tables
SMP
and
Every
port
XRES
are
SOIC
Pinout
CY8C2I
Name
234
16-Pin
PSoC
Device
Description
Analog
Digital
P0
PO
10
10
10
Analog
mux
input
PJt4
16
column
max
input
FjMlml5
15
Analog
P013
column
Analog
column
max
input
P0
10
column
max
input
integrating
SOIC
m4AM
13
m2JAM
12
lMR1t
Analog
14
Pjt4mp
integrating
input
FOOIA
11
input
Mode
SMP
Power
SMP
Power
vsa
Ground
P1
12C
\/ss
Ground
10
P110
12C
10
11
10
P1
Optional
12
10
POlO
Analog
column
max
13
10
P0
Analog
column
max
14
10
P014
Analog
column
max
P016
Analog
column
max
P1
P1
input
Vdd
10
input
10
Ml2ClP1l1
P112
Supply voltage
Switch
10
Power
10
15
Power
16
LEGEND
Analog
These
are
See
PSoC
the
March
29
the
ISSP
Mixed-Signal
are
Serial
Array
Technical
Vss
components
SCL
clock
SDA
Date
External
P10l2CM
ISSP-ScLK
High
ISSP-SDATA
Clock
und
POR
Reference
EX1tLK
Input
input
input
Analog
at
Max
Power
Manual
Input
On
Reset
for details
Document
2006
CONFIDENTIAL
to
connection
Serial
not
connection
connection
Output
Input
pins which
Pump
external
required
HIGHLY
in
bus Howeve
Part Pinout
Part
Type
Pin
of
IC
Digital
16-Pin
Table
available
is
capable
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
APCY00009764
ATTORNEYS
EYES ONLY
APE
L001 0829
CY8C21x34
Final
1.1.2
20-Pin
Table
Data
1-2 20-Pin
Pin
No
Pad
Part
Type
Sheet
Pin
Pinout
SSOP
Pinout
CY8C21334
Name
10
P0
P0
P0
lM
10
lM
10
Analog
colamn
mux
inpat
colamn
mux
lMFD
Analog
inpat
Analog
colamn
mux
inpat
intngrnting
AlMPD
AlMRD
colamn
mux
inpat
integrating
Analog
Power
10
10
13
10
Ground
P1
P1
P1
10
12C
Vss
10
Ground
P1
P1
P1
P1
10
RJ
EO
17
18
120
14
MF1
SCL
Clock
Serial
15
Ml2CSJAP1
connaction
13
MI2CflP1
l2oSnrialDntnSDA
12
10
12C
PJ6PlM
18
Ml2CSLP1L7I
Vss
10
\di
10
ssoi
inpat
Power
12
PSoC Device
20
AlMFtJ
inpat
P0
10
11
20-Pin
Description
nalog
Digital
10
Information
11
P1
P1
P1
P1
SCL lSSPSCLK
Clock
Serial
XRES
connection
SDA
Data
Serial
Clock
External
Optional
lSSPSDATA
Inpat
EXT
CLK
14
P1
10
15
XRES
Inpat
Active
pall
16
10
10
lM
18
10
lM
19
10
20
Power
LEGEND
These
See
the
March
HIGHLY
P0
P0
P0
P0
lM
17
the
PSoC
29
ISSP
with
internal
Mae
colemn
mnx
Inpet
inpat
colemn
mux
inpat
Analog
colemn
mux
inpat
Analog
colemn
mux
inpat
Supply voltage
Oetpet
Inpat
are
Array
not
High
Technical
and
at
Analog
POR
Reference
Power
Maneal
On
Reset
for details
Document
2006
CONFIDENTIAL
reset
Analog
pins which
Mixed-Signal
external
Analog
Vdd
Analog
are
high
down
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
APCY00009765
ATTORNEYS
EYES ONLY
APE
LOOl 0830
CY8C21x34
Final
1.1.3
28-Pin
Table
1-3 28-Pin
Data
Pin
No
Pad
Pin
SSOP
CY8C2I
Name
P0
P0
10
10
Analog
column
ear
Analog
column
max
column
max
pul
input
and
colurnu
IMPJ
columu
AlMFC
AlMFC
input
and
output
10
P0
Analog
10
POFI
Analog
output
intugrating
column
AIMPC11
iuput
max
input
P2
MFQ
MFQ
intugruting
input
10
P2L7
10
P2F5
10
Power
10
10
Power
14
15
10
17
10
capacitor
block
iupat
I2CflE1
switched
capacitor
block
iupat
2CSDA
Ground
28-Pin
PSoC
Device
Serial
Serial
Data
12C
Serial
SCL
Clock
12C
Clock
Ground
P1LO
12C
P1
P1
F2
P2
P2
IRES
Pt
Pip
conuoction
12C
PO
RJ
PO
PJ
F2
P1
P14 BCFCJ
I2CLP1
Vss
10
16
switched
Direct
P1
P1
P1
P1
10
13
Direct
Vus
10
12
MP2
P2
P2
10
11
534
Description
Analog
Digital
10
Information
Pinout
Pinout
Part
Type
Sheet
SDA
P1
P12
Vss
SCL lSSPSCLK
conuection
SDA
Data
Serial
Optioual
Clock
External
lSSPSDATA
EXT
luput
CLK
16
P1
10
19
XRES
lupnt
Active
pull
20
10
22
10
23
10
24
10
25
10
26
10
27
P2
P2
P2
10
21
10
28
the
March
HIGHLY
reset
with
iuternal
Direct
smitched
capacitor
block
iupat
Direct
P0
P0
P0
P0
LEGEND
See
external
smitched
capacitor
block
iupat
P2F6
Power
These
high
down
the
PSoC
29
ISSP
max
input
column
max
input
Analog
column
max
input
Analog
column
max
input
Supply votage
Output
Input
pius which
Mixod-Sigunl
column
Analog
Vdd
Analog
are
Analog
are
Array
uot
Technical
and
High
Aualog
at
PCR
Roforouco
Muuuul
lupat
Cu
Reset
for details
Document
2006
CONFIDENTIAL
Mux
Power
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
-ATTORNEYS EYES ONLY
10
APCY00009766
APELOO1 0831
CY8C21x34
Final
1.1.4
32-Pin
Table
1-4 32-Pin
Data
Pin
QFN
Pinout
CY8C21434
Name
32-Pin
10
POll
column
Analog
mux
input
Device
integrating
input
cc
10
P217
10
P2
P2
10
10
tO
lull.
CY8C21434
In
SMP
Modn
Switch
CO
CO
Pump
external
required
components
to
in
P2
NI
10
NI
10
10
NI
Ground
11
10
12C
Serial
pert
120
Serial
SCL
Clock
P115
Power
Data
120
13
RD
NI
P110
14
10
NI
10
NI
P114
15
10
NI
Top
SOt
P1171
.8
lSSPSDATA
10
NI
10
NI
10
NI
10
NI
10
with
CY8C21634
internul
P2101
P3101
XRES
CO
00
CO
32-Pin
LU
PSoC
Device
cC
P2
22
reuet
CO
00
P210
21
EXTCLK
Input
P312
20
P2121
ooco
ci-o
P3
19
Clock
externnl
P2141
down
pull
16
high
P3121
cr
CD
CO
DI
Active
P2161
05H
SDA
External
Optional
XRES
Input
Serial
P0101
liii
SCL lSSPSCLK
connection
Data
CO
P1
120
View
.6
P1
15
120
24
23
22
21
20
P3111
SDA
Clock
Serial
Ground
CD
CO
QFN
00
Vxn
II
CD
CO
19
18
17
.4
P2111
CY8C21634
in
connection
P117
P1
P1
NCO
.3
P3131
10
Ce
CO
P2171
InCY5C2l434pnrt
Van
Power
connection
CO
CO
CO
part
P3
NI
SNIP
CO
P0111
P2131
CY8C21634
10
Al
part
Of
o_ uo
o_
P3
Power
Ccc
cC
00
P211
10
17
PSoC
Descnption
Analog
Digital
12
Information
Part Pinout
Part
Type
No
Sheet
cCc
CO
P214
411
23
10
24
10
P0
Analog
column
mux
input
25
10
P012
Analog
column
mux
input
26
10
P014
Analog
column
mux
input
27
10
P0
Analog
column
mux
input
Vdd
Supply voltage
Analog
column
max
Analog
column
mux
column
max
input
CD
ca
CD
CD
III
CD
II
input
Analog
CD
input
26
CO
CO
P216
NI
Power
10
P017
30
10
P0
P0
10
31
Power
Vss
LEGEND
Analog
Thuuu
am thu ISSP pins
PSoC Mixed-Signal
Seethe
The
center
pad on
for best
mechunicel
ground
it
March
should
29
the
which
OFN
electrically
are
Array
not
and
Technical
POR
Reference
120
SCL
Manual
and
not
connected
CD
CO
P091
P26
.3
23
22
21
20
P2
P2
OFN
.4
.6
Top
P1
.0
to
not
to
C5-i
Reset
other
CO
CO
P24
P2
CO
.iii 1111
7F
EETE
---o0-a
o-O-
ground
Wss
connected
to
any
CD
IA
P20
19 P3
10 P30
17 XRES
View
.6
for details
Document
ATTORNEYS
CO
24
00
If
floated
NCO
.3
CD
Input
On
Powur
should
be connected
puckugu
and electrical
performance
2006
CONFIDENTIAL
Mux
Analog
ut
High
CD
CO
Ysu
Ni
integrating
connection
Output
leput
thermal
be
Ground
CD
CO
CO
.1
P25
NI
input
32
CO
P01
P27
Al
SMP
29
HIGHLY
CD
ci
co
01
11
signal
No
00
38-1
2025
Rev
11
EYES ONLY
CONFIDENTIAL
APCY00009767
ATTORNEYS
EYES ONLY
APE
LOOl 0832
CY8C21x34
Final
1.1.5
56-Pin
SSOP
The
56-pin
Note
This
Table
1-5 56-Pin
part
is
Data
Sheet
Pad
part
is
Part
CY8C2IODI
for
Pinout
in-circuit
Debug
On-Chip
debugging
It
OCD
NOT
is
PSoC device
available
for
production
SSOP
CY8C2IOOI
Power
ID
____________
Io
10
10
I0
I0
Vss
Ground
Device
Vdd
column
Analog
P0
P2
mux
Analog
POF3
column
column
PO
PO
PO
Al
PC4
Al
FC
Al
Al
PO1
FCO
Al
P2
P2
P2
P2
input
PC
Al
mux
Analog
P26
Al
input
and
column
mux
input
and
column
mux
Al
input
output
output
F24
F22
P2O
NC
NC
P2
P2
I0
PSoC
connection
column
Analog
P2F5
I0
56-Pin
Vss
PO
PO
Direct
switched
Direct
capacitor
NC
No
NC
No
block
input
NC
P32
NC
connection.
NC
NC
input
connection
11
block
capacitor
switched
10
P3O
OCDE
COLK
HCLK
0000
12
NC
No
NC
No
SMP
connection
13
connection.
XRES
Vss
14
OCD
OCDE
OCD
even
15
ocpj
DCDO
OCD
odd
SMP
Switch
16
Power
data
Pump
external
connection
Ground
NC
120
conneGtion
Vss
Ground
SCL
P117
P16
SDA
Pl
F14
connection
NC
21
NC
No
connection
22
NC
No
SCL
P1O
P11
NC
Vss
P3
120
EXTCLK
F1
P13
SCLK
P3F3
10
NC
NC
to
12C
Vss
10
20
SMP
components
Power
19
NC
NC
NC
output
PoweF
18
NC
P3
P3
10
data
NC
Vss
Mode
required
17
Information
Pinout
for the
used
only
Pin
NC
120
SDA
SDATA
connection.
23
10
P1
12C
Serial
Clock
24
ID
P1L5
12C
Serial
Data
25
NC
No
26
P1
P1
27
Not
for
Production
SCL
SDA
connection
Crystal
Input
XTALin
12C
Serial
Clock
SCL lSSPSCLK
28
Power
Vss
Ground
NC
29
No
connection
No
connection.
NC
30
31
ID
P1LO
connection
SDA
32
10
34
P1
P1
P1
10
33
ID
12C
XTALout
lSSPSDATA
Output
Crystal
Serial
Data
VFMTEST
Optional
Clock
External
35
NC
No
NC
No
connection
37
NC
No
connection.
38
NC
No
connection
39
NC
No
connection.
40
NC
No
EXTCLK
connection.
36
Input
connection.
41
Input
XRES
Active
high
external
reset
with
internal
pull
down
42
OCD
HCLK
OCD
43
OCD
CCLK
OCD CPU
44
10
45
10
46
NC
No
connection
47
NC
No
connection.
March
HIGHLY
29
high-speed
clock
output
Document
2006
CONFIDENTIAL
clock
output
ATTORNEYS
No
38-1
2025
Rev
12
EYES ONLY
CONFIDENTIAL
APCY00009768
ATTORNEYS
EYES ONLY
APE
LOOl 0833
CY8C21x34
Table
Final
1-5 56-Pin
Data
Part
Sheet
Pinout
48
10
ID
10
51
10
52
ID
53
ID
54
ID
55
ID
SSOP
P2L2
50
Information
P2
49
56
P2
P2
P0
March
column
max
inpet
Analog
column
max
inpet
and
colemn
oetpet
Analog
column
max
inpet
and
colemn
oetpet
Analog
column
max
inpet
P0
P0
Power
These
Analog
POF2
LEGEND
HIGHLY
Pin
em
29
Vdd
Analog
the
ISSP
Supply voltage
Oatpat
Input
pins which
are
not
High
and
OCD
at
POR
Debug
On
React
Document
2006
CONFIDENTIAL
On-Chip
Power
ATTORNEYS
Sue
No
the
38-1
PSoC
2025
Mixed-Signal
Array
Technical
Ref crenco
Manualfom
Rev
13
EYES ONLY
CONFIDENTIAL
details
APCY00009769
ATTORNEYS
EYES ONLY
APE
LOOl 0834
Register Reference
CYPRESS
FORM
PER
This
chapter
PSoC
the
CY8C21x34
of the
registers
Reference
Technical
PSoC device
For
register
following
conventions
to
specific
this
section
detailed
register
2.2
are
listed
in
The
the
table
P5cC
bit
Write
register
Logical
Clearable
Access
March
HIGHLY
29
or
register
is
bit
two
into
set
or
In
Reserved
bits
banks
which
total
is
space
The
bank
the
user
the
following
is
in
the
address
register
referred
X0l
bit
user
in
is
space
of
as
space
and
to
the
10
Flag
currently
register
in
When
512
is
CPU_F
the
X0l
Bank
and
should
register
not
mapping
tables
blank
fields
are
be accessed
bits
specific
Document
2006
CONFIDENTIAL
is
Note
bits
or
register
Tables
bits
or
register
register
determines
Description
has
device
The
divided
Read
the
Register Mapping
bytes
Convention
reference
information
Manual
Register Conventions
2.1
The
lists
Mixed-Signal Array
ATTORNEYS
No
38-1
2025
Rev
14
EYES ONLY
CONFIDENTIAL
APCY0000977O
ATTORNEYS
EYES ONLY
APE
LOOl 0835
CY8C21x34
Final
Register
Map
Data
Sheet
Table
Ia
ma
Di
Register
User Space
ci
CD
ma
00
PRTOIE
01
PRTOGS
02
PRTODM2
03
PRT1DR
04
PRTIIE
05
PRTIGS
06
PRT1DM2
07
PRT2DR
08
PRT2IE
09
PRT2GS
OA
PRT2DM2
OB
PRT3DR
OC
PRT3IE
00
PRT3GS
OF
PRT3DM2
OF
Ia
ma
Di
C-C
CD
PRTODR
Ia
to
C-i
CD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ACE10CRO
40
CC
CD
80
RW
CO
41
81
Cl
42
82
C2
43
83
ASE11CRO
44
84
C3
RW
C4
45
85
CS
46
86
C6
47
87
C7
48
88
C8
49
89
C9
4A
BA
CA
4B
8B
CB
4C
BC
CC
4D
3D
CD
4E
BE
CF
4F
BF
10
50
90
CUR_PP
DO
11
51
91
STK_PP
Dl
12
52
92
13
53
93
lOX_PP
D3
14
54
94
MVR_PP
04
15
55
95
MVW_PP
DS
16
56
96
I2CCFC
06
17
57
97
12C_SCR
07
18
58
98
CC_DR
08
19
59
99
12C_MSCR
09
IA
BA
9A
INT_CLRO
DA
lB
SB
9B
INT
DB
1C
SC
9C
10
SD
9D
INT_CLR3
DD
iF
SE
9E
INT_MSK3
OF
IF
DBBOODRO
21
DBB000R2
22
DBBOOCRO
24
DBBOIDRI
26
PWV1_CR
62
25
DBBOIDR2
60
23
DBBOIDRO
SF
AMX IN
AMUXCFG
20
DBB000R1
RW
61
CF
CLRI
RW
RW
OF
Al
INT_MSK1
El
RW
RW
RC
MSKO
BO
A2
INT_VC
E2
A3
RES_WDT
E3
64
A4
A5
66
RW
E4
ES
A6
DEC_CRO
E6
67
CMP_CRI
RW
RW
INT
65
RW
RW
AO
63
CMP_CRO
RW
RW
RW
RW
DC
9F
RW
RW
RW
RW
RW
D2
A7
DEC_CR1
E7
CR0
27
DCBO2DRO
28
ADCOCR
68
A8
29
ADC1_CR
69
A9
E9
DCBO2DR2
2A
GA
AA
EA
DCBO2CRO
2B
6B
AB
EB
DCBO3DRO
2C
TMP_DRO
6C
AC
EC
DCBO3DR1
20
TMP_DR1
GD
AD
ED
DCBO3DR2
2E
TMP_DR2
GE
AE
FE
DCBO3CRO
2F
TMP_DR3
GF
RW
RW
E8
DCBO2DR1
DBBO1
RW
RW
RW
RW
RW
RW
AF
30
70
RDIORI
BO
31
71
RDIOSYN
61
RDIOIS
B2
RDIOLTO
B3
32
ACEOOCR1
72
33
ACEOOCR2
73
RW
RW
34
74
RDIOLTI
B4
35
75
RDIOROO
BS
RDIOROI
B6
36
ACEOI CR1
76
37
ACEO1 CR2
77
RW
RW
EF
RW
RW
RW
RW
RW
RW
RW
67
FO
El
F2
F3
F4
FS
F6
CPU_F
P7
38
78
B8
79
69
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
30
70
60
DAC_D
PD
3E
7E
BE
CPU_SCR1
FE
BF
CPU_SCRO
FF
3F
Blank
fields are
March
29
RL
F8
39
HIGHLY
Reference
Reserved
7F
and
shoald
net
be accessed
Document
2006
CONFIDENTIAL
Access
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CONFIDENTIAL
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15
APCY00009771
APELOO1 0836
CY8C21x34
Final
Register
Map
Data
Sheet
Register
Table Configuration
ia
ma
Ia
ma
CD
CD
DPTOrCCvCr
00
PRTODMI
01
PRTOICO
02
PRTOIC1
03
PRT1DMO
04
PRT1DM1
05
PRTIICO
06
PRTIICI
07
PRT2DMO
08
PRT2DM1
09
PRT2ICO
OA
PRT2IC1
05
Space
Ia
ma
CD
DC
FI
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CD
ia
ma
CD
DC
erinron
40
DCC
80
41
81
Cl
42
82
C2
43
83
ASE11CRO
44
84
C3
RW
C4
CS
46
86
C6
47
87
C7
48
88
C8
49
89
C9
4A
8A
CA
46
86
CS
4C
8C
CC
4D
8D
CD
4E
SE
CE
4F
SF
10
50
90
001_C_IN
11
SI
91
CDL
12
52
92
COIOCU
02
13
53
93
CDI_E_OU
03
14
54
94
04
iS
55
9S
05
16
56
96
06
17
57
97
18
58
98
MUX_CRO
08
19
S9
99
MUX_CR1
09
1A
SA
9A
MUX_CR2
DA
lB
SB
96
MUX_CR3
06
IC
SC
9C
10
SD
90
OSC_GO_EN
00
1E
SE
9E
OSC_CR4
DE
9F
CSC_CR3
OF
AO
OSC_CRO
EO
Al
OCC_CRI
El
A2
OSC
E2
A3
VLT_CR
E3
A4
VLT_CMP
E4
AS
ADCO_TR
ES
A6
ADCI_TR
E6
PNIIUU
OE
PRT3IC1
OF
iF
D6600FN
20
DBBOOIN
21
DBB000U
22
SF
RW
RW
RW
23
DBBO1FN
24
OBBO1IN
25
DBBOIOU
26
28
DCBO2IN
29
DCBO2OU
2A
RW
RW
RW
2C
DCBO3IN
20
DCBO3OU
2E
60
CLK_CRI
61
ABF
62
CR0
63
CMP_GO_EN
64
AMD_CRI
66
ALTCRO
67
E1N
DO
Dl
CR2
A7
RW
RW
ES
A9
ILO_TR
E9
6A
AA
BOC_IR
EA
AS
ECO_IR
ES
66
TMP
6C
TMP_DR1
60
TMP_0R2
6E
6F
RW
RW
RW
RW
RW
AC
ED
AE
EE
AF
70
RDIORI
SO
71
RDIOSYN
61
RDIOIS
B2
ROIOLTO
63
32
ACEOOCRI
72
33
ACEOOCR2
73
RW
RW
34
74
RDIOLT1
64
35
75
RDIOROO
65
RDIOROI
66
36
ACEOI CR1
76
37
ACEOI CR2
77
RW
RW
RW
EC
AD
31
EF
RW
RW
RW
RW
RW
RW
RW
78
79
7A
BA
3B
76
F2
F3
F4
FS
F6
69
3A
Fl
68
39
FO
CPU
B7
38
66
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
3C
7C
BC
30
70
SD
DAC_CR
FD
3E
7E
BE
CPU_SCR1
FE
SF
CPU_SCRO
FF
3F
HIGHLY
RW
RW
RW
RW
RW
RW
RW
E7
IMO_TR
30
29
RW
RW
RW
RW
DC
69
DRO
RW
RW
RW
RW
07
AS
TMP_0R3
2F
RW
RW
CF
68
CLK_CR3
RW
RW
RW
RW
RW
RW
RW
RW
65
RW
RW
RW
2B
DCBO3FN
CLK_CRO
AMD_CRO
27
DCBO2FN
March
CC
DCC.1
85
00
fields are
CD
CD
45
OC
Blank
Reference
Reserved
7F
and
shoald
not
be accessed
Document
2006
CONFIDENTIAL
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ATTORNEYS
is
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FC
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specific
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CONFIDENTIAL
APCY00009772
ATTORNEYS
EYES ONLY
APE
LOOl 0837
Electrical Specifications
CYPRESS
PER
This
presents
the
DC
confirm
chapter
that
you have
specifications
Specifications
are
Refer
3-14
to
Table
valid
for
for the
and
4OoC
AC
electrical
specifications
most
data
the
TA
electrical
85C
recent
and
specifications
Tj
on
of
000C
the
as
internal
CY8C21x34
the
sheet by
to
going
PSoC device
web
except
specified
main
the
For
the
most up
to
date
electrical
http//www.cypress.com/psoc
where
IMO
oscillator
25
at
PORM
noted
using
SLIMO
mode
5.25
475
4.75
Ce
3.60
00
3.00
40
2.40
n3
12MHz
MHz
kHz
Cpu
3-la
Figure
The
following
Table
3-1
versus
Voltage
table
lists
the
of
measure
thai
are
used
in
this
IMO Frequency
Trim Options
chapter
of
Measure
Unit
Symbol
of
Measure
microwatts
decibels
mA
milli-smpere
ms
milli-second
my
farad
milli-volts
Hz
hertz
KB
1024
bytes
nA
Kbit
1024
bits
ns
nsnosecond
kHz
kilohertz
nV
nanovolts
k2
nanoampere
ohm
kilohm
MHz
megshertz
pA
picoampere
Ma
megaohm
pF
picofered
iA
microampere
pp
peak-to-peak
iF
microfsrsd
HH
parts
sps
samples
microvolts
uvrms
29
microvolte
sigma
CONFIDENTIAL
Document
ATTORNEYS
per
one
second
stnndnrd
deviation
volte
root-mean-square
2006
million
per
picosecond
pa
microsecond
iv
March
ppm
microhenry
us
HIGHLY
3-lb
Figure
Celsius
degree
femto
Cpu Frequency
units
Unit
Symbol
fF
lMOFrequeucy
Measure
Units of
dB
2451Hz
Frequency
No
38-1
2025
Rev
17
EYES ONLY
CONFIDENTIAL
APCY00009773
ATTORNEYS
EYES ONLY
APE
LOOl 0838
CY8C21x34
Data
Final
Sheet
Maximum
Absolute
3.1
Table
3-2
Electrical
Maximum
Absolute
Symbol
Ratings
Ratings
Mm
Description
TsTo
Specifications
Max
Typ
Notes
units
100
25
-55
Storage Temperature
Higher
temperaturee
storage
time
reteatioe
ature
is
25C 1-
25C
data
temper
etorage
Extended
deratioe
65C
above
temperuterea
storage
redece
will
Recemmended
will
degrade
reliability
TA
Ambient
Vdd
Supply Votage
Vie
DC
Input
Vioz
DC
Votage
lvio
Electro
LU
Latch-up
3.2
on Vdd
Relative
to
3-3
into
any
Discharge
following
and
-40C
to
Table
3-4
lists
85C
Vdd
0.5
mA
mA
Hamaa
2000
Body
maximum
guaranteed
7V
or
Specifications
chip-Level
at
3.6V
25C
and
are
minimum
and
-40C
and
for
85C
TA
design
for the
specifications
or
guidance
2.4V
to
3.OV
and
and
Voltage
-40C
TA
temperature
85C
Mm
Max
Typ
Notes
units
Seetable
5.25
24
mA
MHz
DC
titled
Conditions
MHz
IMD
MHz
SLIMO mode
mA
Vdd
uaing
kHz VC3
0.366
Vdd
Conditions
are
doubler
clock
VC2
1Dc27
Supply Current
IMO
MHz
using
SLIMO mode
1.1
1.5
mA
23.4
Conditions
MHz
VC2
1aa27
las
with
Sleep
Mode Current
and internal
alow
oscillator
and
Vssn
Mode
Sleep
internal
Reference
Current
slow
Voltage
with
oscillator
2.6
active
Sleep Timer woi
Mid temperature range
POR LVD
Sleep
limer
WD1
pA
Vdd
2.55V
0C
2.8
POR LVD
pA
Vdd
3.3V
kHz
VC1
2.55V
TA
kHz
25C CPU
TA
VCI
375
kHz
kHz
0.091
TA
CPU
375
kHz
disabled
-40C
25C
TA
0.091
kHz VC3
CPU
MHz VC2
1.5
disabled
Vdd
doubler
23.4
Specifica
25C
TA
VCI
3.3V
kHz VC3
are
clock
LVD
and
5.CV
disabled
MHz
Supply Current
1.2
MHz
POR
22
are
48
93.75
lccz
5.25v
only
2.40
IMO
to
parameters
Typical
Specifications
voltage
Supply Current
4.75V
ranges
respectively
tions on page
Icc
ESD
Model
Characteristics
Description
Supply
50
-25
Temperature
3.OVto
symbol
Vdd
Pia
Voltage
Chip-Level
3.3V
DC
0.5
0.5
Temperature
table
TA
5v
apply
Port
Electrical
DC
The
Vdd
Veu
Current
DC
33.1
0.5
200
Current
Operating
3.3
6.0
-0.5
Tn-state
Operating
Table
Vas
Vss
Applied
Static
85
-40
Applied
to
Votage
Maximum
ESD
Power
with
Temperature
40C
85C
active
Bandgap
1.28
1.30
1.32
Trimmed
for appropriate
Vdd
Vdd
3.0V
to
5.25V
March
HIGHLY
29
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
Rev
18
EYES ONLY
CONFIDENTIAL
APCY00009774
ATTORNEYS
EYES ONLY
APE
LOOl 0839
CY8C21x34
Table
Data
Final
DC
3-4
Sheet
Chip-Level
Electrical
Specifications
Symbol
continued
Mm
Description
VREF27
Reference
Bandgap
Voltage
Specifications
Max
Typ
1.16
1.30
Notes
Units
Trimmed
1.33
Vdd
for appropriate
Vdd
2.4V
to
3.OV
AGND
Ground
Analog
VREF
VREF
VREF
0.003
DC
3.3.2
The
following
and
-40C
to
Table
tables
3-5
3.3V
and
Purpose
3.OV
2.7V
to
at
3.6V
25C
10
Specifications
maximum
guaranteed
list
IA 85C
5V
apply
General
and
and
are
minimum
TA 85C
-40C
and
for
design
specifications
2.4V
or
guidance
to
for the
3.0V and
voltage
and
temperature
TA 85C
-40C
Symbol
to
5.25V
parameters
Typical
only
Description
Rpo
Puil-down
High
Mm
Units
Vdd
Level
Notes
kO
5.6
Resistor
Output
Max
Typ
5.6
Resistor
Puil-up
kO
IOH
-1.0
10
mA
on even
on odd
Low
VOL
4.75V
ranges
respectively
5V and 3.3V DC GPIO Specifications
Rpu
VoH
0.003
Output
Level
IOL
0.75
25
ViL
Input
Low
ViH
Input
High
VH
Input
Hysteresis
pins
mA
Vdd
IL
Input
Leakage
port
pins
2.1
3.0
to
to
5.25V
exampie
loads
total
P012 P114
P0 P1
5.25
tested
to
exampie
loads
total
P012 P114
P013 P115
5.25
3.0
for
5.25v
exampie
4.75
for
to
exampie
for
for
pins
Vdd
0.8
Level
port
Vdd
Level
4.75
pins
port
on even
on odd
Vdd
port
mV
60
nA
Gross
ciN
capacitive
Load
on
Pins
as
Input
3.5
10
pF
Package
and
pin
dependent
Temp
25c
COUT
capacitive
Load
on
Pins
as Output
3.5
10
pF
Package
and
pin
dependent
Temp
25C
Table
3-6
2.7V
Absoiute
DC GPIO
Mm
Description
Rpu
Puil-up
RpD
Puil-down
High
Max
lyp
5.6
Resistor
Vdd
Level
Notes
kO
kO
IOH
0.4
mA
2.5
mA maximum
get
Low
Output
Level
mA
ViL
Input
Low
ViH
Input
High
VH
Input
Input
Leakage
0.75
Hysteresis
IL
IOL
2.4
6.25 Typ Vdd
50 mA Typ combined
combined
Vdd
Vdd
0.75
2.0
2.4
to
3.OV
90
to
3.OV
16
bud
iOH
mA
maxi
IOL budget
2.4
to
3.0
Vdd
Level
Level
10
mum
VOL
LIA
Units
5.6
Resistor
Output
to
Specifications
Symbol
VOH
Value
2.4
to
3.0
tested
mV
90
nA
Gross
CiN
Capacitive
Load
on
Pins
as
Input
3.5
10
p1
Package
and
pin
dependent
Temp
25c
couT
capacitive
Load
on
Pins
as Output
3.5
10
pF
Package
and
pin
dependent
Temp
25C
March
HIGHLY
29
Absoiute
Value
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
to
LIA
Rev
EYES ONLY
CONFIDENTIAL
-ATTORNEYS EYES ONLY
19
APCY00009775
APELOO1 0840
CY8C21x34
Final
3.3.3
DC
The
following
and
-40C
to
Table
3-7
Sheet
tables
2.7V
or
3.3V
3.OV
to
5V DC Operational
Symbol
TCVosoA
Average
lEBoAa
Offset
Input
Offset
Current
Input
VCMOA
Common
G0LOA
Open
and
4O0C
are
for
minimum
85C
TA
design
Capacitance
Mode
guidance
2.4V
Mm
3-8
3.3V
DC
Analog
Analog
TCV0SCA
Average
Input
Offset
Current
Input
CIN0A
Input
VCMOA
Common
GOLOA
Open
ISCA
Mode
LIow1
rat
Supply
ic2l
3-9
2.7V
DC
Analog
Analog
TCV0SCA
Average
Input
Offset
Leakage
Current
IEBOAa
Input
CINOA
Input
VcM0A
Common
GOLOA
Open
ISOA
Capacitance
Mode
Loop
29
behavior
Rn
Voltage
Max
Iovest
Iea
dependent
Temp
25C
of2O
Units
Notes
mV
pA
4.5
Pins
Gross
pF
9.5
Package
tested
to
and
pin
iA
dependent
Temp
25C
Temp
25C
Vdd
is
below
at
25
50 nA
dB
30
Le
overterriJerature
Port
iA
Pins
1-7
for
the
loe
leage
of
2X RA
Analog
Pins
200
pA
4.5
Pins
Gross
pF
9.5
Package
tested
and
to
pin
dependent
Vdd
Range
80
dB
30
10
Fn
Notes
V/oC
10
Analog
Units
mV
15
2.5
Drift
Port
Max
Typ
lVlin
value
Gain
Port
pin
Amplifier Specifications
Voltage
Port
lof
is
belowl
rat
50
riAoverterrperature
Document
2006
CONFIDENTIAL
fortl
200
Pins
AmplifierSupplyCurrent
Ail
1-7
15
10
absolute
Voltage
to
and
10
Drift
Operational
Offset
Pins
80
Port
tested
iA
Typ
2.5
Decriptian
Input
Port
Range
Symbol
VosoA
Le
Mm
Current
Ijof
behavior
Package
dB
30
50 rtAovertenrature
Gain
Loop
Amplifier
Gross
pF
9.5
Vdd
value
Port
Voltage
5.25V
Amplifier Specifications
Voltage
Pod
Capacitance
to
parameters
Notes
Units
pA
4.5
Pins
0.0
is
absolute
Leakage
IEBOAa
4.75V
Typical
V/oC
10
Port
Voltage
ranges
respectively
mV
80
Operational
Offset
temperature
85C
TA
Max
15
200
Pins
Description
Input
and
voltage
-40C
10
Drift
Range
Symbol
VOSOA
and
Typ
2.5
value
Port
Port
Ijof
Lehavior
ypicI
3.OV
only
Gain
Loop
to
Amplifier Specifications
Voltage
Voltage
for the
specifications
or
AmplifierSupplyCurrent
ISOA
HIGHLY
and
absolute
Voltage
Leakage
Input
CINOA
March
and
Description
Input
Table
maximum
3.6V
25C
at
Specifications
Amplifier Specifications
guaranteed
list
85C
VOSOA
Table
Electrical
Operational
IA
5V
apply
Data
ATTORNEYS
No
38-1
Le
2025
Port
Pins
1-7
forthe
love leage
ofax rk
Rev
EYES ONLY
CONFIDENTIAL
-ATTORNEYS EYES ONLY
20
APCY00009776
APELOO1 0841
CY8C21x34
Final
3.3.4
DC
The
following
and
-40C
5V
apply
to
Table
3-10
Data
Sheet
table
lists
85c
3.3V
DC
Mode Pump
Switch
TA
3.6V
to
25C
at
and
Symbol
are
for
SMP
Mode Pump
Switch
and
-40C
and
minimum
TA
design
85c
sv
from
Output votage
for the
specifications
or
guidance
2.4V
to
3.OV
and
and
voltage
-40C
TA
temperature
85C
3.3v Oetpet
Mm
Pump
from
voltage
Max
Typ
50
4.75
Notes
Units
5.25
Pump
3.00
3.25
2.6v Output
from
voltage
245
Pump
2.55
3.50
Available
Output
2.80
Input
footnote
of
aet
to
SMP
trip
votage
ia
act
to
3.25v
mA
SMP
votage
is
trip
set
to
3.25v
2.55
mA
SMP
trip
votage
is
set
to
2.55V
from
Range
from
Range
Voltage
1.8
Battery
5.0
1.0
Battery
from
Range
voltage
3.3
1.0
Battery
to
2.8
to
npat
from
voltage
Battery
to Start
Pump
1.2
SMP
trip
voltage
is
of
footeote
SMP
voltage
is
trip
of
footnote
SMP
trip
voltage
is
of
footnote
0C
3.25v
Configuration
to
footnote
SOy
Configuration
set
Minimum
of
Configuration
set
Input
neglecting
2.55v
soy
vpUMp
voltage
Inpat
neglecting
3.25V
footeote
of
Configuration
to
Average
ia
voltage
trip
nuglucting
SOy
Average
aet
is
mA
set
vsAysTAsT
voltage
to
5.0
ISV
V5AT
VsAy2v
SMP
footnote
of
trip
configuration
current
.8v VpuMp
vaAT
vsAT3v
SMP
Avurugu
set
is
voltage
trip
.3V VPuMF
v5AT
vsAysv
SMP
configuration
ripple
lPuMP
of footnotu.a
configuration
ripple
VpuMp2v
5.25V
to
parameters
Typical
only
ripple
vpuMp3v
4.75V
ranges
respectively
Specifications
Description
vpuMp5v
Specifications
Specifications
maximum
guaranteed
3.OV
2.7V
or
Electrical
2.55v
Configuration
TA
100
1.25vatTA-405C
AvpuMp
Line
Line
over
Regulation
vi
%vc
range
PUMP Trip
the
DC POR
for
in
on
12
Load
AVPUMPLsd
%Vo
Regalation
page
AVPUMPRFppIa
Output
La
voltage
Ripple
depends
on cap/load
100
35
Efficiency
mVpp
50
E2
35
Efficiency
votage
For
10
V0
footnote
and
LVD
by
value
vdd
the
VMI20
setting
Table
is
the
theVdd
VMI20
3-
value
setting
Table
Specification
footnote
of footnote
is
load
aH
is
the
Specification
specified
of
Configuration
80
LvD
by
3-
page22
Configuration
trip
and
of
PUMP Trip
DC POR
the
for
l2on
vo
specified
22
Configuration
in
footnote
of
Configuration
inductor
set
mA
to
is
mA
Load
is5
mA
SMP
3.25V
VpUMp
uF
Load
capacitor
.55V
and
V5Ar
.3V
Schottky
diode
Fpuep
Switching
Frequency
DCpuep
Switching
Daty
Li
IIH
irÆctor
Ci
50
Cycle
10 iF
MHz
1.3
cadtor
Di
diode See
Schottky
flgure
3-2
Dl
PUMP
Figure
3-2
March
29
HIGHLY
Basic
Switch
Mode
Pump
Circuit
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
Rev
21
EYES ONLY
CONFIDENTIAL
APCY00009777
ATTORNEYS
EYES ONLY
APE
LOOl 0842
CY8C21x34
Final
3.3.5
DC
The
following
and
-40C
to
Table
Sheet
table
lists
3-11
DC Analog
at
to
maximum
3.6V
25C
and
are
minimum
and
400C
and
for
85C
TA
design
guidance
2.4V
to
3.OV
and
voltage
-40C
and
Resistance
Common
to
Mm
Max
Typ
Bus
Analog
of
The
following
and
-40C
5V
apply
to
Table
table
3-12
3.3V
3.0V
2.7V
or
at
to
to
Vdd
DC POR and LVD
and
and
VppoRo
for
PPOR
PORLEV
VppoR2
for
guidance
are
VM
VM
VM
VM
VM
VM
VM
VM
VLVDO
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd
VpuMpl
VpuMp2
VpuMp3
VpuMp4
VpuMp5
VpuMp6
VpuMp7
ys
ys
2.4V
to
3.OV
and
2.7V
voltage
and
temperature
85C
-40C
ranges
respectively
4.75V
Typical
to
5.25V
parameters
only
Specifications
Mm
Max
lyp
Notes
Units
Vdd
Trip
2.36
2.40
01b
for
2.82
during
4.55
must
be
greater
startup
reset
than
from
or equal
the
XRES
to
2.5V
pin
or
from Watchdog
2.95
4.70
LVD
Trip
000b
2.40
2.45
2.51a
OOlb
2.85
2.92
2.9gb
OlOb
2.95
3.02
3.09
OlIb
3.06
3.13
3.20
lOOb
4.37
4.48
4.55
lOib
4.50
4.64
4.75
IlOb
4.62
4.73
4.83
IlIb
4.71
4.81
495
000b
2.45
2.55
2.62C
OOlb
2.96
3.02
3.09
OlOb
3.03
3.10
3.16
Olib
3.18
3.25
3.32d
lOOb
4.54
4.64
4.74
lOib
4.62
4.73
4.83
liOb
4.71
4.82
4.92
ilib
4.89
5.00
5.12
Value
VM
VM
VM
VM
VM
VM
VM
VM
VpuMpo
for
tn
tn
PUMP
Trip
PRLEV
5J
mVaLve
Vpjra
FL
mVaLove
Vpa PCRLEV
PJysgreatertn
53
mVIxve
FL
mVaLove
ipy
sJy
VLVDO
ysgreatertn
HIGHLY
design
or
lOb
Value
2.7V
2.4VVdd
reset
PORLEV
Vdd
5.25V
Notes
Vdd
c2
for the
specifications
85C
00b
PORLEV
PPOR1
March
minimum
and
-40C
Description
Value
to
parameters
800
maximum
3.6V
25C
Symbol
Vdd
4.75V
Typical
and LVD Specifications
guaranteed
lists
85C
TA
Switch
Initialization
DC POR
3.3.6
ranges
respectively
Units
400
800
Resistance
RVDD
temperature
85C
TA
only
Description
Switch
for the
specifications
or
Mux Bus Specifications
Symbol
Rsw
Specifications
Bus Specifications
guaranteed
3.OV
2.7V
or
3.3V
Electrical
Mux
Analog
85C
5V
apply
Data
VLVD3
29
greater
greater
fallirij
for
faIlirj
Document
2006
CONFIDENTIAL
for
01
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
-ATTORNEYS EYES ONLY
22
APCY00009778
APELOO1 0843
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