VIA Technologies, Inc. (a California corporation) et al v. ASUS Computer International et al

Filing 176

ORDER CONSTRUING CLAIMS IN U.S. PATENT NO. 7,313,187. Signed by Judge Beth Labson Freeman on 8/19/2016. (blflc3S, COURT STAFF) (Filed on 8/19/2016)

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UNITED STATES DISTRICT COURT

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NORTHERN DISTRICT OF CALIFORNIA

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SAN JOSE DIVISION

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VIA TECHNOLOGIES, INC. (A
CALIFORNIA CORPORATION), et al.,
Plaintiffs,

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ORDER CONSTRUING CLAIMS IN
U.S. PATENT NO. 7,313,187

v.

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Case No. 14-cv-03586-BLF

ASUS COMPUTER INTERNATIONAL, et
al.,

[Re: ECF 116]

Defendants.
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United States District Court
Northern District of California

Plaintiffs VIA Technologies, Inc., a California corporation, VIA Technologies, Inc., a
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Taiwan corporation, and VIA Labs, Inc., (collectively, “Via”) bring this action alleging patent

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infringement and trade secret misappropriation against Defendants ASUS Computer International,
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ASUSTeK Computer Inc., and ASMedia Technology Inc. (“ASM”) (collectively, “Asus”). The
patent portion of the lawsuit alleges Asus infringes Via’s U.S. Patent No. 7,313,187 (the “’187
Patent”). The Court held a tutorial on June 3, 2016, and a Markman hearing on June 10, 2016, for
the purpose of construing five disputed terms in the ’187 Patent.

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I.

BACKGROUND ON THE ’187 PATENT
The ’187 Patent is titled “High Speed Serial Linking Device with De-Emphasis Function

and the Method Thereof.” As computers require higher and higher rates of data transmission, it
becomes more difficult to transmit data while minimizing signal loss on a circuit board. ’187
Patent at 1:20-24, 27-30. The ’187 Patent describes and claims solutions to improve signal
integrity in a high-speed circuit environment. ’187 Patent at 1:60-2:35. It accomplishes this by
taking a stream of data bits (a string of “0’s” and “1’s”) and using a technique known as “deemphasis.” ’187 Patent at 1:29-31, 1:32-47. In a computers, the data bits of “0’s” and “1’s” are
represented through voltages with a “1” being transmitted using a positive voltage and a “0” being
transmitted using a negative voltage. ’187 Patent at 1:10-2:35. With de-emphasis, the magnitude

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between the signal voltages is increased for the first “1” or “0” in each string of “1’s” or “0’s”,

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while decreased (or de-emphasized) for the remainder of the 1’s or 0’s in the string. ’187 Patent at

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1:32-47. De-emphasis makes it easier to reduce signal loss and increase signal quality at high

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speeds. ’187 Patent at 1:60-2:35.

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A.

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The parties disagree over the specific claim terms that must be construed. In its Patent

Claim Terms at Issue

L.R. 4-1 disclosures, ASUS identified “to serialize the parallel data into a serial data and a delayed

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serial data” as a proposed phrase for construction. Exh. 17 to Reply 3, ECF 133-4. At claims

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construction, ASUS seeks not only construction of that phrase but also the following terms found

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within this phrase: “parallel data,” and “serial data.” Opp. 14, ECF 126. VIA argues that ASUS

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United States District Court
Northern District of California

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waived construction of “parallel data” and “serial data” by not including these terms in their Patent

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L.R. 4-1 disclosures. Reply 5, ECF 133.

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The Court agrees with VIA and finds ASUS did not properly disclose “parallel data” and

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“serial data” in its Patent L.R. 4-1 disclosures. Rule 4-1(a) requires parties to serve on each other

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a list of claim terms that should be construed by the Court. Parties may not attempt an end run

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around this rule by disclosing a large phrase and then seeking to construe specific terms within

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that phrase. Holding otherwise would allow parties to hide the ball and render the claim

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construction process meaningless. Accordingly, the Court will not construe “parallel data” and

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“serial data” because ASUS did not comply with the patent local rules.

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B.

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VIA objects to Dr. Nelson’s deposition testimony at 208:14-16, 208:17-212:11, 212:12-

Evidentiary Objections

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214:05 because opposing counsel “coached Dr. Nelson during his deposition, provided him with

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incomplete documents that omitted information contrary to their positions, and had him provide

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new opinions despite his earlier sworn testimony that all his opinions had already been disclosed.”

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Reply 13, ECF 133. As an initial matter, ASUS cites to Exhibit 3 to its brief as containing Dr.

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Nelson’s deposition testimony at 208:14-16, 208:17-212:11, 212:12-214:05. Opp. 11, ECF 126.

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However, Exhibit 3 does not contain these excerpts of Dr. Nelson’s deposition. Bhakar Decl. ¶ 4,

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ECF 126-1 (“Attached hereto as Exhibit 3 are true and correct copies of excerpts from the January
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8, 2016 Deposition of Dr. Brent E. Nelson including 61:02-68:09, 156:20-160:24.”). In any event,

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VIA attached the relevant portions of Dr. Nelson’s deposition at Exhibit 16 to its reply. ECF 133-

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3. The Court has reviewed Exhibit 16 and does not find Dr. Nelson was improperly coached,

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provided with incomplete documents, or otherwise violated the rules of evidence requiring

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excerpts of his testimony to be stricken. His transcript reveals nothing more than the ordinary

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interaction between parties engaged in a deposition. Accordingly, the Court OVERRULES

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VIA’s objections.
ASUS objects to Mr. Gomez’s opinions at paragraphs 31, 80-87, 89-93, 95-98, 102-106,

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108 of his report as being conclusory. Opp. 25, ECF 126. ASUS argues that at his deposition,

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Mr. Gomez would not point to any specific intrinsic or extrinsic evidence that he relied upon in

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Northern District of California

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forming his opinions and instead stated he was relying on his “background as having 30 years of

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experience in the industry.” Id. VIA responds that Mr. Gomez’s testimony as a person of

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ordinary skill is relevant to the terms and that he also explained he reviewed the ’187 Patent, its

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file history, references cited in the prosecution history, and other documents. Reply 11, ECF 133.

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The Court agrees with VIA and finds that Mr. Gomez adequately supported his opinions on claims

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construction through his experience and reliance on relevant documents. ASUS’s reliance on

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GPNE Corp. v. Apple, Inc., 2014 U.S. Dist. LEXIS 53234 (N.D. Cal. Apr. 16, 2014), is misplaced

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because GPNE excluded the testimony of a reasonable royalty expert who only relied upon his 30

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years of experience, instead of a reliable and testable methodology. Id. at *18-19. In contrast, at

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claims construction, the perspective of a skilled artisan is relevant to construing terms.

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Accordingly, the Court OVERRULES ASUS’s objections.1

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II.

LEGAL STANDARD

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A.

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Claim construction is a matter of law. Markman v. Westview Instruments, Inc., 517 U.S.

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370, 387 (1996). “It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the

General Principles

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ASUS also notes that a motion to strike Mr. Gomez’s testimony was pending when it filed its
brief. Opp. 25, ECF 126. That motion was subsequently granted in part, with the Court denying
ASUS’s motion to strike Mr. Gomez’s testimony but allowing ASUS to conduct an additional
deposition of him. ECF 158.
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invention to which the patentee is entitled the right to exclude,” Phillips v. AWH Corp., 415 F.3d

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1303, 1312 (Fed. Cir. 2005) (en banc) (internal citation omitted), and, as such, “[t]he appropriate

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starting point . . . is always with the language of the asserted claim itself,” Comark Commc’ns, Inc.

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v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998).

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Claim terms “are generally given their ordinary and customary meaning,” defined as “the

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meaning . . . the term would have to a person of ordinary skill in the art in question . . . as of the

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effective filing date of the patent application.” Phillips, 415 F.3d at 1313 (internal citation

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omitted). The court reads claims in light of the specification, which is “the single best guide to the

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meaning of a disputed term.” Id. at 1315; see also Lighting Ballast Control LLC v. Philips Elecs.
N. Am. Corp., 744 F.3d 1272, 1284-85 (Fed. Cir. 2014) (en banc). Furthermore, “the

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Northern District of California

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interpretation to be given a term can only be determined and confirmed with a full understanding

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of what the inventors actually invented and intended to envelop with the claim.” Phillips, 415

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F.3d at 1316 (quoting Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243, 1250 (Fed.

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Cir. 1998)). The words of the claims must therefore be understood as the inventor used them, as

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such understanding is revealed by the patent and prosecution history. Id. The claim language,

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written description, and patent prosecution history thus form the intrinsic record that is most

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significant when determining the proper meaning of a disputed claim limitation. Id. at 1315-17;

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see also Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).

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Evidence external to the patent is less significant than the intrinsic record, but the court

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may also consider such extrinsic evidence as expert and inventor testimony, dictionaries, and

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learned treatises “if the court deems it helpful in determining ‘the true meaning of language used

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in the patent claims.’” Philips, 415 F.3d at 1318 (quoting Markman, 52 F.3d at 980). However,

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extrinsic evidence may not be used to contradict or change the meaning of claims “in derogation

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of the ‘indisputable public records consisting of the claims, the specification and the prosecution

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history,’ thereby undermining the public notice function of patents.” Id. at 1319 (quoting

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Southwall Techs., Inc. v. Cardinal IG Co., 54 F.3d 1570, 1578 (Fed. Cir. 1995)).

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B.

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Paragraph 6 of 35 USC § 112 provides for means-plus-function claiming: “An element in a

Means-Plus-Function Claims

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claim for a combination may be expressed as a means . . . for performing a specified function . . .

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and such claim shall be construed to cover the corresponding structure, material, or acts described

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in the specification and equivalents thereof.” When a claim uses the term “means” to describe a

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limitation, it creates a presumption that the inventor used the term to invoke § 112 ¶ 6. Biomedino

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v. Waters Technologies, 490 F.3d 946, 950 (Fed. Cir. 2007). The “presumption can be rebutted

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when the claim, in addition to the functional language, recites structure sufficient to perform the

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claimed function in its entirety.” Id.

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If a court concludes that a claim limitation is a means-plus-function limitation, “two steps

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of claim construction remain: 1) the court must first identify the function of the limitation; and 2)
the court must then look to the specification and identify the corresponding structure for that

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function.” Id. The claim limitation will then be construed to cover that corresponding structure and

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equivalents thereof. 35 USC § 112 ¶ 6.

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III.

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CONSTRUCTION OF DISPUTED TERMS
A.

“a parallel-to-serial unit which receives a parallel data to serialize the parallel
data into a serial data and a delayed serial data”

Via’s Proposal
Plain and ordinary meaning
Alternative: “a module that
receives a parallel data to
convert the parallel data into a
serial data and a delayed
data.”

Asus’s Proposal
This phrase should be
construed as a means plus
function limitation governed
by 35 U.S.C. § 112 paragraph
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function: “(which) receives a
parallel data to serialize the
parallel data into a serial data
and a delayed serial data”

Court’s Construction
function: “(which) receives a
parallel data to serialize the
parallel data into a serial data
and a delayed serial data”
corresponding structure:
serializers 212, 214 and
register 216 of FIG. 3A

corresponding structure:
serializers 212, 214 and
register 216 of FIG. 3A
Via argues that no construction is necessary because a skilled artisan would readily

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understand the phrase “a parallel-to-serial unit which receives a parallel data to serialize the

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parallel data into a serial data and a delayed serial data.” Mot. 5, ECF 116. Asus argues that this

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phrase should be construed as a means-plus-function limitation because it does not recite any
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definite structure but rather recites functions. Opp. 6, ECF 126.
The Court agrees with Asus and finds that this term is in means-plus-function format.
First, the Court recognizes that the term “a parallel-to-serial unit which receives a parallel data to

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serialize the parallel data into a serial data and a delayed serial data” does not include the word

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“means,” and thus, there is a rebuttable presumption that the term is not subject to § 112(6).

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Therefore, the Court must analyze whether the term fails to “recite sufficiently definite structure”

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or recites “function without reciting sufficient structure for performing that function.” Williamson

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v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (partially en banc). Here, the term

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recites function without reciting a sufficient structure for performing that function. The word

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“unit” is a generic descriptor and does not describe a sufficiently definite structure. See, e.g.

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Williamson, 792 F.3d at 1350-51. Attaching the pre-fix “parallel-to-serial” also does not impart

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structure on the term “parallel-to-serial unit.” Id. at 1351 (“The prefix ‘distributed learning

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control’ does not impart structure into the term ‘module.’ These words do not describe a

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sufficiently definite structure.”). The ’187 Patent also depicts the “parallel-to-serial unit” as black

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boxes that do not connote any specific structure, ’187 Patent at Fig. 2 boxes 210, 230, 250, unlike

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other components which are described using specialized shapes, ’187 Patent at Fig. 2 boxes 212

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and 214 (serializer) and 216 (register). Thus, the patent does not connote any specific structure to

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the “parallel-to-serial unit.”

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Via’s arguments in opposition are not persuasive because their arguments revolve around

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describing the structure in terms of function. See, e.g., Gomez Report (Exhibit 16) to Mot. ¶ 83,

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ECF 116-16 (A person of ordinary skill in the art would understand that the “a parallel-to-serial

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unit which receives a parallel data to serialize the parallel data into a serial data and a delayed

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serial data….”). As a result the term “parallel-to-serial unit” does not connote anything about its

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structure and the Court finds that the term “parallel-to-serial unit” would not be understood by a

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skilled artisan as having sufficient structure for performing the recited functions of “receiv[ing] a

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parallel data to serialize the parallel data into a serial data and a delayed serial data.”

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Under § 112(6), the Court must determine the claimed functions and then determine the
corresponding structure that performs those functions. See Med. Instrumentation & Diagnostics
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Corp. v. Elekta AB, 344 F.3d 1205, 1210 (Fed. Cir. 2003). Asus’s proposed function of “receives

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a parallel data to serialize the parallel data into a serial data and a delayed serial data” is supported

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by the claim language and accurately describes the function of the “parallel-to-serial unit.”

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Accordingly, the Court construes the term’s function as “receives a parallel data to serialize the

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parallel data into a serial data and a delayed serial data.”

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As to structure, Asus argues that Fig. 3A and corresponding text at 3:13-25 of the ’187

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Patent describe the structure necessary to carry out the functions of the “parallel-to-serial unit.”

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The specification indicates that the two serializers in Fig. 3A (box 212 and 214) receive parallel

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data. ’187 Patent at 3:15-17 (“Serializer 212 receives parallel data….”). These two serializers and
the register at box 216 carry out the second function “to serialize the parallel data into serial data

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and delayed data.”). ’187 Patent at 3:15-22 (“Serializer 212 receives parallel data, [D0, D1,...D9],

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serializes the parallel data and outputs serial data DT. Register 216 is used to store the last bit D9

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in the parallel data and output it after one serial bit time.”). As a result, based on the

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specification, serializers 212, 214, and register 216 are the corresponding structures for this

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means-plus-function term.

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B.

“to serialize the/serializing the parallel data into a serial data and a delayed
serial data”

Via’s Proposal
Plain and ordinary meaning.
Alternative: “converting a
parallel data into a serial data
and a delayed serial data”

Asus’s Proposal
“the act of converting two or
more lines of parallel data into
a single-wire serial data signal
where the individual bit values
on the wires of the parallel
data are output serially (one
after another) on a single
wire”

Court’s Construction
“the act of converting two or
more streams of parallel data
into a single stream serial data
where the individual bit values
of the parallel data are output
serially (one after another)”

The disputed term “to serialize the/serializing a parallel data into a serial data and a
delayed serial data” appears in independent claims 1 and 13 of the ’187 Patent. Claim 1 is
representative of how the term is used in the claim language:
1. A high-speed serial linking device with de-emphasis function, comprising:
a parallel-to-serial unit which receives a parallel data to serialize the parallel data
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into a serial data and a delayed serial data, wherein the delayed serial data is one
serial bit time lag behind the serial data;

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a pre-driver which receives the serial data and the delayed serial data to output a data
differential pair according to the serial data and output a delayed-and-inverted
differential pair according to the delayed serial data, wherein the delayed-and-inverted
differential pair is the inverse of and one serial bit time lag behind the data differential
pair; and

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an output driver unit which receives the data differential pair and the delayed-andinverted differential pair to output a de-emphasized transmission differential pair.

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Northern District of California

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’187 Patent at 5:51-67 (emphasis added).
At the Markman hearing, both parties agreed that “to serialize the/serializing the parallel
data into a serial data and a delayed serial data” should be construed as “the act of converting two
or more streams of parallel data into a single stream serial data where the individual bit values of
the parallel data are output serially (one after another).” Accordingly, the Court adopts this
construction.
C.

“one serial bit time lag”

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Via’s Proposal
Plain and ordinary meaning

Asus’s Proposal
“the amount of time required
to transmit one serial bit”

Court’s Construction
“delayed by the duration of
one serial bit”

Alternative: “delayed by a
single serial bit”
The disputed term “one serial bit time lag” appears in independent claims 1 and 13 of the
’187 Patent. Claim 1 is representative of how the term is used in the claim language:

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1. A high-speed serial linking device with de-emphasis function, comprising:
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a parallel-to-serial unit which receives a parallel data to serialize the parallel data into a
serial data and a delayed serial data, wherein the delayed serial data is one serial bit
time lag behind the serial data;
a pre-driver which receives the serial data and the delayed serial data to output a data
differential pair according to the serial data and output a delayed-and-inverted
differential pair according to the delayed serial data, wherein the delayed-and-inverted
differential pair is the inverse of and one serial bit time lag behind the data differential
pair; and
an output driver unit which receives the data differential pair and the delayed-andinverted differential pair to output a de-emphasized transmission differential pair.
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’187 Patent at 5:51-67 (emphasis added).

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At the Markman hearing, both parties agreed that “one serial bit time lag” should be

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construed as “delayed by the duration of one serial bit.” Accordingly, the Court adopts this

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construction.

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D.

“differential pair”

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Via’s Proposal
Plain and ordinary meaning

Asus’s Proposal
“a signal conveyed using two
wires where the data value of
Alternative: “a pair of
the signal is represented by a
complementary signals used to voltage on one of the two
transmit information”
wires and the inverse of that
voltage on the other wire”

Court’s Construction
“a pair of complementary
signals used to transmit
information”

United States District Court
Northern District of California

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The disputed term “differential pair” appears in independent claims 1 and 13 and

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dependent claims 3, 6, 7, 10, 14, and 18 of the ’187 Patent. Claim 1 is representative of how the

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term is used in the claim language:

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1. A high-speed serial linking device with de-emphasis function, comprising:

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a parallel-to-serial unit which receives a parallel data to serialize the parallel data into a
serial data and a delayed serial data, wherein the delayed serial data is one serial bit
time lag behind the serial data;
a pre-driver which receives the serial data and the delayed serial data to output a data
differential pair according to the serial data and output a delayed-and-inverted
differential pair according to the delayed serial data, wherein the delayed-andinverted differential pair is the inverse of and one serial bit time lag behind the data
differential pair; and
an output driver unit which receives the data differential pair and the delayed-andinverted differential pair to output a de-emphasized transmission differential pair.
’187 Patent at 5:51-67 (emphasis added).
At the Markman hearing, both parties agreed that “differential pair” should be construed as
a “pair of complementary signals used to transmit information.” Accordingly, the Court adopts
this construction.

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E.

“[data] differentiator”

Via’s Proposal
“module that outputs a data
differential pair”

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Asus’s Proposal
“an AND and NOR gate
circuit combination that is
controlled by a pair of control
signals to convert a single
wire serial signal into a
differential pair signal”

Court’s Construction
“circuit that outputs a data
differential pair”

The disputed term “[data] differentiator” appears in dependent claim 3 of the ’187 Patent.
Claim 3 states:
1. The high-speed serial linking device according to claim 1, wherein the pre-driver
comprises:

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Northern District of California

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a data differentiator which receives the serial data and accordingly outputs the data
differential pair; and;
an inverse data differentiator which receives the delayed serial data and outputs the
delayed-and-inverted differential pair.
’187 Patent at 6:11-17 (emphasis added).
VIA argues that “data differentiator” should be construed as a “module that outputs a data

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differential pair.” Mot. 16, ECF 116. According to VIA, the specification describes a data

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differentiator broadly as something that receives serial data and outputs a data differential pair. Id.

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(citing ’187 Patent at 3:39-44, 6:13-14). At the Markman hearing, VIA modified its proposal to a

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“circuit that outputs a differential pair.”
Asus counters that the ’187 Patent uses “differentiator” in a manner inconsistent with its

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ordinary meaning and therefore, the patentee has acted as his own lexicographer. Opp. 21-22,

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ECF 126. As a result, Asus argues that the term must be construed according to the special

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meaning given to “differentiator” in the patent. Id. Since the ’187 Patent does not include an

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express definition for “differentiator,” Asus relies upon Figure 4 of the ’187 Patent to reach its
proposed construction that the differentiator have “AND and NOR gate circuit combination that is

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controlled by a pair of control signals to convert a single wire serial signal into a differential pair

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signal.” Id. at 22-23.

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The Court agrees with VIA and finds that “[data] differentiator” should be construed as a
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“circuit that outputs a data differential pair.” The specification describes a data differentiator as a

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circuit that receives serial data, and outputs a data differential pair. ’187 Patent at 3:39-40 (“Data

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differentiator 232 receives serial data DT, and thereby outputs a data differential pair, DP and

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DN.”).

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The Court does not agree with Asus’s position that the patentee acted as his own

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lexicographer with respect to “differentiator.” As the Federal Circuit recently reiterated “[t]he

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standards for finding lexicography and disavowal are exacting. To act as a lexicographer, a

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patentee must clearly set forth a definition of the disputed claim term and clearly express an intent

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to redefine the term.” Luminara Worldwide, LLC v. Liown Elects Co. Ltd., 814 F.3d 1343, 1353
(Fed. Cir. 2016) (internal quotations and citations omitted). Here, the ’187 Patent does not express

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Northern District of California

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a clear intent to redefine “differentiator.” Asus even concedes in its briefing that the ’187 Patent

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does not expressly define “differentiator.” Opp. 22, ECF 126 (“The ’187 patent does not include

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an express definition for what it refers as a ‘differentiator.’”).

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Asus relies upon Int’l Rectifier Corp. v. IXYS Corp., 361 F.3d 1363 (Fed. Cir. 2004) to

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argue that the patentee acted as his own lexicographer with respect to “differentiator.”

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“differentiator.” However, Int’l Rectifier was decided under the Federal Circuit’s then-existing

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approach to claim construction outlined in Texas Digital Sys., Inc. v. Telegenix, Inc., 308 F.3d

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1193 (Fed. Cir. 2002). In Int’l Rectifier, the claim construction began with an examination of the

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dictionary. That approach to claim construction was superseded by the Federal Circtui’s Phillips’s

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decision. Phillips, 145 F.3d at 1320 (Texas Digital “placed too much reliance on extrinsic sources

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such as dictionaries, treatises, and encyclopedias and too little on intrinsic sources, in particular

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the specification and prosecution history.”).

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Since VIA did not act as its own lexicographer, ASUS’s proposed construction improperly

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imports limitations from examples or embodiments in the ’187 Patent. Although the claims are

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read “in view of the specification, of which they are a part, [the Court does] not read limitations

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from the embodiments in the specification into the claims.” See Hil-Rom Servs., Inc. v. Stryker

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Corp., 755 F.3d 1367, 1372 (Fed. Cir. 2014). The specification expressly states that Figure 4,

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from which Asus draws its proposed construction, is a “description of the preferred but non11

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limiting embodiment[].” ’187 Patent at 2:30-35 (emphasis added). Accordingly, the Court

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construes “[data] differentiator” as a “circuit that outputs a data differential pair.”

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IV.

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As set forth above, the Court construes the disputed terms as follows:
Claim Term
Court’s Construction
“a parallel-to-serial unit which receives a
function: “(which) receives a parallel data to
parallel data to serialize the parallel data into a serialize the parallel data into a serial data and
serial data and a delayed serial data”
a delayed serial data”

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ORDER

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“to serialize the/serializing a parallel data into
a serial data and a delayed serial data”

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Northern District of California

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“one serial bit time lag”
“differential pair”
“[data] differentiator”

corresponding structure: serializers 212, 214
and register 216 of FIG. 3A
“the act of converting two or more streams of
parallel data into a single stream serial data
where the individual bit values of the parallel
data are output serially (one after another)”
“delayed by the duration of one serial bit”
“a pair of complementary signals used to
transmit information”
“circuit that outputs a data differential pair”

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The Court also adopts the following constructions that the parties agreed to in their joint

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claim construction and prehearing statement.
U.S. Patent No. 7,313,187
Claim Term
Court’s Construction
“positive…differential signal”
“the complement of the negative signal of the
differential pair”
“negative…differential signal”
“the complement of the positive signal of the
differential pair”

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U.S. Patent No. 8,476,747
Claim Term
Court’s Construction
“lead(s)”
Plain and ordinary meaning
“leadframe”
Plain and ordinary meaning
“pair of differential signal leads”
Plain and ordinary meaning
IT IS SO ORDERED.
Dated: August 19, 2016
______________________________________
BETH LABSON FREEMAN
United States District Judge

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