VLSI Technology LLC v. Intel Corporation

Filing 241

ORDER CONSTRUING CLAIMS IN U.S. PATENT NOS. 7,675,806; 7,709,303; 8,004,922; 8,020,014; 8,268,672; 8,566,836. Signed by Judge Beth Labson Freeman on 2/15/2019. (blflc3S, COURT STAFF) (Filed on 2/15/2019)

1
2
3

UNITED STATES DISTRICT COURT

4

NORTHERN DISTRICT OF CALIFORNIA

5

SAN JOSE DIVISION

6
7

VLSI TECHNOLOGY LLC,
Plaintiff,

8
v.

9
10

INTEL CORPORATION,

11

United States District Court
Northern District of California

Case No. 17-cv-05671-BLF

Defendant.

ORDER CONSTRUING CLAIMS IN
U.S. PATENT NOS. 7,675,806; 7,709,303;
8,004,922; 8,020,014; 8,268,672; 8,566,836
[Re: ECF 143, 158, 179]

12
Plaintiff VLSI Technology LLC (“VLSI”) brings this patent infringement lawsuit against

13
14

Defendant Intel Corporation (“Intel”), alleging infringement of eight patents, including six that are

15

at issue in the present claim construction dispute: U.S. Patent Nos. 7,675,806 (“the ’806 Patent”);

16

7,709,303 (“the ’303 Patent”); 8,004,922 (“the ’922 Patent”); 8,020,014 (“the ’014 Patent”);

17

8,268,672 (“the ’672 Patent”); and 8,566,836 (“the ’836 Patent”). The Court held a tutorial on

18

December 13, 2018 and a Markman hearing on December 14, 2018 (“the Hearing”) for the

19

purpose of construing ten disputed terms in the above listed patents.

20
21

I.

BACKGROUND
The Asserted Patents are directed to semiconductor and microprocessor technology. VLSI

22

asserts that Intel’s products infringe the Asserted Patents. See generally Compl., ECF 1. Each of

23

the six patents at issue in the present claim construction dispute is summarized below.
The ’806 Patent

24

A.

25

The ’806 Patent is titled “Low Voltage Memory Device and Method Thereof” and was

26

issued on March 9, 2010. Ex. 1 to Proctor Decl. (“’806 Patent”), ECF 144-1. This patent claims

27

devices and methods for reducing power consumption in a memory system used to store data. See

28

id. at 1:54–2:3; 9:16–12:8. The invention aims to reduce power consumption by employing a

1

high-voltage mode for storing data to a first memory and a low-voltage mode for accessing a

2

second memory. See id. at 1:54–2:3. In high-voltage mode data may be stored to the first

3

memory (a high-density memory). Id. at 1:58–60. In low-voltage mode the first memory may be

4

in a data retention or sleep state and the second memory (a low-voltage memory) is capable of

5

being accessed. Id. at 1:60–66. The invention can thus store data to high-density memory in high-

6

voltage mode and access low-voltage memory in low-voltage mode. Id. at 1:66–2:3.
The ’303 Patent

7

B.

8

The ’303 Patent is titled “Process for Forming an Electronic Device Including a Fin-Type

9

Structure” and was issued on May 4, 2010. Ex. 2 to Proctor Decl. (“’303 Patent”), ECF 144-2.
This patent claims processes for forming electronic devices that include fin-type transistor

11

United States District Court
Northern District of California

10

structures. See id. at 1:21–23; 8:59–10:51. The invention aims to improve the performance of fin-

12

type transistors by providing a greater range of available channel widths to assure operation across

13

a desired set of operating parameters. Id. at 1:28–33. Channel width may depend on fin height.

14

Id. at 1:26–28. To enable a greater range of channel widths the patent provides a process for

15

forming a semiconductor fin with a first height and removing a portion of the fin such that the fin

16

is shortened to a second height. Id. at 1:61–65.
The ’922 Patent

17

C.

18

The ’922 Patent is titled “Power Island with Independent Power Characteristics for

19

Memory and Logic” and was issued on August 23, 2011. Ex. 3 to Proctor Decl. (“’922 Patent”),

20

ECF 144-3. This patent is directed to power management and delivery in a system-on-a-chip

21

(“SoC”). See id. at 1:7–2:59. An SoC is an integrated design of hardware and software

22

components combined to form a computer on a single integrated circuit. Id. at 1:7–9. In SoC’s,

23

“some . . . components may be designed to operate at different power requirements, including

24

different voltages and/or different operating frequencies.” Id. at 1:19–22. The invention aims to

25

reduce or save power consumption in SoC’s. See id. at 1:46–2:59. In some embodiments, a first

26

power characteristic to operate a memory segment is variable over a first range of power

27

characteristics, while a second power characteristic is separately variable to operate a logic

28

segment. See id. at 5:67–6:7.
2

The ’014 Patent

1

D.

2

The ’014 Patent is titled “Method for Power Reduction and a Device Having Power

3

Reduction Capabilities” and was issued on September 13, 2011. Ex. 4 to Proctor Decl. (“’014

4

Patent”), ECF 144-4. This patent claims devices and methods for reducing power consumption of

5

components of integrated circuits. See id. at Abstract; 7:26–8:55. In one embodiment, the patent

6

teaches determining whether to power down a portion of a component based on the relationship

7

between “estimated power gain” and “estimated power loss” resulting from such powering down.

8

See id. at 4:31–39; 5:37–43; 6:46–52.

9
10

E.

The ’672 Patent

The ’672 Patent is titled “Method of Assembly and Assembly Thus Made” and was issued

United States District Court
Northern District of California

11

on September 18, 2012. Ex. 5 to Proctor Decl. (“’672 Patent”), ECF 144-5. This patent claims

12

assemblies of chips—for example, a combination of a memory chip and a logic chip, or a

13

combination of an integrated circuit and a passive chip—interconnected through solder

14

connections and methods of assembling such interconnected chips. See id. at Abstract; 1:4–28;

15

5:6–11. The invention aims to improve the stability and reliability of interconnections between a

16

first chip and a second chip using solder compositions and metallization. See id. at 1:34–53; 4:33–

17

45. The interconnection may comprise a solder bump and an underbump metallization at the first

18

chip and a metallization at the second chip. See id. at Abstract; 1:36–53; 6:46–48.
The ’836 Patent

19

F.

20

The ’836 Patent is titled “Multi-Core System on Chip” and was issued on October 22,

21

2013. Ex. 6 to Proctor Decl. (“’836 Patent”), ECF 144-6. This patent claims a multi-core system

22

on chip and methods for operating multi-core processor devices. See id. at 1:56–61; 10:44–12:47.

23

The invention aims to improve performance of a multi-core system on chip without substantially

24

increasing the power required by equipping the operating system to send tasks that cannot be

25

distributed across multiple cores to the fastest available single core. See id. at 1:65–2:10. The

26

invention provides for tasks that cannot be run on multiple cores to be run on the single core that

27

has the highest operating frequency at a given operating voltage. See id.

28
3

1

II.

LEGAL STANDARD

2

Claim construction is a matter of law. Markman v. Westview Instruments, Inc., 517 U.S.

3

370, 387 (1996). “It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the

4

invention to which the patentee is entitled the right to exclude,’” Phillips v. AWH Corp., 415 F.3d

5

1303, 1312 (Fed. Cir. 2005) (en banc) (internal citation omitted). As such, “[t]he appropriate

6

starting point . . . is always with the language of the asserted claim itself.” Comark Commc’ns,

7

Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998).

8
9

Claim terms “are generally given their ordinary and customary meaning,” defined as “the
meaning . . . the term would have to a person of ordinary skill in the art in question . . . as of the
effective filing date of the patent application.” Phillips, 415 F.3d at 1313 (internal citation

11

United States District Court
Northern District of California

10

omitted). The court reads claims in light of the specification, which is “the single best guide to the

12

meaning of a disputed term.” Id. at 1315; see also Lighting Ballast Control LLC v. Philips Elecs.

13

N. Am. Corp., 744 F.3d 1272, 1284–85 (Fed. Cir. 2014) (en banc). Furthermore, “the

14

interpretation to be given a term can only be determined and confirmed with a full understanding

15

of what the inventors actually invented and intended to envelop with the claim.” Phillips, 415

16

F.3d at 1316 (quoting Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243, 1250 (Fed.

17

Cir. 1998)). The words of the claims must therefore be understood as the inventor used them, as

18

such understanding is revealed by the patent and prosecution history. Id. The claim language,

19

written description, and patent prosecution history thus form the intrinsic record that is most

20

significant when determining the proper meaning of a disputed claim limitation. Id. at 1315–17;

21

see also Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).

22

Evidence external to the patent is less significant than the intrinsic record, but the court

23

may also consider such extrinsic evidence as expert and inventor testimony, dictionaries, and

24

learned treatises “if the court deems it helpful in determining ‘the true meaning of language used

25

in the patent claims.’” Philips, 415 F.3d at 1318 (quoting Markman, 52 F.3d at 980). However,

26

extrinsic evidence may not be used to contradict or change the meaning of claims “in derogation

27

of the ‘indisputable public records consisting of the claims, the specification and the prosecution

28

history,’ thereby undermining the public notice function of patents.” Id. at 1319 (quoting
4

1

Southwall Techs., Inc. v. Cardinal IG Co., 54 F.3d 1570, 1578 (Fed. Cir. 1995)).

2

III.

DISCUSSION

3

At the time of the parties’ joint prehearing statement the parties had not agreed on

4

constructions for any claim terms. See Joint Statement at 1, ECF 118. In their joint statement the

5

parties noted that they will “not present for construction specific terms [] that Intel asserts as

6

indefinite, as part of the Markman process.” Id. at 2 n.1. The Court notes that certain

7

indefiniteness arguments were raised by Intel in its Responsive Brief. See, e.g., Responsive Br.

8

at 9 n.6., ECF 158. Any indefiniteness or other arguments raised in footnotes are not properly

9

briefed and are denied. The Court discusses in turn the ten disputed terms.
Disputed terms in the ’806 Patent

A.

11

United States District Court
Northern District of California

10

The parties dispute two terms in the ’806 Patent: “when in a second mode of operation”

12
13
14
15

and “arrangement of transistors.” Both terms appear in independent claim 11 which recites:
11. A device, comprising:
a first memory located within an integrated circuit, the first memory having a first
memory cell topology with a first minimum operating voltage, the first memory
cell topology comprising a first arrangement of transistors;

19

a second memory located within the integrated circuit, the second memory having a
second memory cell topology with a second minimum operating voltage, wherein
the second minimum operating voltage is less than the first minimum operating
voltage and wherein the second memory cell topology comprises a second
arrangement of transistors, the second arrangement of transistors different
from the first arrangement of transistors, the second memory configured to store
status information indicative of a status of data stored at the first memory; and

20

a processing core located at the integrated circuit, the processing core operable to:

16
17
18

22

access the first memory and the second memory when in a first mode of
operation, and to access the second memory but not the first memory when
in a second mode of operation;

23

access the status information in the second mode of operation; and

24

enter the first mode of operation in response to the status information
indicating data corresponding to the data stored at the first memory had
changed.

21

25
26
27

’806 Patent at 10:31–57 (emphasis added). The term “arrangement of transistors” is also recited in
claim 6. Each term is discussed in turn.

28
5

1
2
3
4

1. “when in a second mode of operation” (claim 11)
VLSI’s Proposal
No construction needed
because the claim already
precisely defines the second
mode

Intel’s Proposal
“when a lower voltage is
provided to the first and
second memory”

5
6
7
8

Court’s Construction
Plain and ordinary meaning,
which includes the
requirement of claim 11 that
when in the second mode of
operation the voltage(s)
supplied to the first and
second memory, respectively,
must be lower than the
minimum necessary for the
first mode of operation

VLSI argues that no construction is necessary because “the inventors did not intend to
install within this claim term the additional, incorrect limitation found in Intel’s proposal that ‘a

10

lower voltage [be] provided to the first and second memory’ when [the processing core is] in the

11

United States District Court
Northern District of California

9

second mode of operation.” See Opening Br. at 3 (quoting Intel’s proposed construction),

12

ECF 143. Intel counters that “[d]uring prosecution, the applicant explained that the ‘second mode

13

of operation’ means ‘when a lower voltage is provided to the first and second memory.’”

14

Responsive Br. at 1, ECF 158. For the reasons discussed below, the Court adopts the plain and

15

ordinary meaning of “when in a second mode of operation” which includes claim 11’s requirement

16

that when in the second mode of operation the voltage(s) must be lower than the minimum

17

necessary for the first mode of operation.

18

Indisputably, claim 11 of the ’806 Patent teaches a first memory with a first minimum

19

operating voltage and a second memory with a second minimum operating voltage “wherein the

20

second minimum operating voltage is less than the first minimum operating voltage.” See ’806

21

Patent at 10:31–40. Thus, the minimum operating voltage of the second memory must be lower

22

than the minimum of the first memory.

23

Claim 11 further teaches a processing core “operable to[] access the first memory and the

24

second memory when in a first mode of operation, and to access the second memory but not the

25

first memory when in a second mode of operation.” See ’806 Patent at 10:47–53 (emphasis

26

added). In describing the second mode of operation, VLSI itself points to a portion of the

27

specification that states, “the voltage supplied to the first memory [] is reduced below its

28

minimum operating voltage, while the voltage supplied to the second memory [] is maintained
6

1

above the minimum operating voltage for the second memory.” See ’806 Patent at 4:32–36

2

(emphasis added); Opening Br. at 4. The specification further states that “[t]he second

3

memory . . . operates at a lower voltage than the first memory.” See ’806 Patent at 3:58–59

4

(emphasis added). In other words, the specification provides that in the second mode of operation

5

(1) the voltage supplied to the first memory is less than the minimum operating voltage of the first

6

memory; and (2) the voltage supplied to the second memory is lower than the operational voltage

7

of the first memory.

8

Put differently, when in the second mode of operation, both the voltage provided to the

9

first memory and the voltage provided to the second memory must be lower than the minimum
operating voltage of the first memory. Therefore, whether a common voltage or different voltages

11

United States District Court
Northern District of California

10

are provided to the first and second memory, respectively, see id. at 4:1–25, when in a second

12

mode of operation the voltage must be lower than the minimum operating voltage of the first

13

memory. Because the first mode of operation in claim 11 requires access to the first memory, the

14

minimum voltage necessary for the first mode of operation is the minimum operating voltage of

15

the first memory. See id. at 10:47–52.

16

Accordingly, the second mode of operation requires that the operating voltage of the

17

second memory is lower than the minimum operating voltage of the first memory in order to

18

“access the second memory but not the first memory.” See id. at 10:50–51 (emphasis added).

19

If in the second mode of operation the voltage was equal to or greater than the minimum operating

20

voltage of the first memory, access to the first memory would not be restricted as required by the

21

claim language.

22

At the Hearing, the Court proposed a construction consistent with that adopted here, to

23

which Intel did not object. See Hearing Transcript at 27:23–28:17, 30:13–24. Also at the

24

Hearing, VLSI acknowledged that no embodiments of the patent contemplate that when in the

25

second mode of operation the voltage can be higher than the minimum required for the first mode.

26

See id. at 32:9–19. For these reasons and due to the Court’s construction, the Court need not and

27

does not address the parties’ additional arguments.

28

In sum, the Court adopts the plain and ordinary meaning of the disputed term “when in a
7

1

second mode of operation,” which includes the requirement of claim 11 that when in the second

2

mode of operation the voltage(s) supplied to the first and second memory, respectively, must be

3

lower than the minimum necessary for the first mode of operation.
2. “arrangement of transistors” (claims 6 and 11)
VLSI’s Proposal
Intel’s Proposal
Court’s Construction
No construction needed
“number of transistors and
“arrangement of PMOS and/or
because the term as selected
connectivity among those
NMOS transistors defined by
by the inventors requires no
transistors”
the total number of transistors,
clarification
number of PMOS or NMOS
transistors, and manner of
connection between the
transistors”

4
5
6
7
8

In its briefing VLSI argued that no construction was necessary for the term “arrangement

10

of transistors” while Intel argued that the term is defined according to the “number of transistors

11

United States District Court
Northern District of California

9

and connectivity among those transistors.” See Opening Br. at 6; Responsive Br. at 5. However,

12

at the Hearing, the parties agreed that three factors inform a given “arrangement of transistors”:

13

transistor type, the number of transistors, and the manner of connection between the transistors.

14

See Hearing Transcript at 20:7–24, 35:2–4. The parties further agreed that transistor size does not

15

inform an arrangement of transistors. See id. at 33:8–20, 36:12–16. In other words, the parties

16

agreed that if the only difference between two transistor layouts was transistor size then the two

17

layouts would constitute the same “arrangement of transistors.”

18

The only remaining dispute is whether to further narrow the meaning of transistor type.

19

Intel argued at the Hearing that transistor type should be limited to “PMOS or NMOS” while

20

VLSI argued that transistor type should not be defined. See id. at 36:6–17. The Court agrees with

21

Intel. VLSI acknowledges that “the sorts of transistors discussed in the patent each fall into one of

22

two kinds: ‘p-MOS’ and ‘n-MOS.’” See Opening Br. at 6. Thus, limiting transistor type to

23

PMOS1 or NMOS is consistent with the ’806 Patent and stands only to add clarity. Accordingly,

24

here, transistor type is properly limited to PMOS or NMOS.

25
26

Based on the foregoing, the Court adopts the following construction: “arrangement of
PMOS and/or NMOS transistors defined by the total number of transistors, number of PMOS or

27
28

1

The parties interchangeably use “PMOS” and “p-MOS”; “NMOS” and “n-MOS.”
8

1
2

NMOS transistors, and manner of connection between the transistors.”
B.

1. “height” (claims 1, 8, 11, 12, 18 and 19)

3
4
5
6

VLSI’s Proposal
“a distance measured in a
direction substantially
perpendicular to a major
surface of a substrate”

7
8
9
10

United States District Court
Northern District of California

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

Disputed term in the ’303 Patent

Intel’s Proposal
“physical dimension of
distance from the base to the
top of a structure in a
direction substantially
perpendicular to a surface
from which a transistor
structure is subsequently
formed”

Court’s Construction
“physical dimension of
distance from the base to the
top of a structure in a
direction substantially
perpendicular to the primary
surface”

The term “height” appears in multiple claims of the ’303 Patent. Claim 1 is representative
and recites:
1. A process for forming an electronic device comprising:
forming a first semiconductor fin for a first fin-type transistor structure over a
support layer of a substrate, wherein, the first semiconductor fin has a first height;
and
removing a portion of the first semiconductor fin to provide the first semiconductor
fin with a second height, wherein the second height is smaller than the first height.
’303 Patent at 8:60–67 (emphasis added).
The parties agree that “height” as used in the patent corresponds to a distance measured in
a direction substantially perpendicular to a major substrate surface but dispute whether the patent
limits a single fin to a single height. VLSI argues that “the height of a fin [] can be locationdependent,” see Opening Br. at 9, while Intel counters that the fins claimed by the ’303 Patent are
defined by only “a single height at a time,” see Responsive Br. at 9. On its face, VLSI’s proposed
construction would permit the same fin to have multiple “heights” while Intel’s proposed
construction would not. As an analogy, VLSI’s construction could define a person by two
heights—one from the ground to the shoulders and one from the ground to the crown of the
head—whereas Intel’s construction would define the person’s height by only the latter.
“[T]he specification may reveal a special definition given to the claim by the patentee that
differs from the meaning it would otherwise possess.” Phillips, 415 F.3d at 1316. Such
lexicography governs where it “clearly set[s] forth a definition of the disputed claim term” and

28
9

1

“clearly expresses an intent to define the term.” See GE Lighting Solutions, LLC v. AgiLight, Inc.,

2

750 F.3d 1304, 1309 (Fed. Cir. 2014) (internal quotations and citation omitted). Here, in support

3

of their respective proposed constructions, VLSI and Intel each argue that a different definition of

4

“height” in the specification controls. VLSI advances the following definition found in column 3

5

of the specification:

6
7
8
9
10

United States District Court
Northern District of California

11

Note the term “height” is understood herein to refer to a distance measured in a
direction substantially perpendicular to a major surface of substrate 12.
’303 Patent at 3:3–6; see also Opening Br. at 8. Meanwhile, Intel advances the following
definition found in column 6 of the specification:
As used herein, the term “height” is intended to mean the physical dimension of
distance from the base to the top of a structure in a direction substantially
perpendicular to the primary surface.

12

’303 Patent at 6:21–24; see also Responsive Br. at 7. For the reasons discussed below, the Court

13

construes the term “height” according to the definition appearing at column 6, lines 21 to 24.

14

Patentee’s definition of “height” at column 6 is the only one of the two that governs under

15

GE Lighting. Although both definitions are “clearly set forth,” see GE Lighting, 750 F.3d at 1309,

16

patentee “clearly expresse[d] an intent to define the term” with respect to the definition at column

17

6 only, see id. “Height” at column 6, lines 21 to 24, is “defined . . . to aid in understanding this

18

specification.” See ’303 Patent at 5:61–62 (emphasis added); see also id. at 6:21–24. In other

19

words, the definition of height at column 6 appears within the section of the specification

20

dedicated to defining terms as they apply to the entire specification. See id. at 5:60–6:52.

21

Meanwhile, “height” as defined at column 3, lines 3 to 6, appears within a paragraph of the

22

specification dedicated only to describing Figure 3 of the patent. See id. at 2:56–3:13.

23

Moreover, “[t]he patentee’s lexicography must . . . appear with reasonable clarity,

24

deliberateness, and precision before it can affect the claim.” Abbott Laboratories v. Syntron

25

Bioresearch, Inc., 334 F.3d 1343, 1354 (Fed. Cir. 2003) (internal quotation and citation omitted)

26

(emphasis removed). The definition at column 3 states, “the term ‘height’ is understood herein

27

to refer to . . . a major substrate of surface 12,” see ’303 Patent at 3:3–6 (emphasis added), but the

28

scope of the word “herein” is unclear. The explicit reference to “a major substrate of surface 12”
10

1

indicates that “herein” as used at column 3, line 4, corresponds only to Figure 3. See id. at 6:1–13.

2

By comparison, the definition of “height” at column 6, lines 21 to 24, corresponds specifically to

3

“understanding this specification,” see id. at 5:60–61. The Court is simply not persuaded that

4

patentee’s definition of “height” at column 3 referring to a figure in a paragraph dedicated to

5

describing that figure provides the requisite “clarity, deliberateness, and precision,” see Abbott,

6

334 F.3d at 1354, to overcome patentee’s explicit definition of “height” at column 6 with respect

7

to the entire specification.

8
9

VLSI argues that “any construction of ‘height’ must be consistent with the patent’s usage
of that term” and that “only VLSI’s proposed construction satisfies th[is] requirement.” See
Opening Br. at 10. The Court disagrees that only VLSI’s proposal is adequate. VLSI’s proposed

11

United States District Court
Northern District of California

10

construction would permit the same fin to have multiple “heights” at a given time, which is not

12

supported by the specification or the claims. Instead, the patent contemplates fins having only a

13

singular “height” at a given time. See, e.g., ’303 Patent at 8:61–67 (“forming a first [] fin . . .

14

ha[ving] a first height”); 1:64–65 (“removing a portion of the [] fin such that the [] fin is shortened

15

to a second height”); 9:46–47 (“provid[ing] the third [] fin with a third height”). In other words,

16

the patent claims fins with only one height at one time. Thus, the Court finds no inherent conflict

17

between the definition of “height” at column 3 which describes “the [] value as the ‘thickness’ of

18

the previously formed layer 18 [a fin],” see id. at 3:1–3, and the definition of “height” at column 6

19

which would provide the same measurement. VLSI admits that all examples of fins disclosed in

20

the patent have a single height. See Opening Br. at 9. The Court recognizes that a patent’s claims

21

are not limited to illustrated embodiments, see Electro Sci. Indus., Inc. v. Dynamic Details, Inc.,

22

307 F.3d 1343, 1348–49 (Fed. Cir. 2002); however, the Court does not find support for VLSI’s

23

proposed construction in the claims themselves. Accordingly, the Court finds that the definition

24

of “height” at column 3 does not demonstrate additional breadth of the term. Cf. Prima Tek II,

25

L.L.C. v. Polypap, S.A.R.L., 318 F.3d 1143, 1151 (Fed. Cir. 2003).

26

VLSI additionally argues that the definition of “height” at column 6 is inapposite because

27

in the same section the specification states, “top . . . [is] intended to clarify [a] relative position[]

28

within an illustration unless expressly defined otherwise.” See ’303 Patent at 6:5–7; Opening Br.
11

1

at 9. This argument fails. For one, “height” as defined in column 6 is the controlling definition

2

for the reasons stated above, regardless of whether one or more of the words used in the definition

3

is defined elsewhere. Second, the definition of height in column 6 does not refer to “an

4

illustration,” but instead to the entire specification. See ’303 Patent at 5:61–62; 6:21–24.

5

Accordingly, the patentee’s definition of “top” does not alter the Court’s construction of the term

6

“height.”

7

Finally, the Court declines to adopt the portion of Intel’s proposed construction that would
replace “the primary surface” phrase of column 6’s definition of height with “a surface from

9

which a transistor structure is subsequently formed.” See Responsive Br. at 7. The term “primary

10

surface” is defined in the specification and needlessly stacking definition upon definition does not

11

United States District Court
Northern District of California

8

serve to clarify the claim language.

12

In sum, the Court construes the term “height” to mean “physical dimension of distance

13

from the base to the top of a structure in a direction substantially perpendicular to the primary

14

surface.”

15

C.

16
17
18
19
20
21

Disputed term in the ’922 Patent

1. “conversion controller coupled to the supply power converter” (claims 1
and 11)
VLSI’s Proposal
Intel’s Proposal
Court’s Construction
“conversion controller (which “conversion controller that is “conversion controller
is further described later in
separate from the supply
coupled to but separate from
the claim) coupled to the
power converter”
the supply power converter”
supply power converter
(which was introduced earlier
in the claim)”
The parties contest the meaning of the term “conversion controller coupled to the supply

22

power converter” in claims 1 and 11 of the ’922 Patent. Claim 1 is representative and recites:

23

1. A power island for a system-on-a-chip (SoC), the power island comprising:

24
25
26
27
28

. . . a supply power converter coupled between the supply line and the scalable
logic, wherein the supply power converter is configured to convert a supply voltage
of the external supply signal from the first power characteristics to the second
power characteristics; and
a conversion controller coupled to the supply power converter, wherein the
conversion controller is configured to control the supply power converter to change
the external supply signal according to the second power characteristics of the
scalable logic.
12

1
2

’922 Patent at 9:9–37 (emphasis added).
As an initial matter, at the Hearing, Intel confirmed that its alternative proposed

3

construction “conversion controller that is separate from the supply power converter,” see

4

Responsive Br. at 11 (emphasis added), is the “current state of play,” see Hearing Transcript at

5

62:2–4. Also at the Hearing, VLSI confirmed that it is seeking simply the claim language

6

“conversion controller coupled to the supply power converter.” See Hearing Transcript

7

at 55:10–11 (emphasis added). Thus, the only difference between the parties’ proposed

8

constructions is whether the conversion controller must be “separate” from the supply power

9

converter or merely “coupled to.”

10

That being said, the discussion at the Hearing made clear that this dispute is somewhat of a

United States District Court
Northern District of California

11

mirage—based on their representations at the Hearing, the parties do not actually disagree in a

12

significant way. Intel argues that during prosecution the applicant overcame the prior art by

13

including “the requirement that the conversion controller be ‘separate’ [from the supply power

14

converter].” See Responsive Br. at 10; see also Hearing Transcript at 58:15–61:20. Intel contends

15

that therefore the words “coupled to” as used in the term are properly construed to mean “that is

16

separate from.” See Responsive Br. at 11.

17

At the Hearing, VLSI repeatedly acknowledged that the conversion controller and supply

18

power converter are “separate elements.” For example, VLSI explained that “[the conversion

19

controller and supply converter] are coupled together, they are recited as separate elements.” See

20

Hearing Transcript at 52:22–53:2. VLSI admitted that “coupling is a connection of two things,

21

it’s not a merging into one.” See id. at 53:3–9 (VLSI agreeing with the Court’s description)

22

(emphasis added). VLSI further explained that “[w]hen things are coupled together . . . there’s

23

still separately recited elements, and whenever we apply the claims, we still have to find the

24

conversion controller. We still have to find the supply power converter.” See id. at 54:18–22

25

(emphasis added). VLSI recapped by stating, “as emphasized earlier, there are separately recited

26

elements.” Id. at 58:5–7 (emphasis added).

27
28

Thus, the Court finds no meaningful dispute over the “separate from” requirement itself.
Instead, VLSI takes issue with what Intel’s proposed construction would write out of the claim—
13

1

the “coupled to” language. See Hearing Transcript at 58:6–12 (VLSI stating, “We are not

2

suggesting that we can cut one of those [separately recited] elements out in any way, we simply

3

want to remain faithful to the claim . . . . Intel’s proposed construction[] deviates at least a little bit

4

from what the original claim said.”). In other words, VLSI does not agree that “coupled to” is

5

properly replaced with “separate from.” See id. at 54:24–55:1. The Court agrees that Intel’s

6

proposed construction is not consistent with the claims because Intel’s proposed phrase “that is

7

separate from” does not fully describe the “coupled to” claim language. Put differently, the

8

conversion controller and supply power converter could exist separate from another, without being

9

coupled to one another. For example—as discussed at the Hearing by VLSI—a wire may “couple”
together the two separate elements. See Hearing Transcript at 57:12–22. But, if not for the wire,

11

United States District Court
Northern District of California

10

the conversion controller and supply power converter would be “separate from” but not “coupled

12

to” each other. This scenario is not contemplated by the claims but would pass under Intel’s

13

proposed construction. Therefore, Intel’s proposed construction would impermissibly read out an

14

aspect of “coupled to.”

15

Accordingly, for the reasons discussed above, the Court finds it appropriate to maintain the

16

“coupled to” claim language while clarifying that the two elements are “separate from” each other.

17

Although the parties dispute whether the applicant’s statements during prosecution mandate the

18

“separate from” limitation, this disagreement is moot over VLSI’s representations at the Hearing

19

and the Court’s construction.

20
21
22
23
24
25
26
27
28

In sum, the Court construes the disputed term to mean “conversion controller coupled to
but separate from the supply power converter.”
D.

Disputed term in the ’014 Patent
1. “estimated power loss” (claims 1 and 12)

VLSI’s Proposal
“estimated loss of power”

Intel’s Proposal
“a power consumption
estimate made during the
integrated circuit’s / device’s
operation”

Court’s Construction
No construction necessary

The disputed term “estimated power loss” appears in claims 1 and 12 of the ’014 Patent.
Claim 1 is representative and recites:
14

1
2
3
4
5

1. A method for power reduction, the method comprising:
selectively providing power to at least a portion of a component of an integrated
circuit during a lower power mode; and
determining whether to power down the at least portion of the component in
response to a relationship between an estimated power gain and an estimated
power loss resulting from powering down the at least portion of the component
during the lower power mode.
’014 Patent at 7:27–35 (emphasis added). The “estimated power gain” may correspond to the

7

power saved or not used due to powering down. See id. at 5:52–57. Meanwhile, the “estimated

8

power loss” may correspond to operations required prior to powering up or down—operations

9

which themselves may require power equal to or exceeding the “power gain” from powering

10

down. See id. at 3:35–38; 6:49–52. The patent teaches powering down “if the power gain is

11

United States District Court
Northern District of California

6

greater than the power loss.” Id. at 6:49–50.

12

As an initial matter, the Court notes that Intel’s proposed construction is the alternative

13

construction proposed by Intel to “narrow the disputes.” See Responsive Br. at 12 n.9; see also

14

Hearing Transcript at 70:7–11. The parties contest two remaining points: (1) whether “loss”

15

should be replaced with “consumption”; and (2) whether the estimate of power loss must be made

16

during the operation of the integrated circuit / device. See Opening Br. at 13; Responsive Br.

17

at 12. The Court addresses each point in turn.

18

First, VLSI contends that “the concept of ‘power loss’ as recited in the claim is not the

19

same as the concept of ‘power consumption,’ which is [Intel’s proposal].” See Opening Br. at 13.

20

In support, VLSI argues that the patent distinguishes power loss from consumption, see id.,

21

pointing out that the patent expressly states, “the power loss . . . can be evaluated in response to

22

various parameters that affect the power consumption rate,” see ’014 Patent at 7:10–12

23

(emphasis added). Intel counters that a person of ordinary skilled in the art (“POSITA”) would

24

understand “power loss” to refer to an electronic device “consuming power” not “losing power.”

25

See Responsive Br. at 12. Intel also points out that the patent states, “power loss indicates the

26

power consumed during information retrieval operation . . . .” See ’014 Patent at 6:32–35

27

(emphasis added).

28

The Court agrees with VLSI that it would be improper to replace “power loss” with
15

1

“power consumption.” Intel argues that “power consumption” would “help[] the jury understand

2

the term.” See Responsive Br. at 12. However, the words of the claim must be understood as the

3

inventor used them. See Phillips, 415 F.3d at 1316. Here, the patentee drew a distinction between

4

“power loss” and “power consumption”—both terms are used in the specification, but not

5

interchangeably. For example, the specification uses “power consumption” to generally describe

6

“various power consumption control techniques [previously] suggested,” see ’014 Patent

7

at 2:19–21, and to explain that “[u]sually power consumption can vary more dynamically when a

8

larger number of segments or lines is involved,” see id. at 4:20–22. On the other hand, the

9

specification uses “power loss” specifically with respect to the claimed invention—e.g., “a power
loss associated with powering down the at least portion of the component.” See id. at 6:29–31.

11

United States District Court
Northern District of California

10

Moreover, while “the power loss . . . can be evaluated in response to various parameters that

12

affect the power consumption rate,” see id. at 7:10–12 (emphasis added), the patent contemplates

13

power loss that is not necessarily quantified as power consumption, see id. at 6:56–7:2

14

(determining whether to power down based on “the amount of dirty bits”). Finally, “power

15

consumption” is not used in the claims. See id. at 7:27–35; 8:8–18. In sum, the Court finds no

16

reason to depart from the inventor’s selection of “power loss.” See Phillips, 415 F.3d at 1316.
Second, VLSI argues that the term “estimated power loss” does not include a “temporal

17
18

limitation,” see Opening Br. at 14, while Intel contends that power loss can only be estimated

19

“during the integrated circuit’s/device’s[2] operation,” see Responsive Br. at 13 (emphasis in

20

original). Intel maintains that “the ‘power loss’ referred to in the specification varies during the

21

operation of a component of the integrated circuit/device, and therefore can only be ‘estimated’

22

during . . . operation.” See Responsive Br. at 13 (emphasis in original). In support, Intel points

23

out that every parameter the specification discloses as affecting “power loss” varies during the

24

operation of the integrated circuit/device. See id. at 13–14 (citing ’014 Patent). VLSI counters

25

that the claims include no such limitation and that “[s]imply because power loss might vary during

26

operation does not mean it cannot be estimated in advance,” see Reply Brief at 8.

27
28

2

Claim 1 of the ’014 Patent refers to an “integrated circuit” while claim 12 refers a “device.”
16

1

The Court finds that Intel’s proposed limitation “during the integrated circuit’s / device’s

2

operation” is not warranted. Intel’s argument essentially boils down to an assertion that the

3

embodiments disclosed in the ’014 Patent do not describe “estimated power loss” except during

4

operation of the integrated circuit/device. See Responsive Br. at 13–14. Even if true, such an

5

argument on its own does not mandate inclusion of Intel’s proposed limitation. See Electro Sci.,

6

307 F.3d at 1348–49 (“A Court may not import limitations from the written description into the

7

claims.”) (internal quotation and citation omitted). Indeed, “[t]he specification need not describe

8

every embodiment of the claimed invention, and the claims should not be confined to the

9

disclosed embodiments—even when the specification discloses only one embodiment.” Woods v.

10

DeAngelo Marine Exhaust, Inc., 692 F.3d 1272, 1283 (Fed. Cir. 2012).

United States District Court
Northern District of California

11

Intel represents that “the specification expressly states that ‘estimated power gain’—unlike

12

‘estimated power loss’—can be predefined.” See Responsive Br. at 14 (citing ’014 Patent at 5:64–

13

67) (emphasis in original). However, review of column 5, lines 64 to 67, reveals that the

14

specification simply states, “[a]ccording to an embodiment . . . the power gain is predefined.” See

15

id. Contrary to Intel’s suggestion, the specification does not expressly or otherwise state that

16

power loss could not be predefined—instead, the specification is silent on this point. Thus, the

17

Court turns to the claims themselves, and finds no grounds for imposing Intel’s proposed

18

limitation. Claims 1 and 12 do contain a temporal limitation (“during a low power mode,” see,

19

e.g., ’014 Patent at 7:35), but nothing of the sort suggested here by Intel. The Court is unwilling

20

to read in the proposed limitation “during the integrated circuit’s / device’s operation” based on

21

examples in the specification. See Woods, 692 F.3d at 1283.

22
23
24
25
26
27
28

In sum, the Court finds that construction of the disputed term “estimated power loss” is not
necessary or warranted.
E.

Disputed term in the ’672 Patent
1. “bumps . . . on top of the solder composition | solder interconnection layer”
(claims 3 and 12)

VLSI’s Proposal
“bumps . . . above
the solder composition |
solder interconnection layer”

Intel’s Proposal
“solder . . . on the surface of
the solder composition |
solder interconnection layer”
17

Court’s Construction
“solder bumps. . . on top of
the solder composition |
solder interconnection layer”

where “on top of” includes
the requirement that the
solder bumps must be in
contact with the solder
composition | solder
interconnection layer

1
2
3
4
5
6
7
8
9
10

The disputed term “bumps . . . on top of the solder composition | solder interconnection
layer” appears in claims 3 and 12 of the ’672 Patent. The two claims are as follows:
3. A method as claimed in claim 1, wherein the first chip is provided with further bumps
of a larger height on top of the solder composition, said first chip extending laterally
beyond the second chip.
...
12. An assembly as claimed in claim 9, wherein the first chip extends laterally beyond the
second chip and is provided with bumps that are present on top of the solder
interconnection layer.

United States District Court
Northern District of California

11
12

’672 Patent at 8:23–26, 10:1–4 (emphasis added). The parties’ disagreement concerns only the

13

first four words of the disputed term—“bumps . . . on top of,” see id.

14

VLSI proposes “bumps . . . above the solder composition,” see Opening Br. at 15

15

(emphasis added), while Intel proposes “solder . . . on the surface of the solder composition,” see

16

Responsive Br. at 15 (emphasis added). Thus, the parties’ disagreement is twofold : (1) whether

17

to use “bumps” or “solder” and (2) whether to use “above” or “on the surface of.” See id. The

18

Court addresses each dispute in turn.

19

First, VLSI argues that “not all bumps are solder,” that “not all solder is shaped like a

20

bump,” and that “‘bumps’ is a plural term, whereas ‘solder’ is singular.” See Opening Br. at 16.

21

VLSI contends that therefore, substituting “solder” for “bumps” would “alter, not explain, the

22

claims.” Id. Intel counters that based on the claims and the specification “a POSITA would

23

readily understand that the ‘bumps’ of claims 3 and 12 are an additional solder on the surface of

24

the solder composition/interconnection layer.” See Responsive Br. at 17.

25

The Court finds that the claims dictate that the “bumps” must be composed of solder, i.e.

26

“solder bumps.” As VLSI recognizes, “the claims of the patent, not its specification, measure the

27

invention.” See Reply Br. at 9 (quoting and citing Smith v. Snow, 294 U.S. 1, 11 (1935)). Here,

28

bumps are mentioned in the claims for the first time as “further bumps” in dependent claim 3.
18

See ’672 Patent at 8:23–26 (emphasis added). Dependent claim 3 relies on independent claim 1,

2

which recites the following elements: “first chip,” “second chip,” “bond pads,” “solder

3

composition,” “underbump metallization,” “metallization,” and “intermetallic compound.” See id.

4

at 8:2–19. Of these elements, the only antecedent basis for the “further bumps” of claim 3 is the

5

“solder composition” of claim 1—a point VLSI acknowledged at the Hearing, see, e.g., Hearing

6

Transcript at 99:5–10. VLSI admitted that “a particular bump can be solder, it can be made out of

7

solder composition.” See id. at 99:5–6. Put differently, the “solder composition” of claim 1 may

8

be a bump of solder and would therefore provide an antecedent basis for the “further bumps” of

9

claim 3—but necessarily only where the “further bumps” are made of solder. Accordingly, the

10

Court finds that “bumps” as used in the claims of the ’672 Patent means “solder bumps,” which

11

United States District Court
Northern District of California

1

retains the claim language while incorporating the necessary “solder” limitation.

12

Second, VLSI argues that “on top of” as used in claims 3 and 12 permits “one element [to

13

be] above (but physically spaced apart from) another.” See Opening Br. at 17. Intel proposes that

14

“the phrase ‘on top of’ should be construed as ‘on the surface of’ the claimed solder composition

15

layer.” See Responsive Br. at 16. Intel seeks this construction because it contends the “bumps” of

16

claims 3 and 12 “are in physical contact with, and thus on the surface of, the [] solder

17

composition.” See id. (emphasis in original). Indeed, the crux of this dispute is whether the

18

“further [solder] bumps” must be in contact with the solder composition of claim 3 and solder

19

interconnection layer of claim 12. See Hearing Transcript at 80:17–81:1; 88:20–23.

20

The Court finds that the phrase “on top of” includes the requirement that the solder bumps

21

be in contact with the solder composition/interconnection layer. VLSI’s proposed construction

22

would permit the “further [solder] bumps” of claims 3 and 12 to be physically untethered from the

23

solder composition/interconnection layer below. A plain reading of the claims prohibits this

24

construction. Claim 1 sets forth providing bonds pads that have “underbump metallization” at a

25

surface of a first chip. See ’672 Patent at 8:2–6. Claim 1 further requires that “solder composition

26

is provided . . . on the underbump metallization.” Id. at 8:14–15. In other words, the solder

27

composition is the top layer of the first chip/bond pad/underbump metallization/solder

28

composition stack. In claim 1, the solder composition connects the first and second chips. See id.
19

1

at 8:12–19. Dependent claim 3 requires that the first chip be provided with “further [solder]

2

bumps of a larger height on top of the solder composition, said first chip extending laterally

3

beyond the second chip.” Id. at 8:23–26 (emphasis added). To have a larger height, the “further

4

[solder] bumps of a larger height” are necessarily on the portion of the first chip “extending

5

laterally beyond the second chip.” See id. at 8:2–26. Thus, in being “on top of” the solder

6

composition the “further [solder] bumps” must be in contact with the solder composition. The

7

claims simply do not contemplate another location through which the “further [solder] bumps”

8

could be “[provided to] the first chip.” See id. at 8:23–26. A similar analysis applies to claim 12,

9

which is dependent on claim 9.
VLSI relies on Figure 1A of the patent for the proposition that there may be a gap between

11

United States District Court
Northern District of California

10

the solder bumps and solder composition/interconnection layer. See Opening Br. at 15–16. VLSI

12

argues that because elements 23 and 26 in Fig. 1A are separated by a gap, the claims contemplate

13

gaps between the solder bumps and solder composition/interconnection layer of claims 3 and 12.

14

See id. This argument is misguided. In Fig. 1A, element 26 is a “deposited solder dot” on a “lead

15

frame 10.” See ’672 Patent at 6:11–27. Elements 14 and 15 are “conductive interconnections”

16

and elements 16 and 17 are “contact surfaces.” See id. Thus, the gap in Fig. 1A between elements

17

23 and 26 simply has nothing to do with claims 3 and 12, which pertain to a method of assembly

18

of a first chip and second chip, and assembly of a first chip and second chip, respectively.

19

Accordingly, the Court is not persuaded that the “gap” in Fig. 1A referenced by VLSI teaches that

20

the solder bumps in claims 3 and 12 are not in contact with the solder composition/interconnection

21

layer.

22

VLSI additionally argues that other patents use the term “on top of” to refer to “two

23

structures [that] are physically separated,” and that therefore the term should be construed

24

similarly here. See Opening Br. at 16. This argument is unconvincing. VLSI has not shown that

25

these “other patents” are related to the ’672 Patent or that the other patents describe solder bumps

26

“on top of” a solder composition or interconnection layer. Finally, contrary to VLSI’s suggestion,

27

see Opening Br. at 17, “on top of” and “above” are not synonyms. Given two objects, for one to

28

be “on top of” the other implies contact between the objects, while “above” does not. As a
20

1

rudimentary example, given a lamp and a table, to say the lamp is “on top of” the table would

2

require contact, whereas to say the lamp is “above” the table would not. If the lamp were

3

suspended above the table, it would not be “on top of” the table.

4

Notwithstanding the foregoing, the Court is not convinced that Intel’s proposed

5

construction “on the surface of” is proper due to inconsistencies between “on the surface” and “on

6

top of.” However, Intel is only effectively seeking a requirement the solder bumps must be in

7

contact with the solder composition/interconnection layer, which the Court has found. Thus, the

8

Court declines to adopt Intel’s proposed construction “on the surface of.”

9

In sum, the Court construes the disputed term “bumps . . . on top of the solder composition
| solder interconnection layer” as “solder bumps. . . on top of the solder composition | solder

11

United States District Court
Northern District of California

10

interconnection layer.” The phrase “on top of” includes the requirement that the solder bumps

12

must be in contact with the solder composition | solder interconnection layer.
Disputed terms in the ’836 Patent

13

F.

14

Initially, the parties disputed four terms in the ’836 Patent—three so-called “task” terms in

15

claims 1, 10 and 20, and the term “running a multi-core application on a plurality of the multiple

16

cores” in claim 20. However, at the Hearing, Intel agreed with VLSI’s proposed alternative

17

constructions for the “task” terms in claims 1 and 20. See Hearing Transcript at 114:12–18;

18

Opening Br. at 17. The Court accordingly approves and adopts the following constructions:

19

Term

Agreed Construction

20

“upon identifying a processing task that can not
be run across the plurality of cores”

“upon identifying a single-core task”

21
22

(’836 Patent, claim 1)

23

“upon identifying a processing task that cannot
be run across the plurality of the multiple cores”

24

(’836 Patent, claim 20)

25

“upon identifying a single-core task”

Thus, only two terms in the ’836 Patent remain in dispute: (1) “a processing task that can

26

not be run across the plurality of cores”; and (2) “running a multi-core application on a plurality of

27

the multiple cores.” Each term is discussed in turn.

28
21

1. “a processing task that can not be run across the plurality of cores”
(claim 10)

1

VLSI’s Proposal
“a single-core task”

2
3

Intel’s Proposal
“in response to determining
that a processing task requires
a single core to run”

Court’s Construction
“a single-core task upon
identifying said task”

4

6

Alternatively:
“a single-core task upon
identifying said task”3
Claim 10 of the ’836 Patent recites:

7

10. A multi-core system on chip (SOC), comprising:

5

8

a plurality of cores, each core comprising a performance measurement circuit for
measuring a performance parameter value for said core; and

9

at least a first storage device for storing the performance parameter values for the
plurality of cores for use in selecting a core having maximized or minimized
performance parameter value at a specified voltage to run a processing task that
can not be run across the plurality of cores.

10

United States District Court
Northern District of California

11
12

’836 Patent at 11:20–29 (emphasis added).
This term is the same as the agreed-upon term in claim 1 of the ’836 Patent except this

13
14

term does not contain the “upon identifying” claim language. Indeed, the phrase “upon

15

identifying” does not appear in claim 10 of the ’836 Patent, leading to the instant dispute—Intel

16

contends that “upon identifying” nonetheless applies to claim 10, whereas VLSI contends it does

17

not. VLSI argues that claim 10 is “an apparatus claim, not a method claim,” directed to “[a] multi-

18

core system on chip (SOC)” comprising certain elements. See Opening Br. at 19; ’836 Patent at

19

11:20–29. VLSI asserts that “Intel [] seeks to inject method limitations into this apparatus claim,”

20

and that the claim language says “nothing about how or when anything is ‘determining’

21

anything . . . . [or] ‘in response to’ anything.” See Opening Br. at 19. Intel counters that the

22

“applicants’ statements during prosecution make clear that the ‘upon identifying’ phrase [of claims

23

1 and 20] also applies to claim 10.” See Responsive Br. at 20.

24

Prosecution disclaimer precludes a patentee from recapturing a specific meaning that was

25

previously disclaimed during prosecution. Omega Eng'g, Inc, v. Raytek Corp., 334 F.3d 1314,

26

1325–26 (Fed. Cir. 2003). For prosecution disclaimer to attach, “disavowing actions or statements

27
28

3

As proposed by Intel at the Hearing. See Hearing Transcript at 114:20–115:5.
22

1

made during prosecution [must] be both clear and unmistakable.” Id. According to Intel, the

2

“applicants made repeated assertions that each of claims 1, 10, and 20 require ‘identifying’ a

3

processing task that cannot be run across cores.” See Responsive Br. at 22 (emphasis in original).

4

In Intel’s view, the applicants disclaimed a broader interpretation of claim 10—that is, similar to

5

claims 1 and 20, “claim 10 must also be construed to require identification of a processing task

6

that cannot be run across the plurality of cores.” See id. at 22–23 (emphasis in original). On the

7

other hand, VLSI contends that Intel “presents [] quotes out of context,” and urges the Court to

8

read beyond Intel’s “heavily edited, out-of-context prosecution history excerpts.” See Reply

9

at 10–11.
Claim 10 is an apparatus claim that recites the functional limitation “to run a processing

10

United States District Court
Northern District of California

11

task” but does not explicitly require “identification” of the processing task. See ’836 Patent at

12

11:20–29. Intel relies on three prosecution history statements by the applicants to support its

13

theory of prosecution disclaimer. See Responsive Br. at 22–23 (citing 7/25/12 Amendment at 7,

14

Ex. 12 to Selwyn Decl., ECF 158-13; 7/25/12 Amendment at 8; 7/2/13 Notice of Allowance at

15

Bates number VLSI00001934, Ex. 12 to Selwyn Decl., ECF 158-13). For the reasons discussed

16

below, the Court finds that the applicants clearly and unmistakably represented to the Examiner

17

that “identification” is a requirement of claim 10 and therefore disclaimed any reading that does

18

not include that requirement.
To overcome rejection of claims 1 to 19 during prosecution, the applicants explained to the

19
20

examiner that:

21

[T]he claims require identification of “a processing task that can not be run by
the plurality of cores.” See, e.g., claim 1 (“upon identifying a processing task
that can not be run by the plurality of cores . . . ”) and claim 10 (“ . . . to run a
processing task that can not be run by the plurality of cores”).

22
23
24

See 7/25/12 Amendment at 8 (emphasis added and removed). The proposed language of claim 10

25

in the 7/25/12 Amendment does not differ from claim 10 of the ’836 Patent in any way relevant to

26

the instant dispute.4 Thus, the applicants explicitly admitted that claim 10 “require[s]

27
28

Claim 10 of the ’836 Patent only adds “at a specified voltage” and replaces “by” with “across,”
compared to the proposed language of claim 10 in the 7/25/12 Amendment.
23
4

1

identification of a processing task”—the applicants state that the claims include this

2

requirement, and use claim 10 as an explicit example of such a claim. See id. (emphasis added).

3

The Court cannot interpret this statement as anything but “clear and unmistakable.” See Omega,

4

334 F.3d at 1326. VLSI acknowledges that in making this statement the applicants “did address

5

the claim language,” but argue that the applicants were simply “explaining that the [E]xaminer had

6

misapprehended the claims by confusing tasks with cores.” See Reply Br. at 11. While true that

7

the applicants were discussing “identification of cores” vs. “identification of a processing task,”

8

see 7/25/12 Amendment at 8, this does nothing to limit the applicants’ clear and unmistakable

9

admission that claim 10 requires “identification,” see id.

10

The applicants’ statement quoted above is a clear and unmistakable disavowal of a broader

United States District Court
Northern District of California

11

interpretation of claim 10 and on its own sufficient to find prosecution disclaimer. That being

12

said, multiple additional statements by the applicants lend further support to the Court’s finding.

13

For example, the applicants attempt to distinguish claims 1 and 10 from the prior art by arguing

14

that “there is no teaching or suggestion by [the prior art] of identifying tasks ‘that can not be run

15

by the plurality of cores.’” See 7/25/12 Amendment at 8 (emphasis added). In other words, the

16

applicants relied on claim 10’s implicit requirement of “identification” to overcome the prior art.

17

See id.; 7/2/13 Notice of Allowance at Bates number VLSI00001934. As another example, the

18

applicants stated that “upon identifying a single-core processing task that cannot be run by the

19

plurality of cores, the core having the fastest measured processing speed parameter is selected to

20

run the identified single-core processing task. See, e.g., claims 1, 10, and 20.” See 7/25/12

21

Amendment at 7, Ex. 12 to Selwyn Decl. (emphasis added).

22

VLSI’s counterarguments are unavailing. Contrary to VLSI’s assertion, see Opening Br.

23

at 19; Reply at 11, the Court is not “rewriting” claim 10 but instead clarifying that claim 10

24

includes the same “upon identifying” requirement that the applicants clearly and unmistakably

25

admitted it did during prosecution. In addition, the Court’s construction does not inject a method

26

step into an apparatus claim, but merely “defin[es] [] part of [the] invention in functional terms.”

27

See Yodlee, Inc. v. CashEdge, Inc., 2006 WL 3456610, at *4 (N.D. Cal. Nov. 29, 2006). “There is

28

nothing inherently wrong with defining some part of an invention in functional terms. Function
24

1

language does not, in and of itself, render [an apparatus] claim improper.” Id. (internal quotation

2

and citation omitted).

3

In sum, the Court construes the disputed term “a processing task that can not be run across

4

the plurality of cores” in claim 10 as “a single-core task upon identifying said task,” which

5

incorporates the necessary identification requirement and maintains consistency with the parties’

6

agreed-upon constructions.

7
8
9
10

United States District Court
Northern District of California

11
12
13
14
15
16
17
18
19
20
21
22
23

2. “running a multi-core application on a plurality of the multiple cores”
(claim 20)
VLSI’s Proposal
No construction needed
because the terms are readily
understood

Intel’s Proposal
Court’s Construction
“in response to determining
No construction necessary
that an application requires a
plurality of the multiple cores
to run, running the application
on the plurality of the
multiple cores”

Claim 20 of the ’836 Patent recites:
20. In a multi-core processor comprising multiple cores which are controlled by system
logic, a method for executing single core applications and multi-core applications
comprising:
measuring a maximum processing speed value for reach of the multiple cores for at
least a first operating voltage;
storing each measured maximum processing speed value for reach of the multiple
cores;
running a multi-core application on a plurality of the multiple cores by
controlling each of the plurality of the multiple cores to run at a speed which is
identified from the stored maximum processing speed values to be the slowest
maximum processing speed of the plurality of the multiple cores; and
running a single core application on a single core which is identified from the
stored maximum processing speed values for the multiple cores as being the fastest
core upon identifying a processing task that cannot be run across the plurality of the
multiple cores.
’836 Patent at 12:16–35 (emphasis added).

24
VLSI argues that no construction is necessary, see Opening Br. at 24–25, while Intel
25
26

contends that “the claimed method must first determine whether an application is a multi-core
application” in order to execute that type of application on multiple cores, see Responsive Br.

27
at 24 (emphasis added). Intel acknowledges that claim 20 recites no such explicit requirement but
28
25

1

argues that the requirement is implicit in the claim, specification, and prosecution history. See id.

2

at 24–25. For the reasons stated below, the Court finds that no construction is necessary and that

3

the plain and ordinary meaning of the term “running a multi-core application on a plurality of the

4

multiple cores” controls.

5

“[C]laim terms must be given their plain and ordinary meaning to one of skill in the art.”

6

Thorner v. Sony Computer Ent. Am. LLC, 669 F.3d 1362, 1367 (Fed. Cir. 2012). A “patentee is

7

free to choose a broad term and expect to obtain the full scope of its plain and ordinary meaning

8

unless the patentee explicitly redefines the term or disavows its full scope.” Id. On its face, claim

9

20 does not include the limitation proposed by Intel and the Court does not find sufficient support

10

United States District Court
Northern District of California

11

in the remainder of the intrinsic record to implicitly read in such a requirement.
Intel asserts that because claim 20 runs a single core application “upon identifying a

12

[single-core task],” there must be an analogous “determining that an application requires a

13

plurality of [cores]” to run a multi-core application. See Responsive Br. at 24. The Court

14

disagrees. Simply because the method of claim 20 runs a single core application upon identifying

15

a single core task does create a parallel requirement out of thin air with respect to running a multi-

16

core application. Nothing in the claim language mandates Intel’s proposed limitation of

17

“determining that an application requires a plurality of the multiple cores to run.” See Responsive

18

Br. at 24. Instead, the claim is silent on this point. Intel argues that the specification and

19

prosecution history dictate that “multi-core applications are distinct from single-core applications”

20

and must be handled “separately.” See id. at 25 (citing ’836 Patent at 9:65–10:3; 7/25/12

21

Amendment at 9, Ex. 12 to Selwyn Decl., ECF 158-13). The Court does not doubt the veracity of

22

this statement—to handle multi-core and single core applications differently is a prime objective

23

of claim 20. However, the Court finds nothing in the intrinsic record that requires the method of

24

claim 20 to determine that an application requires a plurality of the multiple cores to run. Instead,

25

for example, to run a multi-core application on a plurality of the multiple cores could be by default

26

or pre-determined. The Court is simply not persuaded that Intel’s proposed limitation is warranted

27

over the surrounding claim language and presumption of plain and ordinary meaning, see Thorner,

28

669 F.3d at 1367.
26

Accordingly, the Court adopts the plain and ordinary meaning of the disputed term.

1
2
3

IV.

ORDER
As set forth above, the Court construes the disputed terms as follows:

11

“height”

12

(’303 Patent, claims 1, 8, 11, 12, 18 and 19)

13

“conversion controller coupled to the supply
power converter”

Court’s Construction
Plain and ordinary meaning, which includes
the requirement of claim 11 that when in the
second mode of operation the voltage(s)
supplied to the first and second memory,
respectively, must be lower than the
minimum necessary for the first mode of
operation
“arrangement of PMOS and/or NMOS
transistors defined by the total number of
transistors, number of PMOS or NMOS
transistors, and manner of connection
between the transistors”
“physical dimension of distance from the
base to the top of a structure in a direction
substantially perpendicular to the primary
surface”
“conversion controller coupled to but
separate from the supply power converter”

(’922 Patent, claims 1 and 11)
“estimated power loss”

No construction necessary

18

(’014 Patent, claims 1 and 12)
“bumps . . . on top of the solder
composition | solder interconnection layer”

“solder bumps . . . on top of the solder
composition | solder interconnection layer”

19

(’672 Patent, claims 3 and 12)

4

Claim Term
“when in a second mode of operation”

5
6

(’806 Patent, claim 11)

7
8

“arrangement of transistors”

9

(’806 Patent, claims 6 and 11)

United States District Court
Northern District of California

10

14
15
16
17

20
21
22
23
24
25
26
27
28

“upon identifying a processing task that can not
be run across the plurality of cores”

where “on top of” includes the requirement
that the solder bumps must be in contact with
the solder composition | solder
interconnection layer
“upon identifying a single-core task”

(’836 Patent, claim 1)
“upon identifying a processing task that cannot “upon identifying a single-core task”
be run across the plurality of the multiple cores”
(’836 Patent, claim 20)
“a processing task that can not be run across the
plurality of cores”
(’836 Patent, claim 10)
27

“a single-core task upon identifying said
task”

1
2

“running a multi-core application on a plurality
of the multiple cores”

No construction necessary

(’836 Patent, claim 20)

3
4
5
6
7

IT IS SO ORDERED.
Dated: February 15, 2019
______________________________________
BETH LABSON FREEMAN
United States District Judge

8
9
10

United States District Court
Northern District of California

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28