AVM Technologies LLC v. Intel Corporation
MEMORANDUM ORDER providing claim construction for a single term in claim 12 of U.S. Patent No. 5,859,547 (see Memorandum Order for further details). Signed by Judge Richard G. Andrews on 4/18/2017. (nms)
IN THE UNITED STATES DISTRICT COURT
FOR THE DISTRICT OF DELAWARE
AVM TECHNOLOGIES, LLC,
Civil Action No. 15-33-RGA
Presently before the Court is the issue of claim construction of a single term in claim 12
of U.S. Patent No. 5,859,547 ("the '547 patent"). The parties submitted briefing on the
construction of this term. (D.I. 628, 629). For the reasons that follow, IT IS HEREBY
ORDERED THAT the term "coupled between the logic-block output node and the precharge
node" means "positioned such that the only way charge can flow from the precharge transistor to
the logic block is by passing through the evaluation transistor."
I previously construed a number of disputed terms for this patent. (D.I. 328). During
claim construction, however, I did not construe the term "coupled between the logic-block output
node and the precharge node," which appears in claim 12. 1 Since the parties now dispute the
construction of this term, I think it is necessary for me to resolve the dispute prior to trial.
Plaintiff argues that Defendant previously stipulated to the construction of "coupled
between" as it is used in claim 12. (D.I. 621 at 2). This phrase is used four times in claim 12
and Plaintiff argues that it should have the same construction in each instance. (Id.). Defendant
counters that it argued for its preferred construction of this term in claim 12 during claim
Contrary to Plaintiffs assertion, I did not "reject" Defendant's proposed construction. (D.l. 621 at 2). Rather, I
stated that "I did not construe" this particular term. (D.l. 344 at I, n.2).
construction briefing2 and that the term should have the same meaning as a similar term in claims
1 and 19. (D.I. 628 at 2). According to Defendant, "The slight difference in language between
the 'between' limitation in claims 1 and 19 and the 'between' limitation in claim 12 does not
reflect any substantive difference." (Id. at 3).
I agree with Defendant. The language of claim 12 is substantially the same as the
language I construed in claims 1 and 19. Claim 1 recites "an evaluation transistor between the
dynamic logic block and the precharge transistor," while claim 12 recites "an evaluation
transistor having a source-to-drain path and a gate terminal, the source-to-drain path coupled
between the logic-block output node and the precharge node, the gate terminal coupled to a clock
signal node." In construing the language of claim 1, I noted that "a fundamental feature of the
invention is that the evaluation transistor separates and isolates the logic block from the
precharge node." (D.I. 328 at 15). This finding applies equally to the language at issue in the
limitation from claim 12 quoted above
The specification supports this conclusion. For example, the specification states: "The
evaluation transistor includes a gate and a source-to-drain path. The source-to-drain path is
coupled at one end to a logic-block output node 33 and at an opposed end to the precharge node."
('547 patent at 4:31-34). The specification also indicates that the circuit includes "an evaluation
transistor positioned between the logic block and precharge transistor." (Id. at 4: 18-19). In other
words, I previously determined that the evaluation transistor isolates the logic block from the
precharge node. It seems to me, then, that the source-to-drain path, which is a component of the
evaluation transistor that itself couples to the logic block output node and the precharge node,
Defendant's "argument" appeared in a footnote in the Joint Claim Construction Brief. (D.1. 286 at 53, n.25).
Defendant did not specifically identify the limitation from claim 12 as a disputed construction during claim
must also isolate the logic block from the precharge transistor. Plaintiff's proposal that
"between" means something different in this limitation of claim 12 than in claims 1 and 19 is
wholly inconsistent with my previous construction and with the claims and specification.
Plaintiff argues that Defendant's proposed construction "conflicts with claim 12's three
other uses of the term." 3 (D.I. 621 at 2). Plaintiff specifically points to another use of "coupled
between" in the specification and argues that Defendant's proposed construction would read out
a preferred embodiment. (Id.). I disagree. The portion of the specification Plaintiff cites
specifies that "input transistors are coupled between the logic-block output node and a negative
supply voltage." ('547 patent at 4:59-61). Plaintiff argues that Fig. 3D shows that there is more
than one path for current to flow; that is, current could flow through either of the input
transistors. The problem with Plaintiff's argument is that this corresponds to a different
limitation in claim 12 than the one at issue here, a limitation requiring "a logic block including at
least one transistor coupled between a second-supply voltage node and a logic-block output
node." I am not convinced that this is in conflict with the proposed construction, but whether
there is a conflict is irrelevant. I am not construing "coupled between" in isolation, nor am I
construing the limitation Plaintiff argues is in conflict with Defendant's proposed construction. I
am only construing the term "coupled between the logic-block output node and the precharge
node." Therefore, I reject Plaintiff's argument that the proposed construction reads out a
preferred embodiment and I will adopt Defendant's proposed construction. The term "coupled
between the logic-block output node and the precharge node" means "positioned such that the
The term Plaintiff is referring to appears to be "coupled between." (D.1. 621 at 2). This is not the term I was asked
to construe. Plaintiff has not proposed an alternative construction for the term I was asked to construe, relying
instead on the argument that "coupled between" must have the same meaning every time it is used in claim 12.
only way charge can flow from the precharge transistor to the logic block is by passing through
the evaluation transistor."
J! day of April, 2017.
United States District Judge
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