STC.UNM v. Intel Corporation

Filing 133

MARKMAN RESPONSE BRIEF re 110 Brief filed by STC. UNM. (Attachments: # 1 Exhibit 3 - IEDM Article, # 2 Exhibit 4 - Semiconductor International Article, # 3 Exhibit 5 - 998 Response and Amendment 01141999, # 4 Exhibit 6 - 998 Response and Amendment 05181999, # 5 Exhibit 7 - Declaration of Dr. Chris Mack)(Pedersen, Steven)

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  Exhibit 3  Reducing Variation in Advanced Logic Technologies, Kelin J. Kuhn, IEDM (2007)  Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS Kelin J. Kuhn Intel Fellow Director of Logic Device Technology Portland Technology Development Intel Corporation 12-11-07 IEDM 2007 1 Key messages • • A variety of process, design and layout techniques can be applied to mitigate the impact of random and systematic variation • 12-11-07 Process variation is not a new problem Improvements in variation in 45nm illustrate that variation does not pose an insurmountable barrier to Moore’s Law, but is simply another challenge to be overcome IEDM 2007 2 Process-Design Mitigation for Variation Management 90nm – tall 1.0 µm2 Before Optimization Design mitigation 65nm – wide - 0.57 µm2 Process mitigation - 45nm – wide w/ patterning enhancement 0.346 µm2 BEFORE After Optimization AFTER 0 Design mitigation w/ dummification 12-11-07 Process/design mitigation with computational lithography IEDM 2007 center 50 100 150 edge RADIUS (mm) Process mitigation w/ CMP improvements 25 Systematic Mismatch in the SRAM 65nm – WIDE 0.57 µm2 K. Zhang, VLSI 2004 • SRAM circuits exercise the smallest area devices in the technology • SRAM static noise margin (SNM) is sensitive to device mismatch • Although RDF is the fundamental limit for mismatch in the SRAM a large variety of systematic issues also contribute to SRAM cell mismatch These systematic issues can be mitigated with design and process changes 12-11-07 IEDM 2007 26 Systematic Variation Mitigation Strategies 90nm – TALL 1.0 µm2 65nm – WIDE 0.57 µm2 45nm – WIDE w/ patterning enhancement 0.346 µm2 DESIGN MITIGATION 90nm to 65nm: “tall” design to a “wide” design. • Single direction poly • Elimination of diffusion corners • Relaxation of patterning constraints on other critical layers 12-11-07 IEDM 2007 27 Systematic Variation Mitigation Strategies 90nm – TALL 1.0 µm2 65nm – WIDE 0.57 µm2 45nm – WIDE w/ patterning enhancement 0.346 µm2 PROCESS MITIGATION 65nm to 45nm: Patterning enhancements • Square corners (eliminate “dogbone” and “icicle” corners) • Improved CD uniformity across STI boundaries 12-11-07 IEDM 2007 28

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