Apple Computer Inc. v. Burst.com, Inc.

Filing 108

Declaration of Allen gersho in Support of 107 Response of Burst.com, Inc.'s Opposition to Plaintiff Apple Computer, Inc.'s Motion for Summary Judgment on Invalidity Based on Kramer and Kepley Patents filed byBurst.com, Inc.. (Attachments: # 1 Exhibit A to A. Gersho Declaration# 2 Exhibit B to A. Gersho Declaration# 3 Exhibit C to A. Gersho Declaration# 4 Exhibit D to A. Gersho Declaration# 5 Exhibit E to A. Gersho Declaration# 6 Exhibit F to A. Gersho Declaration (Part 1)# 7 Exhibit F to A. Gersho Declaration (Part 2)# 8 Exhibit G to A. Gersho Declaration# 9 Exhibit H to A. Gersho Declaration# 10 Exhibit I to A. Gersho Declaration (Part 1)# 11 Exhibit I to A. Gersho Declaration (Part 2)# 12 Exhibit J to A. Gersho Declaration# 13 Exhibit K to A. Gersho Declaration# 14 Exhibit L to A. Gersho Declaration# 15 Exhibit M to A. Gersho Declaration# 16 Exhibit N to A. Gersho Declaration# 17 Exhibit O to A. Gersho Declaration)(Related document(s) 107 ) (Crosby, Ian) (Filed on 6/7/2007)

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data throughput rate. Pipeline "breaks" occur when data flow isinterrupted because processing at one stage is .dependent on data which will not be available until a later time. Conditional decisions that are made in the PMC do not affect processing which has been carried out in previous stages. Pipeline breaks can therefore never occur, and the time to calculate the distortion between two k-dimensional vectors and to compare the result is always k clock periods. Fig. 3 shows a sequence of calculations performed by the PMC for the case when k = 4. Time units are specified in clock cycles. A basic unit of one-half cycle clock is meaningful since the chip uses a two-phase clocking scheme. With the exception of the Comparator, all of the pipeline stages are active on the same phase. Computation starts at t =1 with the transfer of the first components of theinputand codevector into the chip. Her?, x i denotes the ith component of the input vector and yj,; is the i th component of the j t h codevector. After two clockcycles,thevalue Ixl - yl,ll is applied to the Squaring Circuit. The first squared distance term dl,l appears at t = 5 , and is added to the accumulator contents (zero) at t = 6. In preparation for a new codebook search, the ER is set to its maximum possible value ofER,, = 2,' - 1 at t = 6. From t = 7 through t = 9, the three disand dl,4 are .accumulated together tance terms d,,,, with dlql to produce a distortion term. At t = 9.5, a comparison is made between theER contents and the Adder output. Since any accumulated distortion term present at the Adder output is less than ER,,, the subtraction in this case causes the ComparatorOutput to be driven low, indicating that the current value in the ER is greater than the Adder output. The Adder output is then transferred to the ER, where it becomes the new standard for subsequent comparisons.

Fig. 4. PMC photomicrograph.

Data flow continues in t h s manner until every codevector has been processed by the PMC. At t h s time, the ER is reset to ER,,, the old input vector is replaced with a new one, and another codebook search begins. There is no need to interrupt data flow during the transition from one input vector to another.

C. Implementation
To provide a description of some of the more subtle features in our design, we now present some aspects of the chip in greater detail. To begin, Fig. 4 shows a photomicrograph of this VLSI circuit. Data enter the two 12-bit input buses along the top edge of the figure and flow from top

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to bottom through the seven array stages. The largest circuit element is the Squaring Circuit, which consumes 20 percent of the available area. Note that approximately 25 percent of the available chip area is presently notused. Part of this area will be utilized in the second-generation chip to expand its capabilities. The second feature of the chip that we will discuss is the Subtractor/Absolute Value circuit. Weuse a special algorithm for calculating absolute differences, since the conventional method is not attractive for use in a pipelined processor. A conventional algorithm for calculating absolute differences between two numbers A and B is shown below. A and B represent n-bit twoys-complement numbers, and C represents. an n-bit unsigned integer. C* is an (n 1)-bit intermediate result.

We partitionthe 12-bit input word C, which is the output of the Subtractor/Absolute Value Circuit, into four unsigned 3-bit words den.oted W,X, Y, and 2. Then C can be written as

c = w.29+

x.26+ Y.23

+ z.

By defining three functions F, G, and H appropriately, we can then write C 2 as

`C2=F(W,X)*216+G(W,Y).213+F(X,Y).210

+ G(W,

2).21° G(X, Z ) . 2 7 + H ( Y , 2 ) .

+

+

where the partial product functions are defined as

F ( i , j ) = 4.i2

+i.j +j2.

To compute: C + ] A- B I 1) C * + - A - B 2) If c*> 0 C+C* else C+C*+l,
where the bar represents a one's complement operation. The problem with this algorithm is thatthe number of logic operations required in the second step (either 0 or 2), is conditional upon the sign bit of C*. The algorithm above is not amenable to implementation as a pipeline array since the data dependency causes an interrupt in the sequential data flow (a pipeline "break"), which is accompanied by a reduction in throughput. This problem may be avoided if we rewrite the algorithm as follows: 1) C * + - A + B 2) If c*> 0 C+C*+l else Ct

G ( i , j ) = i.j
~ ( i ), = +26+ i.j.24 j

c*.

In this case, the number of required logic operations in step 2)is one, independent of the sign of C*. We can implementthe second step as an arithmetic unit which either adds 1 to the input or takes its one's complement. The sign bit of C* can be used asa control inputto determine the logic performed by this stage. This is the form of the Subtractor/Absolute Value Circuit in the PMC. The Squaring Circuit is based on ROM table lookups rather than a conventional multiplier. Bits from' the input word are used `to address six PLA-based ROM'swhich generatepartialproduct terms. These terms are subsequently shifted and accumulated by the next .two pipeline sections. One 24-bit result can be computed by this array every clock period.

The particular partial product functions shown. above were chosen to minimize the number of bits stored in ROM. The number of bits in each ROM is determined by the dynamic range of the particular function in question. The F, G, and H ROM's require output word widths of 8, 6 , and 12bits, respectively. As a result, the total number of bits stored in the Squaring Circuit is only 2944, as compared to 98 304 for the case of a single large ROM. The tablelookup method has two advantages over a conventional Booth multiplier. First, the circuit is simpler than a multiplier with equivalent input word width. Second,the throughput of the ROM-based implementation will often be higher since each of the three stages can be individually clocked at a higher rate than a single more complex multiplier stage. The primary disadvantage of this scheme is that the latency time is three clock periods compared to only one for a conventional multiplier. The latency time for a circuit element is the elapsed time after aninput is applied for the corresponding output to be produced. In our application, this extra latency time (two clock periods) is negligible compared to .the overall processing delay of approximately Nk clock periods introduced by a pattern-match computation.

IV. REAL-TIME SPEECH CODER IMPLEMENTATIONS In this section we describe the function and structure of two real-time hardware speech coders based on vector quantization. Both of these coders utilize the basic CSP architecture for performing codebook-search computations. The first coder, already constructed, is a compact realization of Vector PCM on a single circuit board. We present the results of several experiments performed with this unit. The second coder, recently implemented, performs an adaptive vector predictive coding (AVPC) algorithm based on [SI.

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k=4,8

I

I

I

fc=3.6 kHz
Fig. 5. VPCMspeechcommunicationsystem.
. .

A . A Single-Board VPCM Speech Communication System
A VPCM coder exploits the hgh correlation between samples in a speech waveform contained within one vector and therefore outperforms scalar sample-by-sample quantization at the same bit rate. Simulated results from other, more sophisticated, VQ-basedspeech coding algorithms such as AVPC [5], Shape-Gain VQ [14], and HVQ [15], [16], show that VPCM is inferior for feasible vector dimensions atthe same bit rate. Nevertheless, since our main goal in this project was to demonstrate the feasibility of using the PMC in a real-time speech coder, the inherent simplicity of VPCM made itan ideal choice for a first implementation. Fig. 5 shows a basic block diagram of the hardware configuration for a half-duplex VPCM communication system. The transmitter consists of a band-limiting low-pass filter, a 12-bit linear A/D converter with sample-and-hold, and one CSP unit. A simple table lookup unit, 12-bit linear D/A converter, and reconstruction low-pass filter are used in the receiver. The sampling rate f, = 1/T, is 8 kHz, and the low-pass filters have a cutoff frequency of 3.6 kHz. Although this configuration operates in half-duplex mode only, full-duplex operation can be realizedwithonly a slight increase in hardware complexity (chip count). In the system shown in Fig. 5, the input signal x ( t ) is converted to a discrete-time, discrete-amplitude source x,, which is blocked into vectors and quantized by the CSP unit. For the case of VPCM, the CSP contains only one codebook ROM bank ofsize k N storage locations. Furthermore, the Codebook Data Bus and Address Generator Bus are not required. Codebook indexes I, are transmitted individually every kT, seconds. The decoder generates the discrete-time discrete-amplitude signal 2,, by using to addressthe receivercopy of the codebook. A low-pass filter smoothes the D/A output to produce a reconstructed signal 2 ( t ) . This coder is designed to use codebooks of size 128,256, and 512. Since the vector dimension can be either 4 or 8, the total number of possible transmission bit rates is six, ranging form 0.875 to 2.25 bits/sample. Total encoding delay in this system is 2kT, seconds. A photograph of the circuit board containing one transmitter and receiver is presented in Fig. 6. The board contains a total of 44 analog and digital IC's whch occupy

Fig. 6 . Photograph of VPCMimplementation

an area of 18 X 20 cm2. Thirty-six devices, including the PMC, are used in the transmitter. Reflecting the general fact that VQ decoders are much simpler than their associated encoders, the receiver contains only 8 IC's. Encoder and decoder codebooks are separately stored in EPROM's. Our experiments with this coder confirm that it works properlyfor codebooks of size 128 and 256. The PMC chips which were fabricated run at a maximum clock rate of 3 MHz, so that the largest codebook size for any VPCM coder using a chip from this batch with a sampling rate of 8 kHz is 375. Therefore, we presently cannot use the coder with N = 512. We have recently completed a redesign of the PMC to allow a larger range of vector dimensions and an increased clock rate. We are confident that a clock rate of at least 4 MHz will be achievedwith the improved circuit layout used in this second-version chip. In this case, codebooks of size 512 could be exhaustively searched by the VPCM coder in real time. We designed one codebook for each possible rate in this coder (0.875, 1.0, 1.125,1.75,2.0, and 2.25 bits/sample). The codebooks were designed using the Linde=Buzo-Gray (LBG) algorithm [3] with a 25 s training sequence containing 200 000 waveform samples from 2 male and 2 female speakers. In addition, a sequence of 100 000 samples not contained in the training set used was in a computer simulation to test codebook robustness. Table I gives the SNR values achievedwiththese codebooks when inside and outside training set data are used. We now describe some experimental results obtained using the VPCM single-board coder. One of the more elusive problems we faced was to confirm that the hardware correctly implements the VPCM algorithm. The purpose of our first set of experiments, then, was to verify that the hardware coder can match the performance of computer simulation data. In a second set of experiments, we

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RESULTS Fate
( B i t s per sanple)
.875

TABLE I FROM VPCM SIMULATIONS
SNR

I

I

Dimensim k
8 8 8

(a)
atside Training Set
91 .

Training Set

Inside
10.1 11.2 12.1 13.8 15.1

10 . 1.125

9.9

10.6

IO

17 .5
20 .

4 4 4

13.5
14.1 16.0

2.25

16.5

-

TONE INPUT, RELATIVE AMPLITUDE = -14 dB RATE= 2 0 BITS PER SAMPLE .

\

-

evaluated the coder under various input conditions and conducted informal listening tests to judge its perceptual quality. In general, testing a real-time implementation for correctness is difficult and raisesissueswhich are distinctly differentfrom those involved in -algorithm development [17]. In many instances, the correctness of a speech coder implementation is ultimately judged by listening tests in which the outputs of simulated and real-time coders are compared. This is our approach in Experiment 1, outlined below. A speech passage 9 s long consisting of one female and one male speaker was coded at a rate of 16 kbits/s by the single-board coder. A computer simulation using the same speech input signal and codebook was performed with single-precision floating-point arithmetic. A :B and B : A pairs were constructed from these two coded passages, and then four of these pairs were recorded onto cassette tape such that ordering from pair to pair was random. For each A : B and B :A pair, six listeners were asked to identify the coded passage (either the first or second) which they perceived to be of higher quality. Subjects were not aware of the order in which the simulated and real-time coded passages were presented. Resultsfrom this testshow that the simulated coded speech was judged to be of higher perceptual'quality in 54 percent of the comparisons (versus 46 percent for the real-time coded speech). This indicates that listeners could not easily distinguish between the simulated and real-time coded speech. In Experiment 2, we objectively evaluated the SNR performance of the VPCM coder. Our basic strategy was to measurethe SNR achieved by the hardware coder for various pure tone inputs and to then compare these results to computer simulation data. The measured SNRdata were obtained with a distortion analyzer. For all of these tests, we used the codebook corresponding torate 2.0 bits/sample shown in Table I. Fig. 7 shows a plot of reconstructed signal SNR versus frequency for simulation and measured data. These curves were obtained with a tone input amplitude of -14 dB relative to the A/D converter saturation 'value. Note that the two curves match to within 1.5 dB for all input frequencies, and show very good agreement up to 2.0 kHz. The rapid decrease in SNR with increasing frequency for

0 01 .0

0.32

I

I .o

I

3.2

INPUT FREQUENCY, (kHz)
Fig. 7. Tone SNR versus frequency for VPCM coder.

'

201

I

T

1

I

SIMULATION 7 RESULT

1
I

500 HZ TONE INPUT RATE = 2.0 BITS PER SAMPLE

2

0

- 40

- 30

I

- 20

I

I

-10
(dB)

0

RELATIVE INPUT AMPLITUDE,

Fig. 8. Tone SNR versus relative input amplitude for VPCM coder.

both curves is a result of. the statistical nature of sp,eech signals used for the codebook design. High-frequency speech signals are less correlated than low-frequency ones, so thereis less redundancy for the vector quantizer to exploit. In addition, signals high with amplitude and frequency are not as probable in spoken English as highamplitude low-frequency signals, and therefore signals in the latterclass are better represented by codevectors. Fig. 8 shows a similar plot for the case when the tone input frequency is fixed at 500 Hz and the relative amplitude is varied. In this case, the SNR curves match for all relative amplitudes to within 1.1dB. Next, we evaluated the hardware coder performance for various speech signal classes.Fig.9(a)-(f)showsoscilloscopephotographs of original and reconstructed signals from the VPCM coder. All waveforms in Fig. 9 are coded at a rate of 2.0 bits/sample with the codebook described in Table I. Since the dimension is 4,one vector is 0.5 ms in duration. Segments of the phonemes 1 1 lei, Itl, IzhI, and 1, I/I.are shown. Note that the vowels 11 and I E ~ are repro1 duced most accurately. This is explained by noting that vowels are very common phonemes in English and, hence,

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QUANTIZATION PROCESSOR
h

Sn

--In
OUANTIZER CODEBOOK MEMORY VECTOR LINEAR MEMORY VECTOR LINEAR PREDICTOR

I I

I

I--+

_ _ _ _ _ INFORMATION & ----____ SIDE
Fig. 10. AVPC blockdiagram.

I

I I

J

AVPC is described by the diagram in Fig. 10. A prediction E, of the current input vector s, is subtracted from s,, andtheerror e",isencoded by a vector quantizer. An AVPC decoder is identical in structure to the encoder prediction filter, but the output is in instead of E,. The Mth-order linear prediction filter produces 9, given by
M

E,

=
j=l

AjS"n-j,

Fig. 9. Original (top) and reconstructed (bottom) signals from the VPCM 1, It[, (zhl,and 11( f ) 300 Hz tone, relative 1. coder. (a)-(e) Phonemes 1 1 input amplitude - 8.9 dB. Tlme scale for (a), (b), (d), and (e) Zms/div; (c) 1 ms/div; (f) 0.5 ms/div.

IC[.

are weighted heavily in the codebook design process (LBG algorithm). Conversely, It1 and 1 in Fig. 9(c) and (e) are 1 1 reproduced least accurately, since stop consonants and fricatives are usually short in duration and relatively infrequent in English. Fig. 9(f) shows how the coder performs for a 300 Hz tone input with a relative amplitude of - 8.9 dB. Finally, we comment on the overall perceptual quality of this coder. Informal listening tests indicate that the reconstructed signal quality at a rate of 16 kbits/s is roughly equivalent to that of CVSD at the same rate. Both coders introduce distortionwhich is similarto additive white-noise. Furthermore, the perceivednoiselevelis correlated with the input signal energy in thesense that the noiselevel increases as the input energy increases.
B. Real-Time Speech Coding with A VPC

We can improve the performance of many conventional coding schemes byreplacing a scalar quantizer with a low-dimensionality vector quantizer. This concept is applied in adaptive vector predictive coding (AVPC), in which DPCM is extended to a vector-based adaptive predictive coding scheme [5]. Computer simulations show that for dimensions up to 8 or so, AVPC achieves significantly better SNR performance than VPCM at the same bit rate, often with only a modest increase in system complexity.

where each A, is a k X k predictor matrix and 5, is the reconstructed version of s,. Samples of the input waveform are grouped into frames of length L , and adaptation occurs once per frame. Adaptation consists of classifying each frame into one of m types and selecting the particular codebook and/or set of M matrices {Aj}, i E (1,2,.. -, } , for the type. Each m codebook-predictor pair is optimized appropriately for its associated class.Some side information (the amount is application-dependent) is usuallytransmitted to the decoder to designate which codebook-predictor pair wasused to encode the current frame. We have recently implemented a real-time AVPC speech compression system which will operate at various bit rates between 1 and 2 bits/sample with a vector dimension of 4 or 8. We use switched-prediction, in which the sets { Aj} are designed off-line and stored in the transmitter and receiver. Each frame is classified into one of three types based on the first two frame autocorrelation values (R,,(O) and R x x ( l ) )and a,, the long-term energy of speech (constant with time). The classification determines whlch of three fixed predictor-codebook pairs will be used for that frame, and 2 bits of side information are transmitted to identify the predictor-codebook pair which has been selected. The frame-size L is 60 samples. Our approach in the hardware design was to combine one general-purpose DSP chip, the TMS-32010, with a CSP module of the typeused in our existing real-time VPCM coder. The DSP classifies frames and calculates the vector quantities in,E,, and e", since its architecture is well suited for these tasks. Codebook searches are much more computationally demanding and are performed by the CSP module. DSP program flowcharts for the encoder and decoder are presented in Fig. 11 for the case of first-order predict'

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MAIN ROUTINE:

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a TI
(-1
INITIALIZE

INTERRUPTROUTINE

:

e, = s,-s,

0
TRANSMIT TABLE LOOKUP

FROM CSP

<ENTER-)
MACHINE

READ A I D

TO C S P

UPDATE

INFO : i
CODE SEARCH DONE ?

RESTORE MACHINE

<EXlr)
DECODER ROUTINE:

CLASSIFY SUBROUTINE:

n
INITIALIZE RECEIVE INFO: i TABLE LOOKUP FOR Q (Zn)

(F)

& NO

4
CLASS 3
.

NO

READ A: INTO D.M.

SELECT CODEBOOK 3,

/E&?,
:LASS I CODEBOOK 2, CODEBOOK I,

0
n=n+l

Fig. 11. DSP program flowcharts for AVPC coder. (a) Main routine. (b) Frame classification routine. (c) Interrupt routine. (d) Decoder routine.

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TABLE I1 BREAKDOWN DSP TASKS REAL-TIME OF FOR AVPC CODER
H W often executed
W K clock of Cycles KeqUlKed (TW-32010)

Initialize System
I I R m Rwtine N RT E

Once a t p a r e r m
Once per -le

Calculate S,,

k = Vector D h s i m , N =

codebmk Size

ion ( M = 1). All vector prediction calculations andan end-of-frame check are included inthe MAIN routine, shown in Fig. ll(a). At the frame boundaries, subroutine CLASSIFY is called to select a codebook and predictor matrix Ai, i E {1,2,3}, for the next frame. The selected matrix is read into the TMS-32010's data memory at this time. Classification by the DSP occurs in parallel with the CSP codebook search for the last vector in each frame. A third routine called INTERRUPT is executed whenever a new waveform sample arrives. Input samples are stored in a circular buffer of size 2L. Note+that autocorrelation values R,,(O) and Rxx(l) are calculated by updatinga running double-precision accumulation of products each time INTERRUPT is executed. When CLASSIFY is called, the autocorrelation values for the next frame will be available for use. The DECODE routine is a simplified version of MAIN and is shown in Fig. ll(d). A breakdown of tasks performed by the TMS-32010 in the encoder and the number of clock periods required to execute them are presented in Table 11. Our calculations show that when used with a CSP running a 3 MHz, one TMS-32010 will be utilizedonly 10 percent of the time when N = 256 and k = 4.For the case when N = 256 and k = 8, the utilization increases to 11 percent. This indicates that the substantially unused DSP capability may be exploited to make future improvements to the coder presented here.

The price paid for these advantages is the exponential growth of algorithm complexity with vector dimension for a fixed rate. This characteristic has in the past inhibited the incorporation of vector quantizers into real-time speechcompression systems. Recently, however, VLSI technology has progressed to the point where it is not only feasible but relatively straightforward to implement special-purpose high-speed processor architectures for codebook searching on a single chip. In computation-bound applications such as pattern matching, the choice of processor architecture strongly influences the data throughput rate. Therefore, an appropriately designed special-purpose device can attain substantially greater throughput than a general-purpose processor. The complexity problem associated with vector quantization can be counteracted by exploiting the repetitive and nonconditional nature of codebook-search computationsinthe design of a dedicated processor. The Codebook-Search Processor has such an architecture. The pattern-matching'chip represents our first step toward the goal of realizing sophisticated VQ-based speech coders using VLSItechnology. Results presented in this paper demonstrate the feasibility of implementing compact real-time speech coders based on VQ. Current or enhanced versions of the PMC may be used to realize more powerful VQ coderswith a minimal amount of hardware by combining one or more CSP modules with general-purpose DSP chips.

ACKNOWLEDGMENT The authors gratefully acknowledge the substantial contributions of T. Stanhope, R. Aravind, and s. Butner to the development, fabrication, and testing of the VLSI PatternMatchingChip.The conceptual design of the absolute difference and squaring circuits is due to T. Stanhope. Layout of these two circuits was performed by R. Aravind and T. Stanhope. Berkeley-Caesar CAD tool instruction was given by S. Butner, who also generously provided the instructionand facilities necessary for testing the PMC. The real-time AVPC system was designed jointly with K. Zeger and R: Iltis.

V. CONCLUSIONS Theoretical and computer simulation results show that vector quantization is a very attractive technique for source compression. VQ is an asymptotically optimal coding scheme for a fixed rate in the sense that the rate-distortion lower bound isachievedwhen the vector dimension is allowed to increase to infinity. The conceptual simplicity and generality of vector quantization make it ideal for incorporation.into other types of coders. Computer simulations have proven this to be a veryuseful approach to speech coder design.
REFERENCES

R. M. Gray, "Vector quantization," I E E E Acourt., Speech, Signal Processing Mug.. Apr. 1984. A. Gershoand V. Cuperman,"Vectorquantization: Apatternmatching technique for speech coding,"I E E E Commun. Mug., Dec. 1983. Y . Linde,A. Buzo, and R. M. Gray,"Analgorithmforvector quantizer design," I E E E Trans. Commun., vol. COM-28. pp. 84-95, Jan. 1980. et ul,, "Hardwarerealization of waveformvector B. P.M.Tao Areas Commun., vol. SAC-2, pp. quantizers," I E E E J . Select. 343-352, Mar. 1984. V. Cuperman and A. Gersho, "Vector predictive coding of speech at 16 kbits/s," I E E E Trans.Commun., vol. COM-33,no. I , July

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1985. See also: V. Cuperman and A,'Gersho, "Adaptive differential Global Commun, vectorcoding of speech,"in Conj.Rec.,IEEE Con/., Dec. 1982, pp. 1092-1096. A. Buzo, A. H. Gray, Jr., R. M. Gray, and J. D. Markel, "Speech IEEE Trans, Aco~f., coding based upon vector quantization," Speech, Signul Processing, vol.ASSP-28, no. 5 , pp. 562-574, Oct. 1980. ,800 bits/sand [71 D. Y. Wongand B. H. Juang,"Voicecodingat lower data rates with LPC vector quantization," inProc. IEEE Int. Con/. Acourt., Speech, Signal Processing, Paris, France, May 1982, pp. 606-609. S. Roucos, R. Schwartz, and J. Makhoul, "Vector quantization for very-low-rate coding of speech," in Con/. Rec., 198-1 IEEE Global Commun. Con/., Miami, 29-Dec. FL, Nov. 2, 1982, pp. E6.2.1-E6.2.5. H. Abut, R. M. Gray, and G. Rebolledo, "Vector quantization of speech and speech-like waveforms," IEEE Trans. ACOUSI., Speech, Signul Processing, vol. ASSP-30, p 423-436, June 198?; G. Davidson, R. Aravind, T. Stadope, and A. Gersho, Real-time speech compression with a VLSI vector quantization processor," in Proc. I n t . Conj. ACOUSI., Speech, Signal Processing. Tampa,FL, Mar. 1985. D. Y. Cheng, A. Gersho, B. Ramamurthi, and Y. Shoham, "Fast search algorithms for vector quantization and pattern matching," in Proc. Int. Con/. ACOUSI., Speech, Signal Processing, San Diego, CA, Mar. 1984. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1979. J. Newkirk and R. Mathews, The VLSI Designer's Libraty. Reading, MA: Addison-Wesley, 1983. M. J. Sabin and R. M. Gray, "Product-code vector quantizers for waveform and voice coding," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 474-488, June 1984. of A. Gersho and Y. Shoham,"Hierarchicalvectorquantization speechwithdynamic.codebookallocation,''in Proc.Int.Con/. ACOUSI., Speech, Signal Processing, San Diego, CA, Mar. 1984. Y. Shoham and A . Gersho, "Pitch-synchronous transform codingof speech at 9.6 Kb/s basedonvectorquantization,"in Proc. ICC 1984, pp. 1179-1182. J. Wolf and K. Field, "Real-time speech coder implementation on Trans. Commun., vol. COM-30, pp. anarray processor," IEEE 615-620, Apr. 1982.

degree in electrical engineering from the University of California, Santa Barbara, in 1984. He is currentlyworkingtowardthePh.D. degree in electrical engineering at UCSB. From 1980 to 1982, he worked the with McDonnell Douglas Astronautics Company, Huntington Beach, CA, where he performed electronic and design trajectory simulations for vehicle guidance, navigation, and control applications. Since 1983, he has been a Research Assistantin the CommunicationsResearchLaboratory at UCSB. His current research interests are medium to low bit-rate speech compression using vector quantization and predictive coding techniques.Heisalsointerestedindevelopingspecial-purposecomputer architectures for DSP applications.

Grant A. Davidson (S'83) was born in San Francisco, CA, on March 19, 1958. He receivedthe B.S. degreeinphysicsfromtheCaliforniaPolytechnic University, State San Luis Obispo,1980, in and the M.S.

received the B.S. degree from the Massachusetts Institute of Technology, Cambridge, 1.960,and the Ph.D. in degree from Cornel1 University, Ithaca, NY, in 1963. He is a Professor of Electrical and Computer Engineering at the Universityof California, Santa Barbara, where his current research interests are in the areaof speech and image processing with a focuson the use of vectorquantizationtechniques. He was at Bell Laboratories from 1963to 1980, where he waseng;aged in research in signal.processing for communications. Dr. Gersho has served as Editor of the IEEE COMMUNICATIONSG MA AZINE and Associate Editor of the IEEE TRANSACTIONS COMMUNION CATIONS. He received the Guillemen-Cauer Prize Paper Award in 1980, the Donald McLellan Award in 1983, and an IEEE Centennial Medal in 1984. He also served on the Board of Governors of the IEEE Communications Society from 1981 to 1984.

Allen Geisho (S'X-M64-SM78-F`82)