Netlist, Inc. v. Google Inc.

Filing 45

JOINT CLAIM CONSTRUCTION STATEMENT and Prehearing Statement Under Patent Local Rule 4-3, filed by Netlist, Inc., Google Inc.. (Attachments: # 1 Exhibit A, # 2 Exhibit B)(Hansen, Steven) (Filed on 6/25/2010) Modified on 6/28/2010 (jlm, COURT STAFF).

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Exhibit B to Joint Claim Construction and Prehearing Statement under Patent L.R. 4-3 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS bank NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE Proposed Construction "a group of memory cells or locations inside a memory device" Support in Specification 1:31-34: "Memory modules typically have a memory configuration with a unique combination of rows, columns, and banks which result in a total memory capacity for the memory module." 1:40-44: "The memory cells (or memory locations) of each 512-Mb DRAM device can be arranged in four banks, with each bank having an array of 224 (or 16,777,216) memory locations arranged as 213 rows and 211 columns, and with each memory location having a width of 8 bits." 1:58-61: "The memory locations of each 1-Gb DRAM device can be arranged in four banks, with each bank having an array of memory locations with 214 rows and 211 columns, and with each memory location having a width of 8 bits." 9:18-21: "In certain embodiments in which the density bit is a row address bit, for read/write commands, the density bit is the value latched during the activate command for the selected bank." 21:59-61: "In certain embodiments, a copy of the Al3 address is saved by the PLD 42 for each of the internal banks (e.g., 4 internal banks) per memory device 30." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Proposed Construction "an addressable unit of memory cells" Support The Authoritative Dictionary of IEEE Standards Terms, Seventh Edition, 2000. IEEE "bank" "A contiguous section of addressable memory." 1:31-34 "Memory modules typically have a memory configuration with a unique combination of rows, columns, and banks which result in a total memory capacity for the memory module." 1:58-62 "The memory locations of each 1-Gb DRAM device can be arranged in four banks, with each bank having an array of memory locations with 214 rows and 211 columns, and with each memory location having a width of 8 bits." 9:57-58 "Byte 17: Defines the number of banks internal to the DRAM device used in the memory module" 10:59-62 "Each memory device 31, 33 has a first bit width, a first number of banks of memory locations, a first number of rows of memory locations, and a first number of columns of memory locations." 1 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Extrinsic Support JEDEC, Dictionary of Terms for Solid State Technology, JESD88 December 2009) at 14: Bank address (BA): In a RAM that has multiple banks in its architecture, the address used to select any one of the available banks. Bruce Jacob, et al., Memory Systems: Cache, DRAM, Disk (Elsevier, Inc. 2008) at 321. See, e.g., Figure 7.8 showing a DRAM's internal bank. Deposition Transcript of William Hoffman, dated May 18, 2010 (Google v. Netlist, CV08-4144) at 52, 235-236 and 267-268. at least one integrated circuit element comprising a logic element, a register, and a phase-lock loop Proposed Construction "one or more integrated circuit elements, wherein a logic element, a register, and a phase-lock loop are distributed among the one or more integrated circuit elements" Specification Support 5:37-55 "While the phase-lock loop device 50, the register 60, and the logic element 40 are described herein in certain embodiments as being separate components, in certain other embodiments, two or more of the phase-lock Proposed Construction Google contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. 2 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE loop device 50, the register 60, and the logic element 40 are portions of a single component. Persons skilled in the art are able to select a phase-lock loop device 50 and a register 60 compatible with embodiments described herein. In certain embodiments, the memory module 10 further comprises electrical components which are electrically coupled to one another and are surface-mounted or embedded on the printed circuit board 20. These electrical components can include, but are not limited to, electrical conduits, resistors, capacitors, inductors, and transistors. In certain embodiments, at least some of these electrical components are discrete, while in other certain embodiments, at least some of these electrical components are constituents of one or more integrated circuits." set of input control signals (claim 1) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of input control signals" is a "set of varying electrical impulse inputs that convey information for regulating system operations, including addresses and commands, from one point to another" Specification Support Figures 1A, 1B, 2A, 3A Proposed Construction "input control signals including at least one row/column address signal, bank address signals, and at least one chip select signal, but not including a first command signal" Support Claim 1 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks; a GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) 3 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) circuit mounted to the printed circuit board, the circuit 5:14-21: "The logic element 40 receives a set of input comprising a logic element and a register, the logic element control signals from the computer system. The set of input receiving a set of input control signals from the computer control signals correspond to a second number of memory system, the set of input control signals comprising at least devices smaller than the first number of memory devices. one row/column address signal, bank address signals, and at The logic element 40 generates a set of output control least one chip-select signal, the set of input control signals signals in response to the set of input control signals. The corresponding to a second number of DDR memory devices set of output control signals corresponds to the first arranged in a second number of ranks, the second number number of memory devices." of DDR memory devices smaller than the first number of 6:55-7:2: "As schematically illustrated by FIGS. 1A and DDR memory devices and the second number of ranks less 1B, in certain embodiments, the logic element 40 receives than the first number of ranks, the circuit generating a set of a set of input control signals, which includes address output control signals in response to the set of input control signals (e.g., bank address signals, row address signals, signals, the set of output control signals corresponding to column address signals, gated column address strobe the first number of DDR memory devices arranged in the signals, chip-select signals) and command signals (e.g., first number of ranks, wherein the circuit further responds refresh, precharge) from the computer system. In response to a first command signal and the set of input control to the set of input control signals, the logic element 40 signals from the computer system by generating and generates a set of output control signals which includes transmitting a second command signal and the set of output address signals and command signals. In certain control signals to the plurality of memory devices, the first embodiments, the set of output control signals corresponds command signal and the set of input control signals to a first number of ranks in which the plurality of corresponding to the second number of ranks and the memory devices 30 of the memory module 10 are second command signal and the set of output control arranged, and the set of input control signals corresponds signals corresponding to the first number of ranks; and a to a second number of ranks per memory module for phase-lock loop device mounted to the printed circuit which the computer system is configured." board, the phase-lock loop device operatively coupled to the plurality of DDR memory devices, the logic element, 11:52-57: 11:52-57: "The logic element 40 then receives and the register." a set of input control signals corresponding to a single rank from the computer system's memory controller, and 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, generates and transmits a set of output control signals in certain embodiments, the logic element 40 receives a set corresponding to two ranks to the appropriate memory of input control signals, which includes address signals devices 30 of the memory module 10." (e.g., bank address signals, row address signals, column 4 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) address signals, gated column address strobe signals, chipselect signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B set of input signals (claim 15) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of input signals" is a "set of varying electrical impulse inputs that convey information from one point to another" Specification Support Figures 1A, 1B, 2A, 3A 5:14-21: "The logic element 40 receives a set of input control signals from the computer system. The set of input control signals correspond to a second number of memory devices smaller than the first number of memory devices. The logic element 40 generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices." Proposed Construction "input address signals including at least one row/column address signal, bank address signals, and at least one chip select signal, but not including a command signal" Support Claim 15 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) memory devices coupled to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks; a circuit coupled to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input signals from the computer system, the set of input signals comprising at least one row/column address signal, bank address signals, and at least one chipselect signal, the set of input signals configured to control a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR 5 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) memory devices smaller than the first number of DDR 6:55-7:2: "As schematically illustrated by FIGS. 1A and memory devices and the second number of ranks less than 1B, in certain embodiments, the logic element 40 receives the first number of ranks, the circuit generating a set of a set of input control signals, which includes address output signals in response to the set of input signals, the set signals (e.g., bank address signals, row address signals, of output signals configured to control the first number of column address signals, gated column address strobe DDR memory devices arranged in the first number of signals, chip-select signals) and command signals (e.g., ranks, wherein the circuit further responds to a command refresh, precharge) from the computer system. In response signal and the set of input signals from the computer system to the set of input control signals, the logic element 40 by selecting one or two ranks of the first number of ranks generates a set of output control signals which includes and transmitting the command signal to at least one DDR address signals and command signals. In certain memory device of the selected one or two ranks of the first embodiments, the set of output control signals corresponds number of ranks; and a phase-lock loop device coupled to to a first number of ranks in which the plurality of the printed circuit board, the phase-lock loop device memory devices 30 of the memory module 10 are operatively coupled to the plurality of DDR memory arranged, and the set of input control signals corresponds devices, the logic element, and the register." to a second number of ranks per memory module for 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, which the computer system is configured." in certain embodiments, the logic element 40 receives a set 11:52-57: 11:52-57: "The logic element 40 then receives of input control signals, which includes address signals a set of input control signals corresponding to a single (e.g., bank address signals, row address signals, column rank from the computer system's memory controller, and address signals, gated column address strobe signals, chipgenerates and transmits a set of output control signals select signals) and command signals (e.g., refresh, corresponding to two ranks to the appropriate memory precharge) from the computer system. In response to the set devices 30 of the memory module 10." of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B set of input control signals (claim 28) Proposed Construction Netlist contends that the plain meaning of this phrase is Proposed Construction "input control signals including a row/column address 6 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of input control signals" is a "set of varying electrical impulse inputs that convey information for regulating system operations, including addresses and commands, from one point to another" GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) signal, bank address signals, a chip-select signal, and an input command signal" Support Claim 28 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) dynamic random-access memory (DRAM) devices coupled to the printed circuit board, the plurality of DDR DRAM devices Specification Support having a first number of DDR DRAM devices arranged in a Figures 1A, 1B, 2A, 3A first number of ranks; a circuit coupled to the printed circuit 5:14-21: "The logic element 40 receives a set of input board, the circuit comprising a logic element and a register, control signals from the computer system. The set of input the logic element receiving a set of input control signals control signals correspond to a second number of memory from the computer system, the set of input control signals devices smaller than the first number of memory devices. comprising a row/column address signal, bank address The logic element 40 generates a set of output control signals, a chip-select signal, and an input command signal, signals in response to the set of input control signals. The the set of input control signals configured to control a set of output control signals corresponds to the first second number of DDR DRAM devices arranged in a number of memory devices." second number of ranks, the second number of DDR DRAM devices smaller than the first number of DDR 6:55-7:2: "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives DRAM devices, the second number of ranks smaller than the first number of ranks, the circuit generating a set of a set of input control signals, which includes address output control signals in response to the set of input control signals (e.g., bank address signals, row address signals, signals, the set of output control signals comprising an column address signals, gated column address strobe output command signal, the set of output control signals signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response configured to control the first number of DDR DRAM devices arranged in the first number of ranks, wherein the to the set of input control signals, the logic element 40 circuit further responds to the set of input control signals generates a set of output control signals which includes from the computer system by selecting at least one rank of address signals and command signals. In certain embodiments, the set of output control signals corresponds the first number of ranks and transmitting the set of output 7 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE to a first number of ranks in which the plurality of memory devices 30 of the memory module 10 are arranged, and the set of input control signals corresponds to a second number of ranks per memory module for which the computer system is configured." 11:52-57: 11:52-57: "The logic element 40 then receives a set of input control signals corresponding to a single rank from the computer system's memory controller, and generates and transmits a set of output control signals corresponding to two ranks to the appropriate memory devices 30 of the memory module 10." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) control signals to at least one DDR DRAM device of the selected at least one rank; and a phase-lock loop device coupled to the printed circuit board, the phase-lock loop device operatively coupled to the plurality of DDR DRAM devices, the logic element, and the register. 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives a set of input control signals, which includes address signals (e.g., bank address signals, row address signals, column address signals, gated column address strobe signals, chipselect signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B plurality of input control signals (claim 39) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "plurality of input control signals" is a "plurality of varying electrical impulse inputs that convey information for regulating system operations, including addresses and commands, from one point to another" Specification Support Proposed Construction "input control signals including row address signals, column address signals, bank address signals, command signals, and a second number of chip-select signals less than the first number of chip-select signals" Support Claim 39 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board having a first side and a second side; a plurality of double-data-rate (DDR) memory devices mounted to the 8 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) printed circuit board, each DDR memory device comprising Figures 1A, 1B, 2A, 3A one or more banks, the plurality of DDR memory devices 5:14-21: "The logic element 40 receives a set of input arranged in two or more ranks which are selectable by a control signals from the computer system. The set of input first number of chip-select signals; and at least one control signals correspond to a second number of memory integrated circuit element mounted to the printed circuit devices smaller than the first number of memory devices. board, the at least one integrated circuit element comprising The logic element 40 generates a set of output control a logic element, a register, and a phase-lock loop device signals in response to the set of input control signals. The operationally coupled to the plurality of DDR memory set of output control signals corresponds to the first devices, the logic element, and the register, the at least one number of memory devices." integrated circuit element receiving a plurality of input signals from the computer system, the plurality of input 6:55-7:2: "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives signals comprising row address signals, column address signals, bank address signals, command signals, and a a set of input control signals, which includes address second number of chip-select signals less than the first signals (e.g., bank address signals, row address signals, number of chip-select signals, wherein the logic element column address signals, gated column address strobe receives the bank address signals and at least one command signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response signal of the plurality of input signals, the at least one integrated circuit element generating a plurality of output to the set of input control signals, the logic element 40 signals in response to the plurality of input signals, the generates a set of output control signals which includes plurality of output signals comprising row address signals, address signals and command signals. In certain embodiments, the set of output control signals corresponds column address signals, bank address signals, command signals, and the first number of chip-select signals, the at to a first number of ranks in which the plurality of least one integrated circuit element further responsive to the memory devices 30 of the memory module 10 are plurality of input signals by selecting at least one rank of arranged, and the set of input control signals corresponds the two or more ranks and transmitting the plurality of to a second number of ranks per memory module for output signals to at least one DDR memory device of the which the computer system is configured." selected at least one rank. 11:52-57: 11:52-57: "The logic element 40 then receives 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, a set of input control signals corresponding to a single in certain embodiments, the logic element 40 receives a set rank from the computer system's memory controller, and of input control signals, which includes address signals generates and transmits a set of output control signals (e.g., bank address signals, row address signals, column corresponding to two ranks to the appropriate memory 9 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE devices 30 of the memory module 10." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) address signals, gated column address strobe signals, chipselect signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B set of output control signals (claim 1) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of output control signals" is a "set of varying electrical impulse outputs that convey information for regulating system operations, including addresses and commands, from one point to another" Specification Support Figures 1A, 1B, 2A, 3A 5:14-21: "The logic element 40 receives a set of input control signals from the computer system. The set of input control signals correspond to a second number of memory devices smaller than the first number of memory devices. The logic element 40 generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first Proposed Construction "output control signals, not including a second command signal" Support Claim 1 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks; a circuit mounted to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system, the set of input control signals comprising at least one row/column address signal, bank address signals, and at least one chip-select signal, the set of input control signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of 10 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) DDR memory devices and the second number of ranks less number of memory devices." than the first number of ranks, the circuit generating a set of 6:55-7:2: "As schematically illustrated by FIGS. 1A and output control signals in response to the set of input control 1B, in certain embodiments, the logic element 40 receives signals, the set of output control signals corresponding to a set of input control signals, which includes address the first number of DDR memory devices arranged in the signals (e.g., bank address signals, row address signals, first number of ranks, wherein the circuit further responds column address signals, gated column address strobe to a first command signal and the set of input control signals, chip-select signals) and command signals (e.g., signals from the computer system by generating and refresh, precharge) from the computer system. In response transmitting a second command signal and the set of output to the set of input control signals, the logic element 40 control signals to the plurality of memory devices, the first generates a set of output control signals which includes command signal and the set of input control signals address signals and command signals. In certain corresponding to the second number of ranks and the embodiments, the set of output control signals corresponds second command signal and the set of output control to a first number of ranks in which the plurality of signals corresponding to the first number of ranks; and a memory devices 30 of the memory module 10 are phase-lock loop device mounted to the printed circuit arranged, and the set of input control signals corresponds board, the phase-lock loop device operatively coupled to to a second number of ranks per memory module for the plurality of DDR memory devices, the logic element, which the computer system is configured." and the register." 11:52-57: 11:52-57: "The logic element 40 then receives 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, a set of input control signals corresponding to a single in certain embodiments, the logic element 40 receives a set rank from the computer system's memory controller, and of input control signals, which includes address signals generates and transmits a set of output control signals (e.g., bank address signals, row address signals, column corresponding to two ranks to the appropriate memory address signals, gated column address strobe signals, chipdevices 30 of the memory module 10." select signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B 11 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS set of output signals (claim 15) NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of output signals" is a "set of varying electrical impulse outputs that convey information from one point to another" Specification Support Figures 1A, 1B, 2A, 3A 5:14-21: "The logic element 40 receives a set of input control signals from the computer system. The set of input control signals correspond to a second number of memory devices smaller than the first number of memory devices. The logic element 40 generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices." 6:55-7:2: "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives a set of input control signals, which includes address signals (e.g., bank address signals, row address signals, column address signals, gated column address strobe signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Proposed Construction "output address signals, not including a command signal" Support Claim 15 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) memory devices coupled to the printed circuit board, the plurality of DDR memory devices having a first number of DDR memory devices arranged in a first number of ranks; a circuit coupled to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input signals from the computer system, the set of input signals comprising at least one row/column address signal, bank address signals, and at least one chipselect signal, the set of input signals configured to control a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit generating a set of output signals in response to the set of input signals, the set of output signals configured to control the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit further responds to a command signal and the set of input signals from the computer system by selecting one or two ranks of the first number of ranks and transmitting the command signal to at least one DDR memory device of the selected one or two ranks of the first 12 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) address signals and command signals. In certain number of ranks; and a phase-lock loop device coupled to embodiments, the set of output control signals corresponds the printed circuit board, the phase-lock loop device to a first number of ranks in which the plurality of operatively coupled to the plurality of DDR memory memory devices 30 of the memory module 10 are devices, the logic element, and the register." arranged, and the set of input control signals corresponds 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, to a second number of ranks per memory module for in certain embodiments, the logic element 40 receives a set which the computer system is configured." of input control signals, which includes address signals 11:52-57: 11:52-57: "The logic element 40 then receives (e.g., bank address signals, row address signals, column a set of input control signals corresponding to a single address signals, gated column address strobe signals, chiprank from the computer system's memory controller, and select signals) and command signals (e.g., refresh, generates and transmits a set of output control signals precharge) from the computer system. In response to the set corresponding to two ranks to the appropriate memory of input control signals, the logic element 40 generates a set devices 30 of the memory module 10." of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B set of output control signals (claim 28) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "set of output control signals" is a "set of varying electrical impulse outputs that convey information for regulating system operations, including addresses and commands, from one point to another" Specification Support Proposed Construction "output control signals including an output command signal" Support Claim 28 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board; a plurality of double-data-rate (DDR) dynamic random-access memory (DRAM) devices coupled to the printed circuit board, the plurality of DDR DRAM devices having a first number of DDR DRAM devices arranged in a first number of ranks; a circuit coupled to the printed circuit 13 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) board, the circuit comprising a logic element and a register, Figures 1A, 1B, 2A, 3A the logic element receiving a set of input control signals 5:14-21: "The logic element 40 receives a set of input from the computer system, the set of input control signals control signals from the computer system. The set of input comprising a row/column address signal, bank address control signals correspond to a second number of memory signals, a chip-select signal, and an input command signal, devices smaller than the first number of memory devices. the set of input control signals configured to control a The logic element 40 generates a set of output control second number of DDR DRAM devices arranged in a signals in response to the set of input control signals. The second number of ranks, the second number of DDR set of output control signals corresponds to the first DRAM devices smaller than the first number of DDR number of memory devices." DRAM devices, the second number of ranks smaller than the first number of ranks, the circuit generating a set of 6:55-7:2: "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives output control signals in response to the set of input control signals, the set of output control signals comprising an a set of input control signals, which includes address output command signal, the set of output control signals signals (e.g., bank address signals, row address signals, configured to control the first number of DDR DRAM column address signals, gated column address strobe devices arranged in the first number of ranks, wherein the signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response circuit further responds to the set of input control signals from the computer system by selecting at least one rank of to the set of input control signals, the logic element 40 the first number of ranks and transmitting the set of output generates a set of output control signals which includes control signals to at least one DDR DRAM device of the address signals and command signals. In certain embodiments, the set of output control signals corresponds selected at least one rank; and a phase-lock loop device coupled to the printed circuit board, the phase-lock loop to a first number of ranks in which the plurality of device operatively coupled to the plurality of DDR DRAM memory devices 30 of the memory module 10 are devices, the logic element, and the register. arranged, and the set of input control signals corresponds to a second number of ranks per memory module for 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, which the computer system is configured." in certain embodiments, the logic element 40 receives a set of input control signals, which includes address signals 11:52-57: 11:52-57: "The logic element 40 then receives (e.g., bank address signals, row address signals, column a set of input control signals corresponding to a single address signals, gated column address strobe signals, chiprank from the computer system's memory controller, and select signals) and command signals (e.g., refresh, generates and transmits a set of output control signals precharge) from the computer system. In response to the set corresponding to two ranks to the appropriate memory 14 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE devices 30 of the memory module 10." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B plurality of output signals (claim 39) Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes the following: "plurality of output control signals" is a "plurality of varying electrical impulse outputs that convey information from one point to another" Specification Support Figures 1A, 1B, 2A, 3A 5:14-21: "The logic element 40 receives a set of input control signals from the computer system. The set of input control signals correspond to a second number of memory devices smaller than the first number of memory devices. The logic element 40 generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices." 6:55-7:2: "As schematically illustrated by FIGS. 1A and 1B, in certain embodiments, the logic element 40 receives a set of input control signals, which includes address Proposed Construction "output control signals including row address signals, column address signals, bank address signals, command signals, and the first number of chip-select signals" Support Claim 39 "A memory module connectable to a computer system, the memory module comprising: a printed circuit board having a first side and a second side; a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, each DDR memory device comprising one or more banks, the plurality of DDR memory devices arranged in two or more ranks which are selectable by a first number of chip-select signals; and at least one integrated circuit element mounted to the printed circuit board, the at least one integrated circuit element comprising a logic element, a register, and a phase-lock loop device operationally coupled to the plurality of DDR memory devices, the logic element, and the register, the at least one integrated circuit element receiving a plurality of input signals from the computer system, the plurality of input signals comprising row address signals, column address signals, bank address signals, command signals, and a 15 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) second number of chip-select signals less than the first signals (e.g., bank address signals, row address signals, number of chip-select signals, wherein the logic element column address signals, gated column address strobe receives the bank address signals and at least one command signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response signal of the plurality of input signals, the at least one integrated circuit element generating a plurality of output to the set of input control signals, the logic element 40 signals in response to the plurality of input signals, the generates a set of output control signals which includes plurality of output signals comprising row address signals, address signals and command signals. In certain embodiments, the set of output control signals corresponds column address signals, bank address signals, command signals, and the first number of chip-select signals, the at to a first number of ranks in which the plurality of least one integrated circuit element further responsive to the memory devices 30 of the memory module 10 are plurality of input signals by selecting at least one rank of arranged, and the set of input control signals corresponds the two or more ranks and transmitting the plurality of to a second number of ranks per memory module for output signals to at least one DDR memory device of the which the computer system is configured." selected at least one rank. 11:52-57: 11:52-57: "The logic element 40 then receives 6:55-64 "As schematically illustrated by FIGS. 1A and 1B, a set of input control signals corresponding to a single in certain embodiments, the logic element 40 receives a set rank from the computer system's memory controller, and of input control signals, which includes address signals generates and transmits a set of output control signals (e.g., bank address signals, row address signals, column corresponding to two ranks to the appropriate memory address signals, gated column address strobe signals, chipdevices 30 of the memory module 10." select signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals." See Figures 1A, 1B, 2A, 2B, 3A, and 3B operatively coupled / operationally coupled Proposed Construction "functionally cooperating with" Proposed Construction "directly or indirectly electrically connected to provide for operation signaling" 16 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE Specification Support 5:28-31: "In response to signals received from the computer system, the phase-lock loop device transmits clock signals to the plurality of memory devices 30, the logic element 40, and the register 60." Extrinsic Support Innova /Pure Water, Inc. v. Safari Water Filtration Systems, Inc., 381 F.3d 1111, 1118 (Fed. Cir. 2004) ("'[Operatively connected]' is a general descriptive frequently used in patent drafting to reflect a functional relationship between claimed components"); Manual of Patent Examining Procedure (8th ed., Rev. July 2008) at 2173.05(g). The New Oxford American Dictionary, 1193 (2nd Ed., 2005) (see Exh. B, "operative") Operative: adj. (definition 1). 1. functioning; having effect: the transmitter is operative | the mining ban would remain operative. Support 5:22-45 "In certain embodiments, as schematically illustrated in FIG. 1A, the memory module 10 further comprises a phase-lock loop device 50 coupled to the printed circuit board 20 and a register 60 coupled to the printed circuit board 20. In certain embodiments, the phaselock loop device 50 and the register 60 are each mounted on the printed circuit board 20. In response to signals received from the computer system, the phase-lock loop device 50 transmits clock signals to the plurality of memory devices 30, the logic element 40, and the register 60. The register 60 receives and buffers a plurality of control signals, including address signals (e.g., bank address signals, row address signals, column address signals, gated column address strobe signals, chip-select signals), and transmits corresponding signals to the appropriate memory devices 30. In certain embodiments, the register 60 comprises a plurality of register devices. While the phaselock loop device 50, the register 60, and the logic element 40 are described herein in certain embodiments as being separate components, in certain other embodiments, two or more of the phase-lock loop device 50, the register 60, and the logic element 40 are portions of a single component. Persons skilled in the art are able to select a phase-lock loop device 50 and a register 60 compatible with embodiments described herein." See Figures 1A and 1B GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) 17 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS Claim 45 NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE Netlist contends that the plain meaning of this claim is apparent and, therefore, no construction by the Court is required. Netlist contends that claim 45 is not indefinite and fully complies with the requirements of 35 U.S.C. 112, second paragraph. As stated above, claim 39 is not limited to the inclusion of a register, phase lock loop, and logic element within a single component. Thus, claim 45 adds further limitations to those recited in claim 39. Support in Specification 5:40-42: "[I]n certain other embodiments, two or more of the phase-lock loop device 50, the register 60, and the logic element 40 are portions of a single component." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Indefinite: Claim 45 is indefinite because it can't be construed in view of claim 39, which requires that all three functional parts be included with a single integrated circuit. As a result, claim 45 is indefinite because it tries to remove one functional part ("wherein two or more...") or claims nothing further than what is claimed in claim 39. Support 5:37-55 "While the phase-lock loop device 50, the register 60, and the logic element 40 are described herein in certain embodiments as being separate components, in certain other embodiments, two or more of the phase-lock loop device 50, the register 60, and the logic element 40 are portions of a single component. Persons skilled in the art are able to select a phase-lock loop device 50 and a register 60 compatible with embodiments described herein. In certain embodiments, the memory module 10 further comprises electrical components which are electrically coupled to one another and are surface-mounted or embedded on the printed circuit board 20. These electrical components can include, but are not limited to, electrical conduits, resistors, capacitors, inductors, and transistors. In certain embodiments, at least some of these electrical components are discrete, while in other certain embodiments, at least some of these electrical components are constituents of one or more integrated circuits." 18 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS spaced from NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. However, if the Court believes that construction is required, Netlist proposes: "positioned at a distance from" Specification Support Figures 1A-B, 2A, 3A 6:64-7:19: "In certain embodiments, the set of output control signals corresponds to a first number of ranks in which the plurality of memory devices 30 of the memory module 10 are arranged, and the set of input control signals corresponds to a second number of ranks per memory module for which the computer system is configured. The second number of ranks in certain embodiments is smaller than the first number of ranks. For example, in the exemplary embodiment as schematically illustrated by FIG. 1A, the first number of ranks is four while the second number of ranks is two. In the exemplary embodiment of FIG. 1B, the first number of ranks is two while the second number of ranks is one. Thus, in certain embodiments, even though the memory module 10 actually has the first number of ranks of memory devices 30, the memory module 10 simulates a virtual memory module by operating as having the second number of ranks of memory devices 30. In certain embodiments, the memory module 10 simulates a virtual memory module GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Indefinite: The specification provides no instruction regarding what "spaced from" means; there is no specificity as to the spacing required Support Although Figures 11A and 11B visually illustrate the DDR memory modules on the printed circuit board, the figures are not drawn to scale. Therefore, there is no support or definition provided for the spacing required. 19 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE when the number of memory devices 30 of the memory module 10 is larger than the number of memory devices 30 per memory module for which the computer system is configured to utilize." 19:53-58: "FIG. 2A schematically illustrates an exemplary memory module 10 which doubles the rank density in accordance with certain embodiments described herein. The memory module 10 has a first memory capacity. The memory module 10 comprises a plurality of substantially identical memory devices 30 configured as a first rank 32 and a second rank 34." 22:62-63: "ranks 32, 34, 36, and 38 of memory devices 30." 23:15: "the four ranks 32, 34, 36, 38 is active." 23:25: "four ranks 32, 34, 36, 38." Extrinsic Support The New Oxford American Dictionary, 1624 (2nd Ed., 2005) (see Exh. B, "space") Space: v. (definition 1). 1. [trans.] (usu. be spaced) position (two or more items) at a distance from one another: the houses are spaced out. in a direction along the first side/in a direction along the second side Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is Indefinite: The specification provides no instruction regarding the placement of ranks "in a direction" GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) 20 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE required. Moreover, Netlist disagrees with Google's implicit assertion that claim 11 requires placement of ranks in a direction. Support in Specification FIGS. 11A and 11B 28:28-32: "FIGS. 11A and 11B schematically illustrate a first side 362 and a second side 364, respectively, of such a memory module 300 with eighteen 64 Mx4-bit, DDR-1 SDRAM FBGA memory devices on each side of a 184pin glass-epoxy printed circuit board (PCB) 360." at a time Proposed Construction Netlist contends that the plain meaning of this phrase is apparent and, therefore, no construction by the Court is required. Support in Specification Table 1 (Column 8) 8:44-63: "The `Command' column of Table 1 represents the various commands that a memory device (e.g., a DRAM device) can execute, examples of which include, but are not limited to, activation, read, write, precharge, and refresh. In certain embodiments, the command signal is passed through to the selected rank only (e.g., state 4 of Table 1). In such embodiments, the command signal (e.g., GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) Support Although Figures 11A and 11B visually illustrate the DDR memory modules on the printed circuit board, they are not drawn to scale. Therefore, there is no support or definition provided for the placement of ranks "in a direction." 28:28-32 "11A and 11B schematically illustrate a first side 362 and a second side 364, respectively, of such a memory module 300 with eighteen 64 Mx4-bit, DDR-1 SDRAM FBGA memory devices on each side of a 184-pin glassepoxy printed circuit board (PCB) 360." See Figures 11A and 11B Proposed Construction "at the same time" Support Claim 18 "The memory module of claim 15, wherein the command signal is transmitted to two ranks of the first number of ranks at a time." 8:44-64 "The "Command" column of Table 1 represents the various commands that a memory device (e.g., a DRAM device) can execute, examples of which include, but are not limited to, activation, read, write, precharge, and refresh. In certain embodiments, the command signal is passed through to the selected rank only (e.g., state 4 of Table 1). In such embodiments, the command signal (e.g., read) is 21 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA] EXHIBIT B, Netlist v. Google, Patent Local Rule 4-3(b) DISPUTED CLAIM TERMS NETLIST'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE read) is sent to only one memory device or the other memory device so that data is supplied from one memory device at a time. In other embodiments, the command signal is passed through to both associated ranks (e.g., state 6 of Table 1). In such embodiments, the command signal (e.g., refresh) is sent to both memory devices to ensure that the memory content of the memory devices remains valid over time. Certain embodiments utilize a logic table such as that of Table 1 to simulate a single memory device from two memory devices by selecting two ranks concurrently." GOOGLE'S PROPOSED CONSTRUCTIONS AND SUPPORTING EVIDENCE (All citations are to the `912 Patent unless otherwise noted.) sent to only one memory device or the other memory device so that data is supplied from one memory device at a time. In other embodiments, the command signal is passed through to both associated ranks (e.g., state 6 of Table 1). In such embodiments, the command signal (e.g., refresh) is sent to both memory devices to ensure that the memory content of the memory devices remains valid over time. Certain embodiments utilize a logic table such as that of Table 1 to simulate a single memory device from two memory devices by selecting two ranks concurrently. See Figures 1A and 1B See Tables 1 and 2 22 JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT UNDER P.L.R. 4-3 Case No. CV-09-05718 SBA [Related to Case No. CV-08-04144 SBA]

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