STC.UNM v. Intel Corporation

Filing 176

DECLARATION re 175 Response in Opposition to Motion,, of Brian L. Ferrall in Support of Intel's Opposition to STC's Motion to Strike and Dismiss Intel's Invalidity Affirmative Defense and Counterclaim by Intel Corporation (Attachments: # 1 Exhibit A, # 2 Exhibit B, # 3 Exhibit C, # 4 Exhibit D, # 5 Exhibit E, # 6 Exhibit F, # 7 Exhibit G, # 8 Exhibit H, # 9 Exhibit I, # 10 Exhibit J, # 11 Exhibit K - part 1, # 12 Exhibit K - part 2, # 13 Exhibit L)(Atkinson, Clifford)

Exhibit 1
STC.UNM v. Intel
Invalidity Claim Chart Comparing '998 Patent to Jinbo '222
The following asserted claims of STC.UNM’s U.S. Pat. No. 6,042,998 are invalidated pursuant to 35 U.S.C. § 102 and/or § 103, alone or in combination with other
references, by the prior art reference Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al., entitled “Pattern Formation Method,” with publication date
March 5, 1992 (“Jinbo '222”). These preliminary invalidity contentions are based on information currently known to Intel, and, as a result, apply interpretations
apparently or potentially adopted by STC.UNM. Intel reserves the right to amend its preliminary invalidity contentions in light of developments in the case such as
production of discovery, identification of additional prior art, and issuance of an order following any Claim Construction Hearing, as stated in the Scheduling Order
(Dkt. 47, dated March 2, 2011).

Asserted Claims of '998 Patent
6. A method for obtaining a pattern wherein the Fourier
transform of said pattern contains high spatial frequencies
by combining nonlinear functions of intensity of at least
two exposures combined with at least one nonlinear
processing step intermediate between the two exposures to
form three dimensional patterns comprising the steps of:

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
See, e.g., Jinbo '222 (translation), fig.1:

EXHIBIT G
Ex. 1: Page 1

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.”
See, e.g., Jinbo '222 (translation), at 7:
“As is clear from the aforementioned explanation, by means of the pattern formation method of the
present invention, a first resist pattern is formed once on a substrate, after which the next resist
pattern can be formed in the region between this first resist pattern on the substrate; therefore, a
fine resist pattern that exceeds the resolution limit (is less than the resolution limit) of the
projection exposure device can be formed.”
The phrase “the Fourier transform of said pattern contains high spatial frequencies” is an inherent

Ex. 1: Page 2

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
result of the nonlinear processing step. Also, Admitted Prior Art in the '998 patent itself, Brueck
'835, Waldo '094, Ziger, Gwozdz, and Elliott1 each discloses nonlinear processing, e.g., as
explained in “Invalidity Claim Chart Comparing '998 Patent to AAPA, Brueck '835, Waldo '094,
Ziger, Gwozdz, and Elliott,” served concurrently herewith.

coating a substrate with a first mask material and a first
photoresist layer;
exposing said first photoresist layer with a first exposure
developing said photoresist to form a first pattern in said
first photoresist layer, said first pattern containing spatial
frequencies greater than those in a two dimensional optical
intensity image imposed onto said photoresist layer in said
first exposure as a result of a nonlinear response of said
first photoresist layer;

See, e.g., Jinbo '222 (translation), at 1:
“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”
See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid

1

U.S. Patent No. 5,415,835 to Brueck et al. (“Brueck '835”), U.S. Patent No. 4,891,094 to Waldo III (“Waldo '094”), David H. Ziger, et al., Generalized Approach
Toward Modeling Resist Performance, ALCHE JOURNAL, Vol. 37, No. 12, Dec. 1991, at 1863-74 (“Ziger”), Peter S. Gwozdz, Positive Versus Negative: A Photoresist
Analysis, SEMICONDUCTOR LITHOGRAPHY VI, SPIE Vol. 275, 1981 (“Gwozdz”), and/or David J. Elliott, INTEGRATED CIRCUIT FABRICATION TECHNOLOGY, 2d ed., 1989,
at 85-106 and 326 (“Elliott”).

Ex. 1: Page 3

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
used in the subsequent development of said second resist;
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), fig.1:

Ex. 1: Page 4

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
The phrase “containing spatial frequencies greater than those in a two dimensional optical intensity
image imposed onto said photoresist layer . . . as a result of a nonlinear response of said
[photoresist layer]” is inherently disclosed in the above-cited disclosure of photoresist. Also,
Admitted Prior Art in the '998 patent itself, Brueck '835, Waldo '094, Ziger, Gwozdz, and Elliott
each discloses the nonlinear response of photoresist, e.g., as explained in “Invalidity Claim Chart
Comparing '998 Patent to AAPA, Brueck '835, Waldo '094, Ziger, Gwozdz, and Elliott,” served
concurrently herewith.

Ex. 1: Page 5

Asserted Claims of '998 Patent
transferring said first pattern into said first mask material,
said first mask material comprising at least one of
SiO.sub.2, Si.sub.3 N.sub.4, a metal, a polysilicon and a
polymer;

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
See, e.g., Zdebel '002,2 figs.3 & 4A:

See, e.g., Zdebel '002, C7:20 to C8:22:
“Two layers 84, 86 are conveniently deposited on surface 69 using low pressure chemical vapor
deposition (LPCVD). First layer 84 is a layer of polycrystalline semiconductor, preferably silicon
having a thickness conveniently of about 385 nanometers. Larger or smaller thicknesses may be
used for layer 84 according to relationships with other layers which will be subsequently explained.
Second layer 86 is conveniently a layer of silicon nitride or a sandwich of oxide plus nitride or a
layer of other oxidation resistant material having a thickness of, for example, about 70-120
nanometers. Poly silicon layer 84 will be used to form poly silicon base contact regions 84 of FIG.
2. Where an NPN transistor is being formed, layer 84 is doped by ion implantation of, for example,
boron. The doping may be performed during or anytime after deposition of layer 84, but is
conveniently performed after deposition of layers 84 and 86 through nitride layer 86 and before
deposition of layers 88 or 90. Poly silicon layer 84 is conveniently doped with singly ionized boron
at an energy of about 70 KeV to a dose of about 1.times.10.sup.16 cm.sup.-2, although other
2

U.S. Patent No. 5,067,002 to Zdebel et al., entitled “Integrated Circuit Structures Having Polycrystalline Electrode Contacts,” issued on Nov. 19, 1991 (“Zdebel
'002”).

Ex. 1: Page 6

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
doping levels may also be used depending on the desired device and circuit characteristics. The
implantation is preferably arranged so that the relatively high dose of boron is located near the
upper surface of polycrystalline silicon layer 84, just below silicon nitride 86.
After the boron implantation, two further layers 88, 90 are deposited, for example by LPCVD, over
silicon nitride layer 86. Layer 88 is desirably an undoped layer of polycrystalline silicon having a
thickness conveniently of about 180 nanometers. Larger or smaller thicknesses may be used for
layer 88, taking into account the thickness of other layers, as will be subsequently explained. Layer
90 is formed overlying poly layer 88. Layer 90 conveniently prevents contamination of poly layer
88 and serves as a hard mask for subsequent lithographic patterning of the underlying layers. Layer
90 may be of any material suitable for such purposes. Layer 90 is conveniently of silicon oxide
having a thickness of about 20-40 nanometers.
Processing of the structure continues with the application of layer 92 of photoresist overlying oxide
layer 90 as shown schematically in FIG. 4A. The photoresist is patterned using master mask 94,
represented by the shaded region in FIG. 4B, containing images 95-99 for locating various device
regions. Master mask 94 provides self-alignment of the critical device areas, for example in the
case of the vertical NPN transistor, the collector contact, the base contact or contacts, the emitter
contact, and the emitter-base active region. In accordance with one embodiment of the invention,
master mask 94 defines the master electrode area which includes emitter contact opening 95,
collector contact opening 96, and base contact openings 97, 98 located within perimeter 9 and
surrounded by external region 99. Region 99 identifies the region, outside perimeter 9 of master
mask 94. Openings or windows 95-98 located within perimeters 5-8 respectively are used in the
subsequent process to form the "footprints" of the device terminals, and in the case of the vertical
bipolar device, the active emitter-base region. Perimeter 5, although referred to generally herein as
the emitter opening or emitter contact opening, is used in conjunction with epitaxial island 82
formed within field oxide 71 to locate both the base and emitter of the device as well as the emitter
contact. Variations and further embodiments, in addition to the basic NPN transistor, are discussed
later. Base contact openings 97, 98 are located within perimeters 7, 8 respectively. Collector
contact opening 96 is located within perimeter 6.”

Ex. 1: Page 7

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
See, e.g., Cuthbert '076,3 figs.2 & 3:

See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
3

U.S. Patent No. 5,264,076 to Cuthbert et al., entitled “Integrated Circuit Process Using a ‘Hard Mask’,” issued on Nov. 23, 1993, filed on Dec. 17, 1992 (“Cuthbert
'076”).

Ex. 1: Page 8

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”
See, e.g., Jinbo '222 (translation), at 1:
“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”
See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid
used in the subsequent development of said second resist;

Ex. 1: Page 9

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”

coating said substrate with a second photoresist;

See, e.g., Jinbo '222 (translation), at 1:

exposing said second photoresist with a second exposure

“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”

developing said second photoresist layer to form a second
pattern in said second photoresist layer, said second pattern
containing spatial frequencies greater than those in a two
dimensional optical intensity image imposed onto said
photoresist layer in said second exposure as a result of a
nonlinear response of said second photoresist layer;

See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of

Ex. 1: Page 10

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid
used in the subsequent development of said second resist;
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”

Ex. 1: Page 11

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
See, e.g., Jinbo '222 (translation), fig.1:

The phrase “containing spatial frequencies greater than those in a two dimensional optical intensity
image imposed onto said photoresist layer . . . as a result of a nonlinear response of said
[photoresist layer]” is inherently disclosed in the above-cited disclosure of photoresist. Also,
Admitted Prior Art in the '998 patent itself, Brueck '835, Waldo '094, Ziger, Gwozdz, and Elliott
each discloses the nonlinear response of photoresist, e.g., as explained in “Invalidity Claim Chart
Comparing '998 Patent to AAPA, Brueck '835, Waldo '094, Ziger, Gwozdz, and Elliott,” served
concurrently herewith.
transferring said first pattern and said second pattern into
said substrate using a combined mask including parts of
said first mask layer and said second photoresist;

See, e.g., Jinbo '222 (translation), at 1:
“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step

Ex. 1: Page 12

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”
See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid
used in the subsequent development of said second resist;
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and

Ex. 1: Page 13

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”
See, e.g., Jinbo '222 (translation), fig.1:

See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily

Ex. 1: Page 14

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”

removing said first mask material and said second
photoresist.

See, e.g., Zdebel '002, C9:50-57:
“Subsequently, photoresist 100 is removed with, for example, organic photoresist stripper, oxygen
plasma, or other suitable means. Thereafter the remainder of oxide layer 90 is removed by, for
example, dip etching in a dilute hydrofluoric acid etchant solution. Other suitable etching or
removal techniques known in the art may also be used.”
See, e.g., Cuthbert '076, C3:26 to C4:2:
“The photoresist is now removed. Conventional techniques may be used. The underlying
polysilicon of layer is now etched using the SOG as an etch mask. After the polysilicon has been
etched, the SOG is removed using, for example, an HF solution. Such a removal process may be
used because of the relative etch rates of SOG to thermal oxide. Depending upon the precise
technique used to cure the SOG, etch rate differentials of 15:1 or greater may be obtained. The high
etch rates differential makes it possible to remove the SOG without a significant attack on either
the gate (thermal) or field oxides. The resulting structure is depicted in FIG. 4.”
See, e.g., Cuthbert '076, fig.4:

Ex. 1: Page 15

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Jinbo '222 (translation), fig.1:

7. The method of claim 6 wherein said transferring step
includes at least one of etching, deposition and-lift off, and
damascene.

See, e.g., Zdebel '002, C9:50-57:
“Subsequently, photoresist 100 is removed with, for example, organic photoresist stripper, oxygen
plasma, or other suitable means. Thereafter the remainder of oxide layer 90 is removed by, for
example, dip etching in a dilute hydrofluoric acid etchant solution. Other suitable etching or

Ex. 1: Page 16

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
removal techniques known in the art may also be used.”
See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”
See, e.g., Cuthbert '076, C3:26 to C4:2:
“The photoresist is now removed. Conventional techniques may be used. The underlying
polysilicon of layer is now etched using the SOG as an etch mask. After the polysilicon has been
etched, the SOG is removed using, for example, an HF solution. Such a removal process may be
used because of the relative etch rates of SOG to thermal oxide. Depending upon the precise
technique used to cure the SOG, etch rate differentials of 15:1 or greater may be obtained. The high
etch rates differential makes it possible to remove the SOG without a significant attack on either
the gate (thermal) or field oxides. The resulting structure is depicted in FIG. 4.”
See, e.g., Cuthbert '076, fig.4:

Ex. 1: Page 17

Asserted Claims of '998 Patent

8. A method for increasing spatial frequency content of
lithographic patterns comprising the steps of:

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.”
See, e.g., Jinbo '222 (translation), at 7:
“As is clear from the aforementioned explanation, by means of the pattern formation method of the
present invention, a first resist pattern is formed once on a substrate, after which the next resist
pattern can be formed in the region between this first resist pattern on the substrate; therefore, a
fine resist pattern that exceeds the resolution limit (is less than the resolution limit) of the
projection exposure device can be formed.”
See, e.g., Jinbo '222 (translation), fig.1:

Ex. 1: Page 18

Asserted Claims of '998 Patent

depositing a material;

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., fig.1:

depositing a photoresist on said material;
exposing a periodic image in said photoresist, said periodic
image having a pitch p.sub.min and a linewidth less than
p.sub.min /2;
developing said periodic image to form a periodic pattern
in said photoresist;

Ex. 1: Page 19

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Jinbo '222 (translation), at 1:
“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”
See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.

Ex. 1: Page 20

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid
used in the subsequent development of said second resist;
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), at 5-6:
“Next, by a spin-coating method, a second resist 15 – in this case, the TSMR-365iR used as the
first resist – was applied with a film thickness of 1.0 μm to substrate 11 having the first resist
pattern 13b which had undergone insolubilization processing (Figure 1(D).
As described above, first resist pattern 13b which has undergone insolubilization
processing is insoluble with respect to the solvent of second resist 15, so when first resist pattern
13b is covered by second resist pattern 15 the pattern of the first resist pattern itself does not break
down, nor does it intermix with the second resist.
Next, second resist pattern 15 was baked under the same baking conditions as for the first

Ex. 1: Page 21

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
resist.
Next, substrate 11 having this baked second resist was placed on a wafer stage in the
previously used projection exposure device, after which substrate 11 was aligned with respect to a
mask installed in this projection exposure device. Next, the wafer stage was shifted 0.3 μm in the X
direction – in other words, the wafer stage was shifted such that the line potions of the mask were
projected on the space portions of first resist pattern 13b, which had undergone insolubilization
processing – and then second resist 15 was exposed with an exposure amount of 300 mJ/cm2.
Next, the exposed second resist was developed under the same developing conditions as
for the first resist, obtaining second resist pattern 15a (Figure 1(E)). Because first resist pattern 13b
had undergone insolubilization processing as described previously so as to be insoluble with
respect to the NMD-W developer fluid, no pattern breakdown occurred when the second resist
pattern was developed.
After the second resist was developed, a resist pattern 17 comprised of insolubilizationprocessed first resist pattern 13b and second resist pattern 15a was formed on substrate 11 (Figure
1(E)). When this resist pattern 17 was observed with an S-6000 SEM measurement device, it was
found that a pattern for which line portions with a width of 0.3 μm were aligned with a pitch of 0.6
μm – in other words, a 0.3 μm line-and-space pattern – had been resolved.”
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”
See, e.g., Jinbo '222 (translation), at 7:
“As is clear from the aforementioned explanation, by means of the pattern formation method of the
present invention, a first resist pattern is formed once on a substrate, after which the next resist
pattern can be formed in the region between this first resist pattern on the substrate; therefore, a
fine resist pattern that exceeds the resolution limit (is less than the resolution limit) of the

Ex. 1: Page 22

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
projection exposure device can be formed.”

transferring said periodic pattern to said material;

See, e.g., Zdebel '002, figs.3 & 4A:

See, e.g., Zdebel '002, C7:20 to C8:22:
“Two layers 84, 86 are conveniently deposited on surface 69 using low pressure chemical vapor
deposition (LPCVD). First layer 84 is a layer of polycrystalline semiconductor, preferably silicon
having a thickness conveniently of about 385 nanometers. Larger or smaller thicknesses may be
used for layer 84 according to relationships with other layers which will be subsequently explained.
Second layer 86 is conveniently a layer of silicon nitride or a sandwich of oxide plus nitride or a
layer of other oxidation resistant material having a thickness of, for example, about 70-120
nanometers. Poly silicon layer 84 will be used to form poly silicon base contact regions 84 of FIG.
2. Where an NPN transistor is being formed, layer 84 is doped by ion implantation of, for example,
boron. The doping may be performed during or anytime after deposition of layer 84, but is
conveniently performed after deposition of layers 84 and 86 through nitride layer 86 and before
deposition of layers 88 or 90. Poly silicon layer 84 is conveniently doped with singly ionized boron
at an energy of about 70 KeV to a dose of about 1.times.10.sup.16 cm.sup.-2, although other
doping levels may also be used depending on the desired device and circuit characteristics. The

Ex. 1: Page 23

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
implantation is preferably arranged so that the relatively high dose of boron is located near the
upper surface of polycrystalline silicon layer 84, just below silicon nitride 86.
After the boron implantation, two further layers 88, 90 are deposited, for example by LPCVD, over
silicon nitride layer 86. Layer 88 is desirably an undoped layer of polycrystalline silicon having a
thickness conveniently of about 180 nanometers. Larger or smaller thicknesses may be used for
layer 88, taking into account the thickness of other layers, as will be subsequently explained. Layer
90 is formed overlying poly layer 88. Layer 90 conveniently prevents contamination of poly layer
88 and serves as a hard mask for subsequent lithographic patterning of the underlying layers. Layer
90 may be of any material suitable for such purposes. Layer 90 is conveniently of silicon oxide
having a thickness of about 20-40 nanometers.
Processing of the structure continues with the application of layer 92 of photoresist overlying oxide
layer 90 as shown schematically in FIG. 4A. The photoresist is patterned using master mask 94,
represented by the shaded region in FIG. 4B, containing images 95-99 for locating various device
regions. Master mask 94 provides self-alignment of the critical device areas, for example in the
case of the vertical NPN transistor, the collector contact, the base contact or contacts, the emitter
contact, and the emitter-base active region. In accordance with one embodiment of the invention,
master mask 94 defines the master electrode area which includes emitter contact opening 95,
collector contact opening 96, and base contact openings 97, 98 located within perimeter 9 and
surrounded by external region 99. Region 99 identifies the region, outside perimeter 9 of master
mask 94. Openings or windows 95-98 located within perimeters 5-8 respectively are used in the
subsequent process to form the "footprints" of the device terminals, and in the case of the vertical
bipolar device, the active emitter-base region. Perimeter 5, although referred to generally herein as
the emitter opening or emitter contact opening, is used in conjunction with epitaxial island 82
formed within field oxide 71 to locate both the base and emitter of the device as well as the emitter
contact. Variations and further embodiments, in addition to the basic NPN transistor, are discussed
later. Base contact openings 97, 98 are located within perimeters 7, 8 respectively. Collector
contact opening 96 is located within perimeter 6.”
See, e.g., Cuthbert '076, figs.2 & 3:

Ex. 1: Page 24

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.

Ex. 1: Page 25

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”
See, e.g., Jinbo '222 (translation), at 7:
“As is clear from the aforementioned explanation, by means of the pattern formation method of the
present invention, a first resist pattern is formed once on a substrate, after which the next resist
pattern can be formed in the region between this first resist pattern on the substrate; therefore, a
fine resist pattern that exceeds the resolution limit (is less than the resolution limit) of the
projection exposure device can be formed.”
Accordingly, the pattern formation method of the present invention easily manufactures
highly integrated LSIs and the like.”
See, e.g., Jinbo '222 (translation), at 2:
“Projection exposure devices are widely used in the fabrication of semiconductor devices such as
ICs and LSIs.
Conventionally, when a resist pattern is formed using a projection exposure device, a
procedure is typically used in which a substrate such as a silicon wafer is coated with a resist, and
this resist is exposed with the projection exposure device, after which this resist is developed to
obtain the final resist pattern.
...
In other words, these projection exposure devices are capable of patterning on the order of
0.5 μm, and capable of manufacturing a 16 Mbit DRAM or the like.”

depositing a second photoresist layer on said material;

See, e.g., fig.1:

offsetting said periodic pattern by p.sub.min /2;
repeating said exposing, developing and transferring steps,
thereby interpolating new said pattern midway between

Ex. 1: Page 26

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

said pattern.

See, e.g., Jinbo '222 (translation), at 1:
“1. Pattern formation method characterized by: a step wherein a first resist is formed on a substrate
and said first resist is patterned; a step wherein a first resist pattern obtained by the aforementioned
patterning is processed and made insoluble with respect to the solvent used for a second resist that
is subsequently formed on the aforementioned substrate having said first resist pattern and with
respect to the developer fluid used in the subsequent development of said second resist; and a step
wherein said second resist is formed on the aforementioned substrate having said first resist pattern
for which the insolubilization process has been completed, and said second resist is patterned.”
See, e.g., Jinbo '222 (translation), at 3:
“[T]he objective of the present invention is to provide a pattern formation method capable of
forming a resist pattern [with a size] at or less than the resolution limit of the projection exposure
device.

Ex. 1: Page 27

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
Means to solve the problem
To achieve this objective, the pattern formation method of the present invention is
characterized by:
a step wherein a first resist is formed on a substrate and said first resist is patterned;
a step wherein a first resist pattern obtained by the aforementioned patterning is processed
and made insoluble with respect to the solvent for a second resist that is subsequently formed on
the aforementioned substrate having said first resist pattern and with respect to the developer fluid
used in the subsequent development of said second resist;
and a step wherein said second resist is formed on the aforementioned substrate having
said first resist pattern for which the insolubilization process has been completed, and said second
resist is patterned.
With respect to the application of the present invention it is preferable that the
aforementioned insolubilization process be performed by leaving the substrate having the
aforementioned first resist pattern in a plasma containing a fluorine compound gas for which the
alkane hydrogen has been replaced with fluorine.
Furthermore, the substrate referred to herein is an intermediate body or the like of various
kinds of substrates, such as a glass substrate, a silicon substrate, or a GaAs substrate, with an
insulation film, metal film, or thin film and/or similar elements being formed thereon.”
See, e.g., Jinbo '222 (translation), at 5-6:
“Next, by a spin-coating method, a second resist 15 – in this case, the TSMR-365iR used as the
first resist – was applied with a film thickness of 1.0 μm to substrate 11 having the first resist
pattern 13b which had undergone insolubilization processing (Figure 1(D).
As described above, first resist pattern 13b which has undergone insolubilization
processing is insoluble with respect to the solvent of second resist 15, so when first resist pattern
13b is covered by second resist pattern 15 the pattern of the first resist pattern itself does not break
down, nor does it intermix with the second resist.
Next, second resist pattern 15 was baked under the same baking conditions as for the first

Ex. 1: Page 28

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
resist.
Next, substrate 11 having this baked second resist was placed on a wafer stage in the
previously used projection exposure device, after which substrate 11 was aligned with respect to a
mask installed in this projection exposure device. Next, the wafer stage was shifted 0.3 μm in the X
direction – in other words, the wafer stage was shifted such that the line potions of the mask were
projected on the space portions of first resist pattern 13b, which had undergone insolubilization
processing – and then second resist 15 was exposed with an exposure amount of 300 mJ/cm2.
Next, the exposed second resist was developed under the same developing conditions as
for the first resist, obtaining second resist pattern 15a (Figure 1(E)). Because first resist pattern 13b
had undergone insolubilization processing as described previously so as to be insoluble with
respect to the NMD-W developer fluid, no pattern breakdown occurred when the second resist
pattern was developed.
After the second resist was developed, a resist pattern 17 comprised of insolubilizationprocessed first resist pattern 13b and second resist pattern 15a was formed on substrate 11 (Figure
1(E)). When this resist pattern 17 was observed with an S-6000 SEM measurement device, it was
found that a pattern for which line portions with a width of 0.3 μm were aligned with a pitch of 0.6
μm – in other words, a 0.3 μm line-and-space pattern – had been resolved.”
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”
See, e.g., Jinbo '222 (translation), at 7:
“As is clear from the aforementioned explanation, by means of the pattern formation method of the
present invention, a first resist pattern is formed once on a substrate, after which the next resist
pattern can be formed in the region between this first resist pattern on the substrate; therefore, a
fine resist pattern that exceeds the resolution limit (is less than the resolution limit) of the

Ex. 1: Page 29

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
projection exposure device can be formed.”

10. The method of claim 8, wherein said material includes
an SiO.sub.2 overlayer configured to act as a hardmask
during said etching step.

See, e.g., Zdebel '002, figs.3 & 4A:

See, e.g., Zdebel '002, C7:20 to C8:22:
“Two layers 84, 86 are conveniently deposited on surface 69 using low pressure chemical vapor
deposition (LPCVD). First layer 84 is a layer of polycrystalline semiconductor, preferably silicon
having a thickness conveniently of about 385 nanometers. Larger or smaller thicknesses may be
used for layer 84 according to relationships with other layers which will be subsequently explained.
Second layer 86 is conveniently a layer of silicon nitride or a sandwich of oxide plus nitride or a
layer of other oxidation resistant material having a thickness of, for example, about 70-120
nanometers. Poly silicon layer 84 will be used to form poly silicon base contact regions 84 of FIG.
2. Where an NPN transistor is being formed, layer 84 is doped by ion implantation of, for example,
boron. The doping may be performed during or anytime after deposition of layer 84, but is
conveniently performed after deposition of layers 84 and 86 through nitride layer 86 and before
deposition of layers 88 or 90. Poly silicon layer 84 is conveniently doped with singly ionized boron
at an energy of about 70 KeV to a dose of about 1.times.10.sup.16 cm.sup.-2, although other
doping levels may also be used depending on the desired device and circuit characteristics. The

Ex. 1: Page 30

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
implantation is preferably arranged so that the relatively high dose of boron is located near the
upper surface of polycrystalline silicon layer 84, just below silicon nitride 86.
After the boron implantation, two further layers 88, 90 are deposited, for example by LPCVD, over
silicon nitride layer 86. Layer 88 is desirably an undoped layer of polycrystalline silicon having a
thickness conveniently of about 180 nanometers. Larger or smaller thicknesses may be used for
layer 88, taking into account the thickness of other layers, as will be subsequently explained. Layer
90 is formed overlying poly layer 88. Layer 90 conveniently prevents contamination of poly layer
88 and serves as a hard mask for subsequent lithographic patterning of the underlying layers. Layer
90 may be of any material suitable for such purposes. Layer 90 is conveniently of silicon oxide
having a thickness of about 20-40 nanometers.
Processing of the structure continues with the application of layer 92 of photoresist overlying oxide
layer 90 as shown schematically in FIG. 4A. The photoresist is patterned using master mask 94,
represented by the shaded region in FIG. 4B, containing images 95-99 for locating various device
regions. Master mask 94 provides self-alignment of the critical device areas, for example in the
case of the vertical NPN transistor, the collector contact, the base contact or contacts, the emitter
contact, and the emitter-base active region. In accordance with one embodiment of the invention,
master mask 94 defines the master electrode area which includes emitter contact opening 95,
collector contact opening 96, and base contact openings 97, 98 located within perimeter 9 and
surrounded by external region 99. Region 99 identifies the region, outside perimeter 9 of master
mask 94. Openings or windows 95-98 located within perimeters 5-8 respectively are used in the
subsequent process to form the "footprints" of the device terminals, and in the case of the vertical
bipolar device, the active emitter-base region. Perimeter 5, although referred to generally herein as
the emitter opening or emitter contact opening, is used in conjunction with epitaxial island 82
formed within field oxide 71 to locate both the base and emitter of the device as well as the emitter
contact. Variations and further embodiments, in addition to the basic NPN transistor, are discussed
later. Base contact openings 97, 98 are located within perimeters 7, 8 respectively. Collector
contact opening 96 is located within perimeter 6.”
See, e.g., Cuthbert '076, figs.2 & 3:

Ex. 1: Page 31

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.

Ex. 1: Page 32

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”
See, e.g., Jinbo '222 (translation), fig.1:

11. The method of claim 8, wherein said step of depositing
a photoresist includes depositing at least one of a negative
photoresist, a positive photoresist and a positive
photoresist with an image reversal step.

See, e.g., Jinbo '222 (translation), at 7:
“For example, with the aforementioned embodiment, TSMR-365iR was used as the resist, but the
resist used with the present invention is not limited thereto; other resists (regardless of whether it is
a negative resist or positive resist) are acceptable. However, when the insolubilization process is
performed with a gas plasma that includes a fluorine compound gas for which the alkane hydrogen
had been replaced with fluorine gas, it is preferable that the resist be a so-called novolac resist
(both positive and negative resists are acceptable), because the effect of the insolubilization process
can be clearly obtained.”

Ex. 1: Page 33

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
See, e.g., Jinbo '222 (translation), at 7:
“Furthermore, in the aforementioned embodiment, the same resist was used for the first resist and
the second resist, but when necessary they could be different resists.
Furthermore, the present invention could also be applied so as to make the second resist pattern
insoluble with respect to the solvent and developer fluid of a third resist, with the third resist
pattern being formed on [the second resist], if necessary.”
See, e.g., fig.1:

16. The method of claim 8, wherein said step of
developing said periodic pattern includes etching said
pattern into a hardmask.

See, e.g., Zdebel '002, figs.3 & 4A:

Ex. 1: Page 34

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Zdebel '002, C7:20 to C8:22:
“Two layers 84, 86 are conveniently deposited on surface 69 using low pressure chemical vapor
deposition (LPCVD). First layer 84 is a layer of polycrystalline semiconductor, preferably silicon
having a thickness conveniently of about 385 nanometers. Larger or smaller thicknesses may be
used for layer 84 according to relationships with other layers which will be subsequently explained.
Second layer 86 is conveniently a layer of silicon nitride or a sandwich of oxide plus nitride or a
layer of other oxidation resistant material having a thickness of, for example, about 70-120
nanometers. Poly silicon layer 84 will be used to form poly silicon base contact regions 84 of FIG.
2. Where an NPN transistor is being formed, layer 84 is doped by ion implantation of, for example,
boron. The doping may be performed during or anytime after deposition of layer 84, but is
conveniently performed after deposition of layers 84 and 86 through nitride layer 86 and before
deposition of layers 88 or 90. Poly silicon layer 84 is conveniently doped with singly ionized boron
at an energy of about 70 KeV to a dose of about 1.times.10.sup.16 cm.sup.-2, although other
doping levels may also be used depending on the desired device and circuit characteristics. The
implantation is preferably arranged so that the relatively high dose of boron is located near the
upper surface of polycrystalline silicon layer 84, just below silicon nitride 86.
After the boron implantation, two further layers 88, 90 are deposited, for example by LPCVD, over

Ex. 1: Page 35

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
silicon nitride layer 86. Layer 88 is desirably an undoped layer of polycrystalline silicon having a
thickness conveniently of about 180 nanometers. Larger or smaller thicknesses may be used for
layer 88, taking into account the thickness of other layers, as will be subsequently explained. Layer
90 is formed overlying poly layer 88. Layer 90 conveniently prevents contamination of poly layer
88 and serves as a hard mask for subsequent lithographic patterning of the underlying layers. Layer
90 may be of any material suitable for such purposes. Layer 90 is conveniently of silicon oxide
having a thickness of about 20-40 nanometers.
Processing of the structure continues with the application of layer 92 of photoresist overlying oxide
layer 90 as shown schematically in FIG. 4A. The photoresist is patterned using master mask 94,
represented by the shaded region in FIG. 4B, containing images 95-99 for locating various device
regions. Master mask 94 provides self-alignment of the critical device areas, for example in the
case of the vertical NPN transistor, the collector contact, the base contact or contacts, the emitter
contact, and the emitter-base active region. In accordance with one embodiment of the invention,
master mask 94 defines the master electrode area which includes emitter contact opening 95,
collector contact opening 96, and base contact openings 97, 98 located within perimeter 9 and
surrounded by external region 99. Region 99 identifies the region, outside perimeter 9 of master
mask 94. Openings or windows 95-98 located within perimeters 5-8 respectively are used in the
subsequent process to form the "footprints" of the device terminals, and in the case of the vertical
bipolar device, the active emitter-base region. Perimeter 5, although referred to generally herein as
the emitter opening or emitter contact opening, is used in conjunction with epitaxial island 82
formed within field oxide 71 to locate both the base and emitter of the device as well as the emitter
contact. Variations and further embodiments, in addition to the basic NPN transistor, are discussed
later. Base contact openings 97, 98 are located within perimeters 7, 8 respectively. Collector
contact opening 96 is located within perimeter 6.”
See, e.g., Cuthbert '076, figs.2 & 3:

Ex. 1: Page 36

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)

See, e.g., Cuthbert '076, C2:66 to C3:25:
“A layer of spin-on-glass(SOG) 7 and a layer of photoresist 9 are now deposited to form the
structure depicted in FIG. 2. The term "spin-on-glass" is well known to those skilled in the art and
need not be defined. As can be seen, the SOG has a relatively planar surface and has smoothed out
the topography of the underlying substrate. By relatively planar, it is meant that the surface is
locally planar, although the surface may not be planar over the entire substrate surface. The SOG is
put on with conventional techniques. The planarity of the surface depends upon the topography of
the underlying material and the thickness of the SOG layer. Those skilled in the art will readily
select a thickness for the SOG that is sufficient for it to act as an etch mask for the underlying gate.
A thermal treatment or cure is desirably used to densify and flow the SOG. This process step also
reduces the topography of the SOG and reduces variations in the resist layer thickness.
Lithographic techniques are now used to pattern the photoresist. The photoresist is then used as a
mask for the etching of the SOG. The etching desirably produces vertical sidewalls in the SOG.

Ex. 1: Page 37

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
The resulting structure is depicted in FIG. 3. Those skilled in the art will readily select appropriate
etching techniques and fabricate the structure. The pattern has, for example, gate structures of field
effect transistors.”
See, e.g., Jinbo '222 (translation), fig.1:

18. The method of claim 8, wherein said step of depositing
a material includes depositing a material on at least one of
a textured substrate, a quantum structure, a flux pinning
site for high-T.sub.c superconductors, a birefringent
material, a reflective optical coating, a photonic bandgap,
an electronic device, an optical storage media, a magnetic
storage media, an array of field emitters and a Dynamic
Random Access Memory capacitor.

See, e.g., Jinbo '222 (translation), at 2:
“Projection exposure devices are widely used in the fabrication of semiconductor devices such as
ICs and LSIs.
Conventionally, when a resist pattern is formed using a projection exposure device, a
procedure is typically used in which a substrate such as a silicon wafer is coated with a resist, and
this resist is exposed with the projection exposure device, after which this resist is developed to
obtain the final resist pattern.

Ex. 1: Page 38

Asserted Claims of '998 Patent

Japanese Kokai Publication No. HEI 4[1992]-71222 to Jinbo et al.
(translation)
.. .
In other words, these projection exposure devices are capable of patterning on the order of
0.5 μm, and capable of manufacturing a 16 Mbit DRAM or the like.”

20336-1313/LEGAL20529343.1

Ex. 1: Page 39