Mirror Worlds, LLC v. Apple, Inc.

Filing 160

CLAIM CONSTRUCTION RESPONSE BRIEF re: #151 Mirror Worlds' Claim Construction Brief, filed by Apple Inc. (Attachments: #1 Decl. of Stefani C. Smith ISO Apple's Brief, #2 Exhibit A, #3 Exhibit B, #4 Exhibit C, #5 Exhibit D, #6 Exhibit E, #7 Exhibit F, #8 Exhibit G, #9 Exhibit H, #10 Exhibit I, #11 Exhibit J, #12 Exhibit K, #13 Exhibit L)(Smith, Stefani) Modified on 1/11/2010 (mll, ).

Mirror Worlds, LLC v. Apple, Inc.

Doc. 160 Att. 11

Page 1 Not Reported in F.Supp.2d, 2006 WL 3447632 (E.D.Tex.) (Cite as: 2006 WL 3447632 (E.D.Tex.))

Only the Westlaw citation is currently available. United States District Court, E.D. Texas, Marshall Division. MAURICE MITCHELL INNOVATIONS, L.P., Plaintiff v. INTEL CORPORATION, Defendant. No. 2:04-CV-450. Nov. 22, 2006. Franklin Jones, Jr, Jones & Jones, Marshall, TX, Richard L. Schwartz, Whitaker Chalk Swindle & Sawyer, Fort Worth, TX, Andrew Wesley Spangler, Elizabeth L. Derieux, Sidney Calvin Capshaw, III, Brown McCarroll, Thomas John Ward, Jr, Law Office of T. John Ward Jr. PC, Longview, TX, Daniel Rapaport, Wendel Rosen Black & Dean, Oakland, CA, Manny D. Pokotilow, Caesar Rivise Berstein Cohen & Pokotilow, Philadelphia, PA, Otis W. Carroll, Jr, Ireland Carroll & Kelley, Tyler, TX, for Plaintiff. Eric Hugh Findlay, Ramey & Flock, Allen Franklin Gardner, John Frederick Bufe, Michael Edwin Jones, Potter Minton PC, Tyler, TX, Christa M. Anderson, Clement S. Roberts, Robert A. Van Nest, Ryan M. Kent, Keker & Van Nest, San Francisco, CA, for Defendant. MEMORANDUM OPINION AND ORDER LEONARD DAVIS, District Judge. *1 Before the Court is Defendant Intel Corporation's ("Intel") motion for summary judgment as to invalidity under 35 U.S.C. § 112 (Docket No. 104). Having considered the parties' written submissions and oral argument, the Court GRANTS the motion. BACKGROUND

Maurice Mitchell Innovations, L.P. ("Mitchell") filed suit against Intel on December 17, 2004 alleging infringement of Claim 1 of U.S. Patent No. 4,875,154 ("the '154 patent"). In general, the '154 patent discloses what the patent refers to as a "Bimemory Independent CPU (`central processing unit')" microcomputer, also referred to as a "BICPU microcomputer." According to the specification, the BICPU microcomputer is comprised of a known CPU chip with additional circuitry to enable the CPU to interact in a multi BICPU microcomputer system. Each BICPU microcomputer within a system is supplied with an assigned standard memory-mechanically and logically connected to its BICPU's "A" bus circuits. The BICPU microcomputer is also provided with connectors enabling the CPU to be connected to system buses. Col. 7:3-12. In general terms, the specification says that the invention allows a number of BICPU microcomputers to be linked together in a "bimemory independent pattern" using a "standard" set of system buses to mechanically interconnect "B" or "C" bus circuits of any two BICPU microcomputers. Col. 7:12-22. Mitchell claims Intel's products, including inter alia, the ASCI Red super computers, the Pentium II, Pentium III, and Pentium IV processors, contain chipsets that infringe the '154 patent. At the Markman hearing, the Court construed FN1 Claim 1 limitations nine and ten, and thirteen FN2 and fourteen as means-plus-function terms and construed the functions of those terms. Intel argued at the hearing that there were no corresponding structures for these functions. At the hearing, Mitchell argued that the terms were not meansplus-function limitations. In order to be fully briefed on the issue of corresponding structure, the Court did not identify the corresponding structures for these functions and instead deferred the issue to summary judgment. The determination of whether a

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corresponding structure exists for these functions is now ripe for decision. FN1. Limitation nine states "first switch means comprised of at least three distinct parts for connecting said dedicated memory address, data, and control circuits of said path configuring means to each of said first three sets of contacts." Limitation ten states "second switch means for connecting said dedicated memory address, data, and control lines of said path configuring means to said dedicated memory address, data, and control lines of said CPU respectively." FN2. Limitations thirteen and fourteen state "means for causing said first and second switch means to remain in said non signal-conducting state upon application of power to said CPU power circuit and to assume a signal conductive state upon receipt of an appropriate signal from said CPU" and to "assume a non signal-conducting state upon receipt of an appropriate signal from said CPU." APPLICABLE LAW Summary Judgment Standard Summary judgment shall be rendered when the pleadings, depositions, answers to interrogatories, and admissions on file, together with the affidavits, if any, show that there is no genuine issue as to any material fact and that the moving party is entitled to judgment as a matter of law. FED.R.CIV.P. 56(c); Celotex Corp. v. Catrett, 477 U.S. 317, 323-25 (1986); Ragas v. Tenn. Gas Pipeline Co., 136 F.3d 455, 458 (5th Cir.1998). An issue of material fact is genuine if the evidence could lead a reasonable jury to find for the non-moving party. Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 248 (1986). In determining whether a genuine issue for trial exists,

the court views all inferences drawn from the factual record in the light most favorable to the nonmoving party. Id.; Matsushita Elec. Indus. Co. v. Zenith Radio, 475 U.S. 574, 587 (1986). Indefiniteness *2 A patent is entitled to a presumption of validity, and an accused infringer must prove invalidity by clear and convincing evidence. Metabolite Labs., Inc. v. Lab. Corp., 370 F.3d 1354, 1365 (Fed.Cir.2004). The requirement that "claims `particularly point ... out and distinctly claim ...' the invention is met when a person experienced in the field of the invention would understand the scope of the subject matter that is patented when reading the claim in conjunction with the rest of the specification." Default Proof Credit Card Sys., Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed.Cir.2005) (quoting S3 Inc. v. nVIDIA Corp., 259 F.3d 1364, 1367 (Fed.Cir.2001)). However, if one " `employs means-plus-function language in a claim, one must set forth in the specification an adequate disclosure showing what is meant by that language. If an applicant fails to set forth an adequate disclosure, the applicant has in effect failed to particularly point out and distinctly claim the invention as required by the second paragraph of section 112." See 35 U.S.C. § 112, ¶ 6." Id. (quoting In Re Donaldson Co., 16 F.3d 1189, 1195 (Fed.Cir.1994) (en banc)). Accordingly, when faced with means-plus-function limitations, courts "must turn to the written description of the patent to find the structure that corresponds to the means recited in the [limitations]." Default, 412 F.3d at 1298. " `A structure disclosed in the specification qualifies as "corresponding" structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.' " Id. (quoting B. Braun Med. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed.Cir.1997)). "This duty to link or associate structure to function is the quid pro quo for the convenience of employing § 112, ¶ 6." Id. (citing O.I.

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Corp. v. Tekmar Co., 115 F.3d 1576, 1583 (Fed.Cir.1997)). The question is "whether one skilled in the art would understand the specification itself to disclose the structure, not simply whether that person would be capable of implementing that structure." Med. Instrumentation & Diagnostics Corp. v. Elekta AB, 344 F.3d 1205, 1212 (Fed.Cir.2003). ANALYSIS Corresponding Structure for First and Second Switch Means The ninth limitation claims a "first switch means" with a function of "connecting said dedicated memory address, data, and control circuits of said path configuring means to each of said first three sets of contacts." Claim Construction Opinion at 32. The tenth limitation claims a "second switch means" with a function of "connecting said dedicated memory address, data, and control lines of said path configuring means to said dedicated memory address, data, and control lines of said CPU respectively." Id. at 33. Mitchell asserts that the corresponding structure for these functions is described at columns 19:64-20:5. This passage says: *3 Each first switch means, second switch means, third switch means 108, fourth switch means 110, fifth switch means 112, sixth switch means 114, and seventh switch means 116, it is noted, actually represents a plurality of logical elements, each of which can logically disconnect an address, data, or control circuit that is mechanically connected to the switch means, under the control of the CPU 102 when power is being supplied to the BICPU microcomputer power circuits. '154 patent, col. 19:64-20:5. This passage merely refers to a "plurality of logical elements." Even Mitchell himself recognized that a plurality of logical elements can refer to any number of combina-

tions of elements and does not refer to a specific FN3 structure. Dr. Patterson, Mitchell's expert, corroborated Mitchell's testimony regarding this issue. FN4 FN3. When asked in his deposition whether the patent described anywhere which of these thousands of "logical elements" should be used to build the first switch means, Mitchell responded "that leaves that up to the designers." Mitchell Depo. at 224:23-225:12. Mitchell further recognized that the switch means could be built in "almost as many different ways as there were design teams." Id. FN4. When asked about how many possible combinations of circuits could provide this logical connection other than the tri-state device, Patterson responded "there is many other examples ... [t]here is, you got all the combinations of all kinds of things that can be. It can be a big number, I don't know." Patterson Depo. at 155:8-25. At the hearing on this motion, the Court repeatedly asked Mitchell to identify a structure in the speFN5 cification that corresponded to the functions. Mitchell could only point to the language above and tell the Court that a person skilled in the art would know that a "plurality of logical elements" necessarily referred to tri-state circuitry. Notably, tri-state circuitry is never mentioned the language quoted above, nor does it appear anywhere in the specification. FN5. The transcript from the hearing at p. 26-27 states: THE COURT: So what are you saying, though, is the structure and is it supported by the summary judgment proof; and if so where? MR. SCHWARTZ: Well, the structure has to do with the tri-state drivers. The

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tri-state drivers were known to those of ordinary skill in the art at the time this applicationIn response, Intel states: MR. VAN NEST: Your Honor, there isn't a word anywhere in the specification about a tri-state driver. Mitchell argues that a person skilled in the art could read the function of limitations nine and ten and infer from the function that a tri-state circuitry device is a device that could perform the function. See Patterson Supplemental Decl. ISO Sur-Reply to MSJ of Invalidity, ¶ 14. The only authority Mitchell cited in the hearing to support this proposition was Budde v. Harley-Davidson, Inc. 250 F.3d 1369 (Fed.Cir.2001). In Budde, the Federal Circuit stated, "it is well settled that whether or not the specification adequately sets forth structure corresponding to the claimed function necessitates consideration of that disclosure from the viewpoint of one skilled in the art." Id. at 1376. While this is the law, the specification must disclose at least some kind of structure in the first place for this rule to apply. The law is clear: the corresponding structure must appear in the specification, and an expert cannot use his knowledge to select a structure that is capable of performing the recited function. Atmel, 198 F.3d at 1382 ("knowledge of one skilled in the particular art ... may only be employed in relation to structure that is disclosed in the specification."). This is the trade off for claiming as meansplus-function. The limitation must `be construed to cover the corresponding structure ... described in the specification and equivalents thereof.' " 35 U.S.C. § 112, ¶ 6. Braun Med., 124 F.3d at 1424. Therefore, some structure must be identified. Following the hearing on this motion, where Mitchell was unable to articulate a structure, Mitchell filed its Notice of Record Cite and Supplemental Authority (Docket No. 191). Despite the repeated inquiries for Mitchell to identify a structure, even in its supplemental briefing, Mitchell could

point to no more than the "logical element" language above. Mitchell reurges the proposition that "[o]ne skilled in the art would know that the logical element, each of which can logically connect or disconnect, is the recitation of the structure of the switch means" and that one skilled in the art would know from the "plurality of logical elements" language that the first and second switch means are tristate devices. Mitchell's Notice of Record Cite and Supplemental Authority at 6-7. However, again no where in the specification do the phrases "tri-state devices" or "tri-state circuitry" appear. *4 While tri-state devices may perform the recited functions, and one skilled in the art might know the function could be performed by a tri-state device, the patentee is limited to structures actually disclosed in the specification when the patentee claims as means-plus-function. See Atmel, 198 F.3d at 1382. Here, no structure is disclosed in the specification for this function. Mitchell points to a printing error in the patent office that caused part of a sentence to be deleted in column 14:22. The sentence in the patent reads "[t]he buffers driving the"; and the rest of the sentence is cut off. '154 patent, Col. 14:22. Mitchell argues that in reviewing the prosecution history, it is clear that the sentence at one time read "[t]he buffers driving the data bus lines have full `three-state' capability. This is necessitated by the fact that the lines are bi-directional." Mitchell's Notice of Record Cite and Supplemental Authority at 5. Mitchell argues that this language is specifically directed towards the "three-state" capability and supports a corresponding structure. Id. Even if this sentence is directed toward tri-state circuitry, and it is debatable that even the complete version of the sentence would support a corresponding structure, at no time did Mitchell file a certificate of correction to remedy this omission. The law requires the structure to be set forth in the specification, not the prosecution history. See 35 U.S.C. § 112, ¶ 6. It is the patentee's responsibility to review and correct errors in the patent in a timely

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fashion to avoid errors and omissions. See Sw. Software, Inc. v. Harlequin, Inc., 226 F.3d 1280, 1296 (Fed.Cir.2000) ( "Moreover, it does not seem to us to be asking too much to expect a patentee to check a patent when it is issued in order to determine whether it contains any errors that require the issuance of a certificate of correction."). The USPTO offers the certificate of correction procedure to cure just such defects so that patent owners can be assured that when the public views their patents, they view accurate representations of the claimed invention. See id. (In a case where the corresponding structure was not originally included in the patent, the Federal Circuit noted: "Until the PTO issues a certificate of correction pursuant to 35 U.S.C. § 254 adding the corresponding structure, such a claim would appear invalid to the public, and reasonable competitors would be justified in conducting their affairs accordingly."). There is no reference to a structure in the specification to support the functions in limitations nine and ten as required by 35 U.S.C. § 112, ¶ 6; therefore, Claim 1 is invalid because it is indefinite. Corresponding Structure for "means for causing" The thirteenth and fourteenth limitations claim a "means for causing" with functions of "(1) [c]ausing said first and second switch means to remain in said non signal-conducting state upon application of power to said CPU power circuit and to assume a signal conductive state upon receipt of an appropriate signal from said CPU and (2)[a]ssum[ing] a non-signal conducting state upon receipt of an appropriate signal from said CPU." Claim Construction Opinion at 33. In identifying the corresponding structure to these functions at the Markman hearing, Intel proposed adopting Judge Illston's previous construction. Mitchell did not provide the Court with an alternative corresponding structure in its brief or argument; therefore, the Court adopted Judge Illston's structure and stated "[t]o the extent that any structure for the corresponding function of the thirteenth and fourteenth

limitations is provided in the specification, that structure is described at col. 24:67-col. 25:56." Id. The passage at columns 24:67-25:56 contains no structure. Rather, as discussed below, even Mitchell recognizes that the passage describes the operation of the switch means, but does not disclose any structure. *5 At the hearing, Mitchell referred the Court to a device called a MCS-6520 and said the device related to tri-state drivers. Hearing on Mot. Summary Judgment Tr. at 30. This device is discussed in column 15 and is completely outside the Markman ruling. '154 patent, Col. 15:42-55. Even if the Court considered the MCS-6520 as a possible structure, nothing in this part of the specification links the MCS-6520 with claim limitations thirteen and fourFN6 teen. The MCS-6520 is a chip comprised of various parts including drivers, but no driver is specifically detailed in the description at column 15. Intel argued, and Mitchell did not rebut the statement, that Mitchell is essentially saying that one skilled in the art would read the language at columns 24-25 and then look at the MCS-6520 as a whole and determine that somewhere in that chip is a tri-state device that is the structure for the funcFN7 tions of "means for causing." Federal Circuit precedent simply does not allow this reading of the patent to satisfy the § 112, ¶ 6 requirement. See Atmel, 198 F.3d at 1382. Mitchell could not identify any other possible corresponding structure at the FN8 hearing. FN6. The language reads: The MCS6520 is a direct pin for pin replacement for the Motorola MC6820 Peripheral Interface Adapter, the "PIA." As such, it meets all of the "PIA" electrical specifications and is totally hardware compatible with the MC6820. The MCS6520 is an I/O device which acts as an interface between the microprocessor and the peripherals such as printers, displays, keyboards, etc. The

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prime function of the MCS6520 is to respond to stimulus from each of the two worlds it is serving. On one side, the 6520 is interfacing with the peripherals via two eight-bit-bi-directional peripheral data ports. On the other side, the device interfaces with the microprocessor through an eight-bit data bus...." '154 patent, Col. 15:42-55. FN7. MR. VAN NEST: What they are saying is you have to read this [Cols 24-25] and then go look at the 6520, which is a whole chip. It is not a switch or a buffer or a driver. It is a whole chip, Your Honor, with thousands and thousands of transistors. They are saying go look at this and somewhere in it you can find a tri-state driver and that is our structure. Hearing on Mot. Summary Judgment Tr. at 31. FN8. Hearing transcript at p. 33: THE COURT: So what is the structure that one of ordinary skill in the art would have seen and linked up to the function? MR. SCHWARTZ: Yes, Your Honor. That is precisely the point that Mitchell has taken in this case. There is no specific detailed structure set out in the specification. In its post-hearing-supplemental briefing, Mitchell seems to abandon the MCS-6520 argument and instead lays out the entire passage the Court set out in FN9 the Markman opinion and argues that the passage "is actually a description of the operation of the switch means." Mitchell's Notice of Record Cite and Supplemental Authority at 8 (emphasis added). Thus, Mitchell's reasoning is the same as its argument for limitations nine and ten: this passage does not identify a specific structure, but one skilled in the art would know that the corresponding structure

could be the control elements of the tri-state devices. Id. ("What is set forth above in Columns 24 and 25 to one skilled in the art is a description of how control is exerted on the control elements of the tri-state devices."). Mitchell asserts that the "means for causing" is understood by one skilled in the art as a specific portion of the tri-state circuitry, which is the control element. Id. But again, there is no reference to tri-state circuitry, control elements, or any other structure in this passage. FN9. The passage reads: Col. 24, line 67 to Col. 25, line 17: When power is removed from the BICPU microcomputer power circuits, a first switch means automatically, logically disconnects, and floats each connected circuit, and latches the first switch means in the logically disconnected position. Each logically disconnected and latched, floating, address circuit, data circuit and control circuit stays floating and logically disconnected and latched, when power is supplied to the BICPU microcomputer power circuits, until each first switch means is logically connected by signals from the BICPU microcomputer, after power is supplied to the BICPU microcomputer power circuits. A first switch means remains under control of the BICPU microcomputer, after power is supplied to the power circuits, and the BICPU microcomputer can logically disconnect and float, or logically connect, each of these circuits connected to a first switch means. Col. 25, lines 33-49: Each of these circuits contains a second switch means, similar in action to the first switch means, except the logically disconnected, floating, latched portion of

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the circuit, is connected to the CPU of the BICPU microcomputer. Each logically disconnected, floating, latched CPU address circuit, data circuit and control circuit, stays floating and disconnected and latched, when power is supplied to the BICPU microcomputer power circuits until each second switch means is logically connected, by signals from the BICPU microcomputer after power is supplied to the BICPU microcomputer power circuits. A second switch means remains under control of the BICPU microcomputer, after power is supplied to the power circuits,. and the BICPU microcomputer can logically disconnect or logically connect, each of the circuits connected to a second switch means. Once again, there is no reference to a structure in the specification to support the functions in limitations thirteen and fourteen as required by 35 U.S.C. § 112, ¶ 6, thus Claim 1 must fail as invalid because it is indefinite. CONCLUSION Accordingly, Mitchell has failed to raise a fact issue as to whether limitations nine, ten, thirteen, and fourteen set forth corresponding structures for their functions as required by 35 U.S.C. § 112, ¶ 6. The Court holds that Claim 1 is indefinite and therefore invalid as a matter of law and GRANTS Intel's motion for summary judgment as to invalidity. So ORDERED. E.D.Tex.,2006. Maurice Mitchell Innovations, L.P. v. Intel Corp. Not Reported in F.Supp.2d, 2006 WL 3447632 (E.D.Tex.) END OF DOCUMENT

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Page 1 249 Fed.Appx. 184, 2007 WL 2777968 (C.A.Fed.) (Not Selected for publication in the Federal Reporter) (Cite as: 249 Fed.Appx. 184, 2007 WL 2777968 (C.A.Fed.))

This case was not selected for publication in the Federal Reporter. Not for Publication in West's Federal Reporter See Fed. Rule of Appellate Procedure 32.1 generally governing citation of judicial decisions issued on or after Jan. 1, 2007. See also Federal Circuit Rule 32.1 and Federal Circuit Local Rule 32.1. (Find CTAF Rule 32.1) United States Court of Appeals, Federal Circuit. MAURICE MITCHELL INNOVATIONS, L.P., Plaintiff-Appellant, v. INTEL CORPORATION, Defendant-Appellee. No. 2007-1108. Sept. 24, 2007. Rehearing and Rehearing En Banc Denied Nov. 5, FN* 2007. FN* Circuit Judge Schall did not participate in the vote. *184 Appealed from United States District Court for the Eastern District of Texas, Leonard Davis, Judge. Richard L. Schwartz, Whitaker, Chalk, Swindle & Sawyer, L.L.P., of Fort Worth, TX, argued for plaintiff-appellant. Of counsel on the brief was Manny D. Pokotilow, Caesar, Rivise, Bernstein, Cohen & Pokotilow, Ltd., of Philadelphia, PA. Robert A. Van Nest, Keker & Van Nest LLP, of San Francisco, CA, argued for defendant-appellee. With him on the brief were Christa M. Anderson and Steven A. Hirsch. Before RADER, MOORE, Circuit Judges, and FN** YEAKEL, District Judge .

FN** Honorable Lee Yeakel, District Judge, United States District Court for the Western District of Texas, sitting by designation. RADER, Circuit Judge. **1 The United States District Court for the Eastern District of Texas granted Intel Corporation's ("Intel") motion for summary judgment that claim 1 of U.S. Patent No. 4,875,154 ("the '154 patent") is invalid as indefinite pursuant to 35 U.S.C. § 112, ¶ 2. Maurice Mitchell Innovations, L.P. v. Intel Corp., No. 2:04-CV-450 (E.D.Tex. *185 Dec. 11, 2006) (" Final Judgment "); Maurice Mitchell Innovations, L.P. v. Intel Corp., No. 2:04-CV-450, 2006 WL 3447632 (E.D.Tex Nov. 22, 2006) (" Opinion "); Maurice Mitchell Innovations, L.P. v. Intel Corp., No. 2:04-CV-450, 2006 WL 1751779 (E.D.Tex. Jun. 21, 2006) (" Claim Construction Opinion "). Because the district court correctly construed the claim term "means for causing" as a means-plus-function limitation under 35 U.S.C. § 112, ¶ 6 and correctly found the specification did not contain any corresponding structure, this court affirms. I The United States Patent and Trademark Office issued the '154 patent, entitled Microcomputer with Disconnected, Open, Independent, Bimemory Architecture, Allowing Large Interacting, Interconnected Multi-microcomputer Parallel Systems Accomodating [sic] Multiple Levels of Programmer Defined Heirarchy [sic], on October 17, 1989 from an application filed on June 12, 1987. The patent abstract states: A Bimemory Independent CPU (BICPU) microcomputer which is comprised of a known CPU chip provided with additional circuitry to enable CPU to interact in a multi BICPU microcomputer system. Each BICPU microcomputer in a system

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is supplied with an assigned standard memory mechanically and logically connected to it's [sic] BICPU's "A" bus circuits. The BICPU microcomputer is also provided with connectors enabling the CPU to be connected to system buses. Any number of BICPU microcomputers can be logically chained, linked and treed in a simple logical bimemory independent pattern infinitely in as many dimensions as is reasonably desired, using one standard set of dedicated, simple, single line conductors (system buses) to mechanically interconnect any "B" or "C" bus curcuits [sic] of two different BICPU microcomputers. '154 Patent Abstract. Generally, the patent describes a BICPU computer system "comprised of a known CPU chip with additional circuitry to enable the CPU to interact in a multi BICPU microcomputer system." '154 Patent col.7 ll.3-6. According to the specification, the invention allows "[a]ny number of BICPU microcomputers [to] be logically chained, linked and treed in a simple logical bimemory independent pattern infinitely in as many dimensions as is reasonably desired, using one standard set of dedicated, simple, single line conductors (system buses) to mechanically interconnect any `B' or `C' bus circuits of two different BICPU microcomputers." '154 Patent col.7 ll.12-19. Claim 1 reads: A microcomputer data processing apparatus, comprising: [1] a Central Processing Unit (CPU), [2] a path configuring means, [3] path control circuits connecting said CPU to said path configuring means, **2 [4] a plurality of contacts comprised of a plurality of distinct sets, [5] wherein said CPU further comprises a dedicated memory address circuit, a dedicated memory data circuit, a dedicated memory control circuit and a dedicated power circuit,

[6] wherein said path configuring means further comprises a dedicated memory address circuit, a dedicated memory data circuit and a dedicated memory control circuit, [7] wherein each dedicated memory address, data, and control circuit includes a plurality of dedicated *186 memory address, data, and control lines respectively, wherein [8] said memory control lines are comprised of a read/write line, timing lines and status lines, [9] first switch means comprised of at least three distinct parts of connecting said dedicated memory address, data, and control circuits of said path configuring means to each of said first three sets of contacts, and [10] second switch means for connecting said dedicated memory address, data, and control lines of said path configuring means to said dedicated memory address, data, and control lines of said CPU respectively, [11] wherein said first and second switch means assume a non signal-conducting state when said CPU power circuit is not supplied with power, [12] wherein said lines of said CPU an said contacts assume a non-signal conducting state when said first and second switch means are in said nonsignal conducting state, [13] means for causing said first and second switch means to remain in said non signal-conducting state upon application of power to said CPU power circuit and to assume a signal-conductive state upon receipt of an appropriate signal from said CPU, and to [14] assume a non signal-conducting state upon receipt of an appropriate signal from said CPU. '154 Patent col.90 l.59-col.91 l.37 (emphases and [limitation numbers] added).

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Maurice Mitchell Innovations, L.P. ("Mitchell") brought suit against Intel in the United State District Court for the Eastern District of Texas alleging a number of Intel's products infringe Claim 1 of the '154 patent. In construing the claims, the district court adopted the claim construction of District Judge Susan Illston of the United States District Court for the Northern District of California. Claim Construction Opinion; see, Maurice Mitchell v. Samsung Electronics Co., Ltd., No. C 01-0295 SI (N.D.Cal. Jan. 29, 2002). Specifically, the district court construed "first switch means," "second switch means," and "means for causing" as meansplus-function limitations governed by 35 U.S.C. § 112, ¶ 6. Id. The district court then determined that the '154 patent specification did not disclose structure for the "switch means" limitations and the "means for causing" limitation. Opinion. As a result, the district court found Claim 1 of the '154 patent indefinite and therefore invalid as a matter of law. Id. II **3 This court reviews a district court's grant of summary judgment without deference, drawing all justifiable inferences in favor of the nonmovant. Genentech, Inc. v. Amgen, Inc., 289 F.3d 761, 767 (Fed.Cir.2002). Claim construction is a matter of law that this court reviews without deference. Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1456 (Fed.Cir.1998) (en banc); Markman v. Westview Instruments, Inc., 52 F.3d 967, 979 (Fed.Cir.1995), aff'd, 517 U.S. 370, 116 S.Ct. 1384, 134 L.Ed.2d 577 (1996). "The review of indefiniteness under 35 U.S.C. § 112, paragraph 2, proceeds as a question of law without deference." SmithKline Beecham Corp. v. Apotex Corp., 403 F.3d 1331, 1338 (Fed.Cir.2005). "A patent issued from the United States Patent and Trademark Office (PTO) bears the presumption of validity under 35 U.S.C. § 282. An accused infringer, therefore,*187 must prove patent invalidity under the clear and convincing evidentiary stand-

ard." Metabolite Labs., Inc. v. Lab. Corp. of Am. Holdings, 370 F.3d 1354, 1365 (Fed.Cir.2004). Specifically, "[t]he claims as granted are accompanied by a presumption of validity based on compliance with, inter alia, § 112 ¶ 2." S3 Inc. v. NVIDIA Corp., 259 F.3d 1364, 1367 (Fed.Cir.2001) . As stated in § 112 ¶ 2, "[t]he specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention." Claims "particularly point[ ] out and distinctly claim[ ]" the invention when one of ordinary skill in the art would understand the scope of the invention when the claims are read in conjunction with the specification. Default Proof Credit Card Sys., Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed.Cir.2005); 35 U.S.C. § 112 ¶ 2. But, if an applicant "employs means-plus-function language in a claim, one must set forth in the specification an adequate disclosure showing what is meant by that language." In re Donaldson, 16 F.3d 1189, 1195 (Fed.Cir.1994) (en banc); 35 U.S.C. § 112 ¶ 6. Therefore, "[i]f there is no structure in the specification corresponding to the meansplus-function limitation in the claims, the claim will be found invalid as indefinite." Biomedino, LLC v. Waters Technologies Corp., 490 F.3d 946, 950 (Fed.Cir.2007). III The district court found that "means for causing" was a means-plus-function limitation without any descriptive corresponding structure within the specification. The only possible structure corresponding to the claimed function appears at Col.24 l.67 to Col.25 l. 56. Opinion, slip op. at 8. The district court then determined this passage did not contain any structure. As illustrated by the claim language in limitation 13, the "means for causing" controls the first and second switch means. In other words, the "means

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for causing" would need a structure (i.e., device or driver) to control the function of the switch means. Mitchell contends that the '154 patent specification contains an adequate disclosure corresponding to the "means for causing" limitation to satisfy § 112 ¶ 2. Mitchell argues that the district court incorrectly limited the corresponding structure to the disclosure at Col.24 l.67 to Col.25 l.56 when the following additional passages also disclose structure: Col.15, ll.40-56; Col.19, line 34 to Col.20, line 5; Col.13, ll.11-19; Col.7, ll.37-44; Col.44, ll.21-46; Col.89, ll.14-49; Col.90, ll.16-30; and Col.16, ll.48-53. **4 Like the district court, however, this court discerns little, if any, structure for "means for causing" in the specification and no disclosed link between that purported structure and the claimed function. This court also credits the district court's finding that Mitchell's counsel admitted during the summary judgment hearing that the Col.24 l.67 to Col.25 l.56 passage does not include any structure linked to the claimed function. Maurice Mitchell Innovations v. Intel Corp., 2:04cv450, slip op. at 35 (E.D.Tex. Sept. 28, 2006) (Transcript of Pretrial and Motion Hearing). Beyond that passage, however, this court finds no specific structure disclosed anywhere in the specification to carry out the "means for causing" function. Mitchell also offers another source of structure for the claimed means. The specification refers to the MCS6520 Peripheral Interface Adaptor ("PIA"). ' 154 Patent col.15 ll.40-55. The MCS6520 is a complex integrated circuit (i.e., chip) containing numerous individual circuits which *188 functions as an interface between a microprocessor and peripheral devices such as printers, displays and the like. Mitchell contends that the MCS6520 contains tristate circuitry or tri-state drivers and that a person of ordinary skill in the art would understand the tristate structure in the MCS6520 to be capable of performing the "means for causing" function. While the MCS6520 may contain tri-state or driver type circuits, the specification does not identify the

tri-state circuits in the MCS6520 as the structure to carry out the "means for causing" limitation. The mere mention of a complicated integrated circuit, comprised of hundreds if not thousands of circuits, is much too broad to sufficiently indicate the precise "means for causing" structure to a person of ordinary skill in the art. See Med. Instrumentation & Diagnostics Corp. v. Elekta AB, 344 F.3d 1205, 1212 (Fed.Cir.2003) ("It is important to determine whether one of skill in the art would understand the specification itself to disclose the structure, not simply whether that person would be capable of implementing that structure."). In other words, as the district court noted, the MCS6520 is both too broad and not linked to the "means for causing" limitation. Opinion, slip op. at 8-9. Mitchell also attempts to identify structure in a variety of generalized passages in the specification. This court has examined these passages and finds no specific structure. Mitchell only states that "[t]hese passages are additional disclosures of the details of the structure, readily apparent to a person of ordinary skill in the art." In effect, Mitchell merely references various passages in the specification without providing any information to show structure corresponding to "means for causing." Mitchell appears to be arguing that a person of ordinary skill in the art would be able to ascertain the corresponding structure by combining a variety of passages in the specification with their knowledge of the art. However, "in order for a claim to meet the particularity requirement of ¶ 2, the corresponding structure(s) of a means-plus-function limitation must be disclosed in the written description in such a manner that one skilled in the art will know and understand what structure corresponds to the means limitation." Atmel Corp. v. Info. Storage Devices, Inc., 198 F.3d 1374, 1382 (Fed.Cir.1999). Thus, the statute requires more than just the possibility that an artisan of ordinary skill may be able to figure out the corresponding structure. The quid pro quo for using a means-plus-function limitation requires specificity in reciting structure and linking that structure to the limitation. Id. Mitchell does not carry

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out its part of the quid pro quo bargain. This court sustains the finding that claim 1 is indefinite under U.S.C. § 112, ¶ 2. **5 This court need not reach the "switch means" and "path configuring means" limitations because the district court's decision can be affirmed solely on the "means for causing" limitation. IV Because the district court correctly construed the claim term "means for causing" as a meansplus-function limitation under 35 U.S.C. § 112, ¶ 6 and correctly found the specification did not contain any corresponding structure for this limitation, this court affirms. AFFIRMED COSTS Each party shall bear its own costs. C.A.Fed.,2007. Maurice Mitchell Innovations, L.P. v. Intel Corp. 249 Fed.Appx. 184, 2007 WL 2777968 (C.A.Fed.) END OF DOCUMENT

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