DSS Technology Management, Inc. v. Apple, Inc.

Filing 1

COMPLAINT Complaint for Patent Infringement against Apple, Inc. ( Filing fee $ 400 receipt number 0540-4420499.), filed by DSS Technology Management, Inc.. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Civil Cover Sheet)(Joe, Christopher)

EXHIBIT 1

111111

United States Patent

[19]

Carvey

1111111111111111111111111111111111111111111111111111111111111
US006128290A

[11]

[45]

[54]

Inventor:

[73]

Assignee: BBN Corporation, Cambridge, Mass.

[ *]

Notice:

[21]

Appl. No.: 08/949,999

[22]

Filed:

Philip P. Carvey, Bedford, Mass.

This patent is subject to a terminal disclaimer.

Primary Examiner---Ruy D. Vu
Assistant Examiner-Jasper Kwoh
Attorney, Agent, or Firm-Leonard Charles Suchyta; Floyd
E. Anderson

Oct. 14, 1997
Related U.S. Application Data

[63]

Continuation-in-part of application No. 08/611,695, Mar. 6,
1996, Pat. No. 5,699,357.

[51]
[52]

Int. CI? ..................................................... H04B 7/212
U.S. CI. .......................... 370/347; 370/350; 370/442;
370/509; 455/89; 364/708.1
Field of Search ..................................... 370/347,350,
370/442, 509, 512; 455/89; 364/708.1

[58]

References Cited

[56]

U.S. PATENT DOCUMENTS
5,247,285

*Oct. 3, 2000

5,297,142 3/1994 Paggeot et al. ......................... 370/461
5,307,297 4/1994 Iguchi et al. ... ... ... .... ... ... ... ... 364/708.1
5,371,734 12/1994 Fischer .................................... 370/311
5,481,265 1/1996 Russell .. .... ... ... ... ... ... .... ... ... ... .... 341/22
5,517,505 5/1996 Buchholz et al. ...................... 370/350
5,598,419 1/1997 Weigand et al. ........................ 370/514

PERSONAL DATA NETWORK

[75]

6,128,290

Patent Number:
Date of Patent:

[57]

ABSTRACT

The data network disclosed herein utilizes low duty cycle
pulsed radio frequency energy to effect bidirectional wireless data communication between a server microcomputer
unit and a plurality of peripheral units located within short
range of the server unit, e.g. within 20 meters. By establishing a tightly synchronized common time base between
the units and by the use of sparse codes, timed in relation to
the common time base, low power consumption and avoidance of interference between nearby similar systems is
obtained.

11 Claims, 8 Drawing Sheets

9/1993 Yokota et al. .......................... 361/680

21

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PERSONAL DATA NETWORK

being developed which project a private image directly into
an user's eye using a device which is mounted on a headband or eyeglasses. These displays are useful, for example,
for providing combat information to military personnel and
for realistic games. Likewise, so called virtual keyboards are
being developed which use inertial or magnetic sensors
attached to a users fingers in the manner of rings. Further,
apart from more usual business type computer applications,
the data network system of the present invention may also be
useful for applications such as physiological monitoring
where the peripheral units may be physiological sensors
such as temperature, heartbeat and respiration rate sensors.
As will be understood, such peripheral units may be useful
for outpatient monitoring, monitoring for sudden infant
death syndrome, and for fitness training. It is convenient in
the context of this present description to refer to such
conventional and inconventional peripheral units collectively as personal electronic accessories (PEAs).
Briefly stated, a data network system according to the
present invention effects coordinating operation of a plurality of electronic devices carried on the person of the user.
These devices include a server microcomputer and a plurality of peripheral units which are battery powered and
portable and which provide input information from the user
or output information to the user. The server microcomputer
incorporates an RF transmitter for sending commands and
synchronizing information to the peripheral units. The
peripheral units, in turn, each include an RF receiver for
detecting those commands and synchronizing information
and include also respective RF transmitters for sending
information from the peripheral unit to the server microcomputer. The server microcomputer includes a receiver for
receiving that information transmitted from the peripheral
units.
The server and peripheral unit transmitters are energized
in low duty cycle pulses at intervals which are determined by
a code sequence which is timed in relation to the synchronizing information initially transmitted from the server
microcomputer.

CROSS REFERENCE TO RELATED
APPLICATION
This application is a continuation-in-part of application
Ser. No. 08/611,695 filed on Mar. 6, 1996 now U.S. Pat. No.
5,699,357.
BACKGROUND OF THE INVENTION
The present invention relates to a data network and more
particularly to a data network which can effect bidirectional
wireless data communications between a microcomputer
unit and a plurality of peripheral units, all of which are
adapted to be carried on the person of the user.
The size and power consumption of digital electronic
devices has been progressively reduced so that personal
computers have evolved from lap tops through so-called
notebooks, into hand held or belt carriable devices commonly referred to as personal digital assistants (PDAs). One
area which has remained troublesome however, is the coupling of peripheral devices or accessories to the main
processing unit. With rare exception, such coupling has
typically been provided by means of connecting cables
which place such restrictions on the handling of the units
that many of the advantages of small size and light weight
are lost.
While it has been proposed to link a keyboard or a mouse
to a main processing unit using infrared or radio frequency
(RF) communications, such systems have been typically
limited to a single peripheral unit with a dedicated channel
of low capacity.
Among the several objects of the present invention may
be noted the provision of a novel data network which will
provide wireless communication between a host or server
microcomputer unit and a plurality of peripheral units; the
provision of a data network which provides highly reliable
bidirectional data communication between the peripheral
units and the server; the provision of such a data network
which requires extremely low power consumption, particularly for the peripheral units; the provision of such a network
system which avoids interference from nearby similar systems; and the provision of such a data network system which
is highly reliable and which is of relatively simple and
inexpensive construction. Other objects and features will be
in part apparent and in part pointed out hereinafter.

5

10

15

20

25

30

35

40

BRIEF DESCRIPTION OF THE DRAWINGS

45

SUMMARY OF THE PRESENT INVENTION
The data network of the present invention utilizes the fact
that the server microcomputer unit and the several peripheral
units which are to be linked are all in close physical
proximity, e.g., within twenty meters, to establish, with very
high accuracy, a common time base or synchronization. The
short distances involved means that accuracy of synchronization is not appreciably affected by transit time delays.
Using the common time base, code sequences are generated
which control the operation of the several transmitters in a
low duty cycle pulsed mode of operation. The low duty cycle
pulsed operation both substantially reduces power consumption and facilitates the rejection of interfering signals.
In addition to conventional peripheral devices such as a
keyboard or mouse, it should be understood that data communications in accordance with the present invention will
also be useful for a wide variety of less conventional
peripheral systems which can augment the usefulness of a
microcomputer such as a PDA. For example, displays are

50

55

60

65

FIG. 1 is an overall block diagram of a wireless data
network system linking a personal digital assistant or server
microcomputer with a plurality of peripheral units;
FIG. 2 is a block diagram of a modem circuitry employed
in one of the peripheral units of FIG. 1;
FIG. 3 is a block diagram of a modem circuitry employed
in the server microcomputer of FIG. 1;
FIG. 4 is a block diagram of the transmitter circuitry
employed in the modem of FIG. 2;
FIG. 5 is a circuit diagram of receiver circuitry employed
in the modem of FIG. 2; and
FIG. 6 is a diagram illustrating timing ofRF signals which
are transmitted between the server microcomputer and the
various peripheral units;
FIG. 7 is a block diagram of the controller employed in
the PEA modem; and
FIG. 8 is a block diagram of the digital matched filter
employed in the PEA controller; and
Corresponding reference characters indicate corresponding parts throughout the several view of the drawings.
DESCRIPTION OF THE PREFERRED
EMBODIMENT
Referring now to FIG. 1, a server microcomputer of the
type characterized as a personal digital assistant (PDA) is

6,128,290

3

4

designated generally be reference character 11. The PDA
greater detail hereinafter, the FSK tones are transmitted in
only those slots indicated by a TDMA program. Both the
may also be considered to be a HOST processor and the
HUB of the local network. The PDA is powered by a battery
host and all PEAs share a common TDMA program at one
12 and may be adapted to be carried on the person of the
time. For each slot, this TDMA program indicates that a PEA
user, e.g. in his hand or on a belt hook. Such PDAs typically 5 or host is to transmit, or not, and whether it will receive, or
not. In the intervals between slots in which a PEA is to
accept options which are physically configured as an industry standard PCMCIA card. In accordance with the present
transmit or receive, all receive and transmit circuits are
invention such a card, designated by reference character 13
powered down.
is implemented which includes a PCMCIA interface and
Referring now to FIG. 3, the PEA modem illustrated there
PDAmodem.
10 comprises five major components, a transmitter 15, a
As is described in greater detail hereinafter, the network
receiver 17, a local oscillator 16 which is shared by the
system of the present invention establishes wireless comtransmitter and the receiver, a controller 14 which times and
munication between PDA 11 and a plurality of peripheral
coordinates the operations of the transmitter, receiver, and
units or PEAs designated generally by reference characters
PCMCIA interface and, finally, a crystal oscillator 18 which
21-29. A PDA and a collection of PEAs associated with it 15 is utilized in maintaining the network time base. The oscilare referred to herein as an "ensemble". The present invenlator 18 utilizes a crystal which operates at 4 Mhz. There are
tion allows the creation of a data network linking such an
no differences between the receiver, local oscillator, and
ensemble of elements with minimal likelihood of interfertransmitter in both the PEA and PDA modems. PDA conence from similar ensembles located nearby. Each of the
troller 14 differs from the PEA modem in three ways. First
peripheral units is powered by a respective battery 30 and 20 it contains no synhronization capability as it serves as the
incorporates a PEA modem 31. Further, each peripheral unit
network master. Secondly, it includes a PCMCIA interface
can incorporate a sensor 33, which responds to input from
rather than a sensor/transducer interface. Only the PEA
the user or an actuator 37 which provides output to the user.
modem is described in detail herein since it is includes all
Some peripheral units might also employ both sensors and
the novel capabilities of the PDA modem.
actuators. As illustrated, each PEA modem preferably incor- 25
Referring now to FIG. 4, transmission is effected using the
porates two antenna's, a dipole antenna 38 for reception and
local oscillator 45 to drive the transmit antenna amplifier 50
a loop antenna 39 for transmitting. The use of separate
whose output drives transmit antenna 51. The local oscillator
antennas for transmitting and receiving facilitates the utili45 is coupled to a tuning network 48 including a plurality of
zation of impedance matching networks which in turn
frequence adjusting varactors VRI-VR3. Operation of the
facilitates the operation at very low power.
30 varactors is controlled by switch pairs 52 and 53. 500
Referring now to FIG. 2, the PDAmodem illustrated there
nanoseconds before the start of transmission, the local
comprises five major components, a transmitter 40, a
oscillator 45 is powered up. During this period and during all
receiver 41, a local oscillator 42 which is shared by the
receive intervals, frequency selection varactor switches 52
transmitter and the receiver, a controller 43 which times and
and 53 are opened and closed respectively. This frequency
coordinates the operations of the transmitter, receiver, 35 selection state is employed for all periods except those in
microprocessor and, finally, a voltage controlled crystal
which the local oscillator is used to drive the antenna
oscillator oscillator 44 which is utilized in maintaining a
amplifier. To transmit a "one", both switches 52 and 53 are
common time base with the host microcomputer. The oscilopened. This causes the oscillator to oscillate above its
lator 44 utilizes a crystal which operates at 4 Mhz.
nominal value. To transmit a "zero", both switches 52 and 53
As is described in greater detail hereinafter, the controller 40 are closed. This causes the oscillator to oscillate below its
43 sequences the operations necessary in establishing synnominal value. The local oscillator output then drives amplichronization with the host system, adjusting the oscillator
fier 50. In the preferred embodiment, the transmit antenna 51
is loop of wire two centimeters in diameter. During short
44, acquiring from the host appropriate code sequences to be
used in data communications, in coupling received inforperiods in which data is not being received nor is being
mation from receiver 41 to a sensor/actuator interface, 45 transmitted, the oscillator is powered and the varactor condesignated by reference character 46, and in transmitting
trol voltage V c is adjusted such that the oscillator frequency
data from the interface 46 back to the host through transequals the carrier frequency.
mitter 40. The controller in one embodiment is partitioned
Referring now to FIG. 5, the input signal from the
into a commercially available general purpose microprocesreceiving antenna 38 is applied, through an impedance
sor such as the PIC16C64, together with a special purpose 50 matching network 61 to a low noise amplifier 62 and
logic integrated circuit (IC). The special purpose IC implebandpass filter 63. The received and amplified signal is
ments those functions which cannot be efficiently executed
combined with the local oscillator shifted 45 degrees in
on the general purpose microprocessor. For example, the
phase in mixer 65 to produce signal 1m and combined with
clock to the PIC16C64 is sourced by the special purpose IC
the local oscillator shifted -45 degrees in phase in mixer 66
because even in the microprocessor's so-called "sleep" 55 to produce signal Qm. 1m and Qm are the so-called "inmode, its power consumption is higher than acceptible.
phase" and "quadrature-phase" signals commonly known to
radio engineers. Both 1m and Qm are centered at zero hertz
As is explained in greater detail hereinafter, the general
rather than at an intermediate frequency. This scheme is
scheme of data transmission and reception is a form of time
commonly referred to as "direct conversion" because a
division multiple access (TDMA). This TDMA access is
characterized by a frame interval, common to the host and 60 direct conversion to baseband is effected rather than conall PEAs of 32.768 milliseconds, segmented into 16,384
version to an intermediate frequency which is then contime slots. Each time slot is further partitioned into four data
verted to baseband. Direct conversion reduces power
bit intervals during which the RF carrier is modulated either
consumption, as no intermediate frequency circuits are
above the the nominal for a binary "one" or below the carrier
employed and it allows use of low pass filters to effect
for a binary "zero". The basic modulation scheme is fre- 65 selectivity. Lowpass filters 67 and 68, preferably of the
quency shift keying (FSK), well known to those skilled in
linear phase type, remove the unwanted mixing products and
digital radio transmission. However, as is explained in
provide selectivity of signals 1m and Qm respectively.

6,128,290

5

6

The filtered output signals If and Qf passed through
channels requiring larger bandwidths are assigned a multiplicity of slots. For example, when ten slots are assigned, the
blocking amplifiers 69 and 70 to form signals I and Q. The
virtual channel bandwidth is increased to 1220 bits per
supply currents of amplifiers 69 and 70 are adjusted so that
second. More than one virtual channel can be established
the parasitic output capacitance of these amplifiers effectively form a bandpass filter with gain. These amplifiers 5 between the PDA and a single PEA. If one channel is
outgoing from PDA to PEA while the other channel is
block frequencies below 100 KHz and above two MHz. This
incoming from the PEA to the PDA, an effectively full
filtering adds to the overall selectivity and blocks any
duplex communication link is constructed. It is possible for
unwanted DC mixer byproduct common to direct conversion
each virtual channel to differentiate bandwidths. Another
schemes.
10 possible operational mode is for the data transfer direction of
Some conventional frequency discriminators create the
a single virtual channel to be changed dynamically. A control
signal V=I*dQ/dt-Q*dI/dt. When the frequency of the
channel can be employed whose sole purpose is to indicate
received signal is above the local oscillator frequency, V is
the data flow direction on the data channel. Changeover
greater than zero. Correspondingly, when the frequency of
from one direction to another is typically affected at the
the received signal is below the local oscillator frequency, V
15 frame boundary.
is less than zero. This scheme has the advantages of being
A single virtual channel may be shared amongst several
totally insensitive to both amplitude and phase errors
PEAs under control of the PDA. In this operational mode, a
between I and Q mixer stages. Its disadvantage is that it
control virtual channel is employed to indicate to the
requires the creation of the time derivatives of I and Q. As
ensemble of PEAs sharing the channel which is to transmit
is well known, precise derivative forming circuits and and
20 at any given time. Still another operational mode occurs
difficult to implement and power consumptive.
when a single virtual channel is used to broadcast informaTo circumvent the disadvantages of derivative forming
tion from PDA to multiple PEAs. While it is possible to
networks and still keep the advantages of the frequency
establish virtual channels between two PEAs, the increased
discrimination scheme, the receiver employs all pass phase
worst case separation possible from one PEA to another PEA
shifters 71, 72, 73 and 74 to create the signals la, Qa, Qb and 25 may preclude establishment of a reliable radio link. ThereQc respectively. Multipliers 75 and 76 together with adder
fore PEA to PEA links are not present in the preferred
77 then form the signal U=la*Qb-Ib*Qa. The advantage is
embodiment. While all these operational modes appear
that U has the same desirable properties of a discriminator
different, they are essentially well known variants to the
based on l*dQ/dt-Q*dI/dt without requiring differentiation.
underlying time division multiple access technique.
It is only required that la and Ib be separated by 90 degrees
TDMA allows an ensemble of PEAs and PDA to establish
and that Qa and Qb be separated by 90 degrees. As is well 30
a wide assortment of non-conflicting, error free, virtual
known, all pass networks consisting of a resistor and capacichannels between PEAs and PDA. When two different
tor can be used to effect this phase separation. These
ensembles of PEAs and PDA happen by chance to employ
networks produce an accurate 90 degree phase separation
the same carrier frequency, it is possible for the RF bursts of
over a frequency range well in excess of the blocking
one ensemble to overlap those of the other ensemble. This
amplifier bandpass and consume extremely low power con- 35
overlap can cause errors. If during a particular bit period,
sumption.
two RF bursts are being simultaneously received, one from
Limiter 78 then amplifies U to form signal Lim. Limiter
a transmitter in the home ensemble and the other from a
circuits which can generate these signals are well known and
foreign ensemble, the receiver will "capture' only the data
have been integrated into integrated receiver chips for many 40 received from the stronger of two transmitters. This well
years. Limiter output Lim is utilized by the controller 43 in
known aspect of FM modulation, results in an error free
both establishing the common time base and in recovering
channel when the stronger transmitter is part of the home
the data transmitted as described in greater detail hereinafter.
ensemble and can result in errors when the stronger transmitter is part of a foreign ensemble. While it is very likely
FRAME STRUCTURE
45 that the stonger transmitter is part of the home ensemble,
there are circumstances in normal operation where the
As indicated previously, the basic scheme for allowing
stonger transmitter will part of a foreign ensemble. Note that
multiple Personal Electronic Assessocies (PEAs) to comeven when a foreign transmitter is of much greater power
municate with the common server microcomputer (PDA)
than the home transmitter, if the foreign RF bursts and home
may be characterized as a form of time division multiple
access (TDMA). A single virtual channel can be established 50 RF burst do not overlap, no error occurs.
between the PDA and anyone PEA by assigning one or more
As is well known, many channel errors can be corrected
slots within the 32.768 millisecond frame. In the preferred
by employing Error Correction Codes (ECC). In this
embodiment, four data bits are transmitted during each slot
technique, data to be sent over a channel is segmented into
interval with the designation of a binary one or zero encoded
words of length M. A checksum of length C is computed as
by means of frequency modulation of the RF carrier as 55 the word is being transmitted and also sent across the
described previously. In slots where a PEA neither transmits
channel. For the M bits of data, a total of N=M+C bits of
nor receives, essentially all of the modem circuits are
channel bandwidth are utilized. For a fixed word length, as
powered off, thus effecting a substantial power reduction. As
the number of error bits which can be corrected increases,
is described in greater detail hereinafter, some slots are used
the channel efficiency decreases. As a general rule, as the
to establish synchronization between PEA and PDA and 60 channel's error rate increase, the channel bandwdith effiothers are used to implement a control channel. These slots
ciency (needed to achieve a certain corrected error rate)
are not assigned to a particular PEA but are rather shared
decreases and the minimum wordsize increases. In one of
amongst all PEAs.
the simplest error correction schemes, called majority
coding, where data bit is transmitted three time (M=1, C=2),
In normal operation, each virtual channel is half duplex,
transfering data either from PEA to PDA or from PDA to 65 channel bandwidth is reduced to 33%.
PEA. Assignment of a single slot per frame results in a
In channels where errors occur in bursts, single error
virtual channel bandwidth of 122 bits per second. Virtual
correction codes, even though they have high channel

6,128,290
7

8

ted by the PDA. Each SB consists of eight RF bursts spread
efficiency, will yield poor after correction error rates. In
out over 252 slots. One of the SBs arbitrarily starts a frame.
interleaving, a well known scheme to handle burst errors,
data is segmented into words which are then interleaved
The positions of the remaining seven SBs are selected
pseudo-randomly with two restrictions. First the maximum
onto the channel. If the maximum error burst consists of four
consecutive errors, then interleaving four words results in 5 interval between two successive SBs is less than 6.144
milliseconds. Secondly, the positions must allow a unique
each burst occuring in a separate codeword. Since each
codeword now has only one error after interleaving, it can be
frame determination based on the intervals between SBs.
Thus for example, equidistantly spaced SBs are not allowed.
corrected.
Yet another means for correcting errors is to packetize the
In accordance with one aspect of the present invention,
data and retransmit on detection of a checksum error. For 10 the slot location of each RF burst within all SBs is identical
for all ensembles. In a particular ensemble, the 32-bit data
virtual channels not requiring low latency, the highest chanbit pattern of each SB will be identical. Between two
nel efficiencies are possible. Hybrid schemes where error
different ensembles, however, the SB data bit pattern, chocorrection codes are employed together with retransmission
of packets on checksum errors are also possible.
sen randomly, will be quasi-distinct. The combination of SB
Error rates caused by the interference of RF bursts 15 data bit pattern and SB locations allow every ensemble to be
uniquely identified.
between two different ensembles can be significantly
In the preferred embodiment illustrated in FIG. 6, each of
reduced by judicious assignment of slots in each ensemble.
One assignment scheme that has desirable properties
the eight SBs 100-107 is immediately followed by a sector
employs majority encoding and the use of so-called Optiassigned to the common Communication and Control Chancally Orthogonal Codes (OOCs). In this scheme, the 16384 20 nel (CCC). The sector immediately following the first seven
CCC sectors is assigned to the Attention Channels (ACs).
slots are equally segmented into 256 intervals called sectors.
The CCC sectors are designated by reference characters
A maximum of three RF bursts can occur in each section.
110-117 in FIG. 6 while the Attention Channels are desigThe position of each burst is dictated by a one in an OOC
nated by reference characters 120--127. As will be explained
codeword. Codewords have unity auto-correlation and
cross-correlation with respect to rotation by an arbitrary 25 in greater detail later, the CCC and AC are used in mainnumber of slot positions within a sector. The codes are
taining the virtual channels between PDA and all PEAs.
mostly zeros with three scattered ones representing the
Referring now to FIG. 7, all PEA activities are activated
locations of the slots in which RF bursts are to be transmitted
and monitored by the PEA controller 43. While the controlor received. There are ten OOC codewords with a sector
ler could be implemented in a single custom integrated
length of 64 slots. In general, a sector can be assigned any 30 circuit, the present embodiment partitions the controller into
one of the ten codewords with a rotation of from zero to 63
a commercially available microprocessor 90, a PICI6C64, a
slot positions.
special purpose logic integrated circuit IC 91, voltage conTo assign slots in an ensemble, one of 640 different
trolled crystal oscillator 44, and a charge pump voltage
combinations of codeword and rotations is selected for the 35 generator 93. Voltage controlled crystal oscillator (VCXO)
first sector. A codeword/rotation combination is selected for
44 is controlled by voltage Vc, sourced by charge pump 93.
the second section such that 1) the last RF burst postion of
The controller IC 91 can cause the frequency of oscillation
the last sector codeword and the two RF burst postions of the
to change by activating charge pump. Varying the control
new codeword do not form a codeword and 2) the last two
voltage Vc from 0 to -6 volts changes the oscillator freRF burst positions of the last sector codeword and the first 40 quency by 50 parts per million. VCXO 44 is powered
RF burst position of the new codeword do not form a
continuously and serves as the time base for all activities.
The microprocessor chip includes 256 bytes of ROM which
codewords, and 3) the codeword/rotation has not been
selected before. Each sector consists of three identical RF
contains the program instructions needed for all activities
bursts (i.e a majority error correcting code is chosen).
and 256-bytes of SRAM used in program execution.
At any instant of time, the frame structures of two 45
The controller IC 91 serves as the primary control agent
ensembles will in general not be aligned. However, with
for all activities. It contains registers, counters, Finite State
their uncorrelated separate time bases, the frame structures
Machines (FSMs), and as will be explained in more detail
will slip past one another and will become aligned. Every
later, a Digital Matched Filter (DMF) used to detect synchronization and attachment beacons, and a 1024x16-bit
possible correlation between the two frames will thus eventually occur. Assuming each ensemble is using 100% of its 50 SRAM used to store the usage sector assignments in the
PEAs TDMA plan. While some of the activites are implebandwidth, then it is highly likely that at some time a
mented without microprocessor intervention, most activities
codeword in each ensemble will be aligned. When codeinvolve the microprocessor execution of short instruction
words from separate ensembles are aligned, a receiver
sequences. Normally, the microprocessor clock, sourced by
captures data from the stronger transmitter. In this case, the
error correction coding serves no value since it perfectly 55 controller IC 91 is inactive, thus reducing power consumpcorrects the data of the foreign transmitter. When this
tion. When microprocessor intervention is required, controlcondition occurs, the probability that another sector is also
ler IC 91 activates the microprocessor clock and issues an
aligned is about 0.002. Thus one sees a worst case uncor8-bit code over the interconnecting bus to indicate what
rectible error rate of about 0.001. As is well known, this
activity the microprocessor is to perform. When the microuncorrectible error rate is sufficiently low that, by employing 60 processor has completed its program sequence, it issues a
packetizing and retransmitting on checksum errors, an effeccode to controller IC 91 indicating completion. Controller
tively error free channel can be obtained.
IC 91 then inactivates the microprocessor clock returning
the micrprocessor into its minimum power consumption
As will be understood by those skilled in the art, the
state.
TDMA system is greatly facilitated by the establishment of
To reduce power consumption by the controller IC 91,
a common frame time base between PEA and PDA. In 65
establishing this common time base, the present invention
only a very small percentage of the logic is clocked conemploys timing or synchronization beacons (SBs) transmittinuously. Clocks to all remaining sections of controller IC

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91 are enabled only when required. As is common practice
receive additional AB each within a 6 millisecond period of
the previously received AB. This succession of ABs forms
in low power designing, the supply voltage of all internal
logic is reduced to one volt and implemented with special
an HDLC channel using bit-stuffing to delineate the beginlow voltage cell designs.
ning and end of a packet.
A single packet of information (the Attachment Packet) is
The PEA controller 43 operates in one of three major 5
transmitted over and over by the PDA during the attachment
states: Unattached (U), Sleep (S), and Active (A). These
procedure, interleaved with the Synchronization Beacons.
states and the state change conditions are described below.
This packet contains all information needed to establish a
In the Unattached state, the controller has not been
Command and Control Channel (CCe) connection between
personalized by any particular PDA. It cannot function
normally until it receives information contained in an attach- 10 the PEA's microprocessor and the PDA's microprocessor.
The packet contains the Synchronization Beacon code, the
ment packet. This packet is sent over a communications link
Synchronization Beacon interval spacings, and a 6-bit idenformed when the PDA modem broadcasts Attachment Beatification number issued to each PEA. A 16-bit checksum at
cons in response to the user's request. An Attachment
the end of the packet allows the PEA to verify correct packet
Beacon (AB) is composed of RF bursts having the same
interval spacings as Synchronization Beacons but with a 15 receipt. Total packet length, including the 8-bit start of
packet flag is 84 bits. Receipt of an Attachment Packet thus
particular bit pattern.
requires a worst case of 0.69 seconds. Once an Attachment
A pair of Digital Matched Filters (DMFs) implemented in
Packet has been received, the PEA enters the Sleep state.
controller I C 91 are the primary means for both receiving the
In this state, the PEA has sufficient information to synattachment packet and for establishing synchronization. As 20
chronize itself to the Synchronization Beacons (SB) norshown in FIG. 8, each DMF is composed of 1032-bit shift
mally broadcast by the PDA. It can synchronize itself to the
register 100, 32-bit DMF Target register 101,
home PDA since it has the Synchronization Beacon bit
32-comparitors 102-133, a 32-input adder 134, and two
pattern and the intervals between Synchronization Beacons.
6-bit comparitors 135 and 136. Limiter 78 output sources
In the Sleep state, a PEA initiates a Synchronization
data to each DMF. One DMF is clocked on the positive edge 25
Beacon search procedure every 8 seconds. This procedure is
of a 2 MHz clock derived from VCXO 44 while the other is
identical to that employed in attachment except that the
clocked on the negative edge. Each of the 32-taps on the
Synchronization Beacon code contained in the Attachment
shift register correspond to bit locations of Syncronization
Packet is stored in the DMF Target Registers. If a Synchroand Attachement Beacons. The 32-bits from the shift register
nization Beacon is not detected within 6.144 milliseconds, it
are compared, bit for bit by exnor gates 102-133 with the
target bit beacon bit-sequence held in DMF Target Register 30 is assumed that the home PDA is not near enough for
synchronization to proceed. It then powers off all circuits
101. Adder 134 sums the number of comparitor matches. A
except the alarm clock circuits which reinitiates the Synsum equal to zero indicates that each shift register tap is
chronization Beacon search procedure 8 seconds later.
exactly the compliment of the DMF Target Register 101
while a sum equal to thirty-two indicates that each shift 35
Once a single Synchronization Beacon is detected, the
PEA assumes that its home PDA is nearby and that it should
register tap exactly matches the corresponding bit in the
DMF Target Register 101. As is understood by those skilled
acquire synchronization. It acquires synchronization in two
in the data communications arts, a more robust detection
stages. When the first Synchronization Beacon is detected, a
14-bit counter is cleared. This counter, clocked at the slot
scheme results when detection allows a few errors to occur
rather than requiring a perfect match. Accordingly, compari- 40 clock rate, then continues counting.
tor 135 detects a match when the sum is greater or equal to
When the next Synchronization Beacon is detected, the
thirty while comparitor 136 detects an unmatch when the
upper 8-bits of the counter are stored in an interval register
sum is less than or equal to two.
and the upper 6-bits of the counter are cleared. The lower
6-bits are then compared against zero. Under worst case
At the end of each 500 nanosecond bit period, the two
DMF's thus indicate one of three conditions, target match, 45 clock tolerance, the low 6-bit value should be zero plus or
minus 0.25 clock periods. If the low order counter bits are
target compliment match, and no match. The DMF can thus
zero no action is taken. Charge pump 93 is activated to
form a communications channel between transmitter and
increase the VCXO frequency. The interval is compared
receiver without the receiver being synchronized to the
against each of the seven interval values loaded in the
transmitter in the manner utilized after attachment, i.e. after
the PEA has become part of the ensemble. A target match 50 Attachment Packet, no two of which are identical.
indicates a logic' one' and digit received condition while a
After the third Synchronization Beacon is detected, the
target compliment match indicates a logic 'zero' and digit
process is repeated. This time, the interval is compared
received condition. With eight Attachment Beacons transagainst the next interval in the Synchronization Beacon
mitted per frame, an asynchronous 244 bit per second
interval table with the assumed framing established from the
communications channel can be formed between the PDA 55 first interval. Again the charge pump is activated to increase
and an unattached PEA by detecting these Attachment
the VCXO frequency if needed. This process of comparing
Beacons or their compliments.
intervals and adjusting the crystal oscillator continues until
the PEA has a reliable indication that framing has been
An Unattached PEA initiates an Attachment Beacon
established and that the crystal oscillator frequency is very
search procedure every 8 seconds. In this procedure, the
controller enables the DMF to detect Attachment Beacons. 60 close to that of the PDA. When this occurs the second phase
of synchronization, called phase alignment, is entered.
It allows the search to continue, attempting to match the
attachment bit pattern (or its compliment) every 250 nanoIn the phase alignment stage, the first four bursts of the
seconds. If no Attachment Beacon is detected during a
Synchronization Beacon are used to adjust the phase of the
search period of 6.144 milliseconds the PEA terminates the
VCXO. The bit pattern of the first four bursts of all Synsearch and reenters its low power condition until the next 65 chrnonization Beacons is either 0011 or 1100. This simplisearch is initiated. When an Attachment Beacon AB or its
fies the phase adjustment process. VCXO frequency adjustcompliment is detected, it then expects to quasi-periodically
ment is one sided in that BCC can only increase frequency

6,128,290
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via the charge pump. Leakage currents in the charge pump
from the user or output information to the user, and
cause the frequency to decrease. Thus by monitoring the
which are adapted to operate within short range of said
percentage of time that the Syncronization Beacon transiserver unit;
tions are ahead or behind the 2 MHz bit clock, the microsaid server microcomputer incorporating an RF transmitprocessor can determine when synchronization is estab- 5
ter for sending commands and synchronizing informalished.
tion to said peripheral units;
After the PEA acquires synchronization, it sends a status
said peripheral units each including an RF receiver for
code over the Attention Channel assigned to that PEA.
detecting said commands and synchronizing informaEach frame contains seven sectors assigned to Attention
tion and including also an RF transmitter for sending
Channel groups. These sectors follow the sectors assigned to 10
input information from the user to said server microthe Command and Control Channel sectors which immedicomputer;
ately follow the eight Synchrnonization Beacons. Eight
successive frames provide a total of 56 Attention Channels,
said server microcomputer including a receiver for receivone for each of the 56 possible PEAs. After the PEA acquires
ing input information transmitted from said peripheral
synchronization, it sends a status code over the Attention 15
units;
Channel assigned to the PEA indicating that it has just
said server and peripheral transmitters being energized in
acquired synchronization and is requesting activation. Each
low duty cycle RF bursts at intervals determined by a
PEA is required to send a status code in its respective
code sequence which is timed in relation to said synAttention Channel once every eight frames. The PEA and
chronizing information.
PDA microprocessors then go through a protocol which
2. A data network system as set forth in claim 1 wherein
checks that the PEAs TDMA plan is current. If the PEA's 20
said server and peripheral units are allocated respective time
TDMA plan is not current, the PDA then loads the new
slots within a predetermined frame interval for transmitting.
TDMA plan into the PEA's TDMA memory and enables the
3. A data network system as set forth in claim 2 wherein
PEA to enter the Active state.
a code sequence for a given one of said units is transmitted
The basic unit of the TDMA plan is a User Data Inforwithin a respective time slot.
mation Block (UDIB). Each UDIB contains 12 bits. When 25
4. A data network system as set forth in claim 1 wherein
no error encoding is employed, each UDIB nets 12 user data
said server microcomputer unit transmits RF synchronizing
bits. Majority error correction coding, where the sector
beacons at times within each of a predetermined sequence of
contains three identical copies of the same RF burst nets four
frames which times vary in accordance with a code unique
error corrected data bits. Majority coding is employed on all
to the particular server microcomputer unit.
sectors comprising both the Command and Control Channel 30
5. Adata network system for effecting coordinated operaand Attention Channels.
tion of a plurality of electronic devices, said system comOn entry to the Active state, the PEA initializes registers
prising:
and waits until the beginning of the next frame. At that time,
a server microcomputer;
it accesses its TDMA control memory, resident in the 35
a plurality of peripheral units which are battery powered
1024x16 BCC SRAM, to determine 1) when it should
and portable, which provide either input information
transmit or receive data, 2) which sub-channel, and 3) which
from the user or output information to the user, and
error correction to apply. The data then being transmitted
which are adapted to operate within about 20 meters of
and received by each PEA will then depend on its applicasaid server unit;
tion or function within the ensemble, e.g. as a sensor, 40
said server microcomputer incorporating an RF transmitactuator or other type of component.
ter for sending commands and synchronizing informaAs will be understood by those skilled in the art, the use
tion to said peripheral units during allocated time slots
of sparse codes, pseudorandomly selected, together with
within an overall time frame;
error correction coding, renders the data communication
said peripheral units including an RF receiver for detectprovided by the present invention highly reliable and rela- 45
ing said commands and synchronizing information and
tively unsusceptible to interference from similar networks
including also an RF transmitter for sending input
operating nearby. Further, the utilization of low duty cycle
information from the user to said server microcomputer
pulse mode transmission particularly with the employment
during respective allocated time slots within said overof uncorrelated codes in a TDMA context, leads to very low
all time frame;
power consumption since the transmitters and receivers in 50
said server microcomputer including a receiver for receiveach PEA are powered for only a small percentage of the
ing input information transmitted from said peripheral
total time.
units;
In view of the foregoing it may be seen that several
objects of the present invention are achieved and other
said server and peripheral transmitters being energized in
advantageous results have been attained.
low duty cycle pulses at pseudo-random intervals
55
within each of said allocated time slots, said pseudoAs various changes could be made in the above construcrandom intervals being determined by a code sequence
tions without departing from the scope of the invention, it
which is timed in relation to said synchronizing inforshould be understood that all matter contained in the above
mation.
description or shown in the accompanying drawings shall be
6. Adata network system for effecting coordinated operainterpreted as illustrative and not in a limiting sense.
60
tion of a plurality of electronic devices, said system comWhat is claimed is:
prising:
1. Adata network system for effecting coordinated operation of a plurality of electronic devices, said system coma server microcomputer unit, said server unit including an
prising:
oscillator for establishing a time base;
a server microcomputer unit;
a plurality of peripheral units which are battery powered
65
and portable and which provide either input informaa plurality of peripheral units which are battery powered
and portable, which provide either input information
tion from the user or output information to the user;

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said server microcomputer incorporating an RF transmitter controlled by said oscillator for sending commands
and synchronizing information to said peripheral units;
said peripheral units each including an RF receiver for
detecting said commands and synchronizing information and including also a local oscillator which can be
synchronized to said server unit oscillator using said
synchronizing information and an RF transmitter controlled by said local oscillator for sending input information from the user to said server microcomputer;
said server microcomputer including a receiver controlled
by said server unit oscillator for receiving input information transmitted from said peripheral units;
said server and peripheral transmitters being energized in
low duty cycle RF bursts which are timed in relation to
said synchronizing information.
7. A data network system as set forth in claim 6 wherein
said server and peripheral units are allocated respective time
slots within a predetermined frame interval for transmitting.
8. A data network system as set forth in claim 6 wherein
said input and output information is carried by frequency
modulation of the respective transmitters and the receivers
employ the respective oscillators for detecting the frequency
modulation.
9. Adata network system for effecting coordinated operation of a plurality of electronic devices, said system comprising:
a server microcomputer unit, said server unit including an
oscillator for establishing a time base;
a plurality of peripheral units which provide either input
information from the user or output information to the
user, and which are adapted to operate within about 20
meters of said server unit;
said server microcomputer incorporating an RF transmitter controlled by said oscillator for sending commands
and synchronizing information to said peripheral units,
said synchronizing information being carried by time
spaced beacons characteristic of the particular server
unit;
said peripheral units each including an RF receiver for
detecting said commands and synchronizing information and including also a local oscillator, each of said
peripheral units being operative in a first mode to
receive said beacons independently of synchronization
of the respective local oscillator when that peripheral
unit is in close proximity to said server unit and to
determine from the server unit its characteristics, each
of said peripheral units being operative in a second
mode to synchronize the respective local oscillator with

the server unit oscillator, each of said peripheral units
also including an RF transmitter operative in a third
mode for sending input information from the user to
said server microcomputer,
said server microcomputer including a receiver for receiving input information transmitted from said peripheral
units;
said server and peripheral transmitters being energized in
low duty cycle RF bursts at intervals with said receivers
being controlled by the respective oscillators.
10. Adata network system as set forth in claim 9 wherein
said server and peripheral units are allocated respective time
slots within a predetermined frame interval for transmitting.
11. A data network system for effecting coordinated
operation of a plurality of electronic devices, said system
comprising:
a server microcomputer unit, said server unit including an
oscillator for establishing a time base;
a plurality of peripheral units which provide either input
information from the user or output information to the
user;
said server microcomputer incorporating an RF transmitter controlled by said oscillator for sending commands
and synchronizing information to said peripheral units,
said synchronizing information being carried by time
spaced beacons;
said peripheral units each including an RF receiver for
detecting said commands and synchronizing information and including also an RF transmitter for sending
input information from the user to said server microcomputer;
said server microcomputer including a receiver for receiving input information transmitted from said peripheral
units, said server microcomputer unit being operative
to define a TDMA plan in which said server and
peripheral units are allocated respective time slots
within a predetermined frame interval for transmitting;
each of said peripheral units being operative in a first
mode to receive said beacons from said server unit
independently of synchronization of the respective
local oscillator when the peripheral unit is in close
proximity to the server unit and to determine the
respective TDMA plan, each of said peripheral units
being operative in a second mode to exchange input
and output information with said server unit in accordance with the determined TDMA plan.

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