Nokia Corporation v. Apple Inc.

Filing 59

Claims Construction Initial Brief re: 58 Motion Requesting Claims Construction by Plaintiff Nokia Corporation, Counter Defendant Nokia Inc. (Attachments: # 1 Exhibit 1.U.S. Patent No. 5,946,647, # 2 Exhibit 2.U.S. Patent No. 5,612,719, # 3 Exhibit 3.Excerpts from Helander, Martin et. al, Handbook of Human-Computer Interaction 2nd Ed. (1997), # 4 Exhibit 4.Nokia N900 Device Details webpage, # 5 Exhibit 5.Excerpts from Nokia N900 User Guide, # 6 Exhibit 6.Nokia N8 Device Details webpage, # 7 Exhibit 7.Excerpts from Nokia N8 User Guide, # 8 Exhibit 8.Excerpts from The American Heritage Dictionary of the English Language (1976), # 9 Exhibit 9.U.S. Patent No. 5,398,310, # 10 Exhibit 10.U.S. Patent No. 5,588,105, # 11 Exhibit 11.U.S. Patent No. 5,523,775, # 12 Exhibit 12.Office Action issued during prosecution of the 719 Patent dated September 7, 1994, # 13 Exhibit 13.U.S. Patent No. 4,139,837, # 14 Exhibit 14.Response to Office Action filed during prosecution of the 719 Patent dated October 24, 1994, # 15 Exhibit 15.Office Action issued during prosecution of the 719 Patent dated April 9, 1996, # 16 Exhibit 16.U.S. Patent No. 5,347,295, # 17 Exhibit 17.Response to Office Action filed during prosecution of the 719 Patent dated July 9, 1996, # 18 Exhibit 18.U.S. Patent No. 7,760,559, # 19 Exhibit 19.Declaration of Dr. David T. Blaauw dated December 17, 2010, # 20 Exhibit 20.Intel PXA27x Processor Family Datasheet (2005), # 21 Exhibit 21.Intel PXA27x Processor Family Developers Manual (April 2004), # 22 Exhibit 22.Office Action issued during prosecution of the 559 Patent dated September 10, 2007, # 23 Exhibit 23.Response to Office Action filed during prosecution of the 559 Patent dated November 29, 2007, # 24 Exhibit 24.U.S. Patent No. 7,380,116, # 25 Exhibit 25.Office Action issued during prosecution of the 116 Patent dated April 20, 2007, # 26 Exhibit 26.Amendment filed during prosecution of the 116 Patent dated July 20, 2007, # 27 Exhibit 27.Declaration of William C. Simpson dated December 16, 2010, # 28 Exhibit 28.Excerpts from Websters 9th New Collegiate Dictionary (1983), # 29 Exhibit 29.U.S. Patent No. 7,054,981, # 30 Exhibit 30.Office Action issued during prosecution of the 981 Patent dated November 5, 2004, # 31 Exhibit 31.Amendment A filed during prosecution of the 981 Patent dated March 4, 2005, # 32 Exhibit 32.Amendment B filed during prosecution of the 981 Patent dated August 19, 2005, # 33 Exhibit 33.Patent Examiners Amendment and Interview Summary issued during prosecution of the 981 Patent dated December 28, 2005, # 34 Exhibit 34.U.S. Patent No. 7,532,680, # 35 Exhibit 35.U.S. Patent No. 5,117,201, # 36 Exhibit 36.U.S. Statutory Invention Registration H965, # 37 Exhibit 37.CML Semiconductor Products FX009A Datasheet (July 1994), # 38 Exhibit 38.Analog Devices AD8320 Datasheet (1998), # 39 Exhibit 39.U.S. Patent No. 5,752,172, # 40 Exhibit 40.U.S. Patent No. 6,603,431, # 41 Exhibit 41.U.S. Patent No. 6,348,894, # 42 Exhibit 42.Excerpt from The Compact Edition of the Oxford English Dictionary, Vol. 1 (1971), # 43 Exhibit 43.U.S. Patent No. 6,317,083, # 44 Exhibit 44.U.S. Patent No. 7,558,696) (Newton, Michael) Modified docket text on 12/20/2010 (jas).

Nokia Corporation v. Apple Inc.

Doc. 59 Att. 20

EXHIBIT 20

Dockets.Justia.com

Intel® PXA27x Processor Family
Electrical, Mechanical, and Thermal Specification

Data Sheet

High-performance processor: -- Intel XScale® microarchitecture with Intel® Wireless MMXTM Technology -- 7 Stage pipeline -- 32 KB instruction cache -- 32 KB data cache -- 2 KB "mini" data cache -- Extensive data buffering 256 Kbytes of internal SRAM for high speed code or data storage preserved during low-power states High-speed baseband processor interface (Mobile Scalable Link) Rich serial peripheral set: -- AC'97 audio port -- I2S audio port -- USB Client controller -- USB Host controller -- USB On-The-Go controller -- Three high-speed UARTs (two with hardware flow control) -- FIR and SIR infrared communications port Hardware debug features -- IEEE JTAG interface with boundary scan Hardware performance-monitoring features with on-chip trace buffer Real-time clock Operating-system timers LCD Controller Universal Subscriber Identity Module interface

Low power: -- Wireless Intel Speedstep® Technology -- Less than 500 mW typical internal dissipation -- Supply voltage may be reduced to 0.85 V -- Four low-power modes -- Dynamic voltage and frequency management High-performance memory controller: -- Four banks of SDRAM: up to 104 MHz @ 1.8 V I/O interface -- Six static chip selects -- Support for PCMCIA and Compact Flash -- Companion chip interface Flexible clocking: -- CPU clock from 104 to 520 MHz -- Flexible memory clock ratios -- Frequency changes -- Functional clock gating Additional peripherals for system connectivity: -- SD Card/MMC Controller (with SPI mode support) -- Memory Stick card controller -- Three SSP controllers -- Two I2C controllers -- Four pulse-width modulators (PWMs) -- Keypad interface with both direct and matrix keys support -- Most peripheral pins double as GPIOs

Order Number 280003-004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. In tel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA27x processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Ale rtVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyrigh t © Intel Corporation, 2005. All Rights Reserved.

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Contents

Contents
1 Introduction ......................................................................................................... 1-1 1.1 About This Document ................................................................................. 1-1 1.1.1 Number Representation ................................................................ 1-1 1.1.2 Typographical Conventions...........................................................1-1 1.1.3 Applicable Documents...................................................................1-2

2 3

Functional Overview ........................................................................................... 2-1 Package Information ........................................................................................... 3-1 3.1 3.2 3.3 3.4 3.5 3.6 Package Information .................................................................................. 3-1 Processor Materials....................................................................................3-2 Junction To Case Temperature Thermal Resistance ................................. 3-3 Processor Markings....................................................................................3-3 Intel® PXA27x Processor Family Identification Markings .......................... 3-5 Tray Drawing .............................................................................................. 3-5 Ball Map View.............................................................................................4-2 4.1.1 1.8V SCSP Ball Map ..................................................................... 4-2 Intel® PXA27x Processor Family Mapping Tables.....................................4-7 4.2.1 Intel® PXA271 Processor (1x256Mbit(x16) Flash and 1x256Mbit(x16) SDRAM - 1.8V)....................................................4-7 4.2.2 PXA272 Processor (2x256 Mbit(x32) (x16 each die) Flash - 1.8V)................................................................................4-10 Pin Usage.................................................................................................4-13 Signal Types.............................................................................................4-27 Memory Controller Reset and Initialization...............................................4-28 Power-Supply Pins ................................................................................... 4-29 Absolute Maximum Ratings........................................................................5-1 Operating Conditions..................................................................................5-1 Power-Consumption Specifications............................................................5-6 DC Specification.........................................................................................5-6 Oscillator Electrical Specifications..............................................................5-7 5.5.1 32.768-kHz Oscillator Specifications ............................................. 5-7 5.5.2 13.000-MHz Oscillator Specifications............................................5-8 CLK_PIO and CLK_TOUT Specifications .................................................. 5-9 48 MHz Output Specifications ..................................................................5-10 AC Test Load Specifications ...................................................................... 6-1 Reset and Power Manager Timing Specifications......................................6-2 6.2.1 Power-On Timing Specifications ................................................... 6-2 6.2.2 Hardware Reset Timing.................................................................6-4 6.2.3 Watchdog Reset Timing ................................................................ 6-5 6.2.4 GPIO Reset Timing ....................................................................... 6-5

4

Pin Listing and Signal Definitions ..................................................................... 4-1 4.1 4.2

4.3 4.4 4.5 4.6 5 5.1 5.2 5.3 5.4 5.5

Electrical Specifications ..................................................................................... 5-1

5.6 5.7 6 6.1 6.2

AC Timing Specifications...................................................................................6-1

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6.3 6.4

6.5 6.6 6.7

6.2.5 Sleep Mode Timing ....................................................................... 6-6 6.2.6 Deep-Sleep Mode Timing..............................................................6-7 6.2.7 Standby-Mode Timing ................................................................. 6-10 6.2.8 Idle-Mode Timing.........................................................................6-10 6.2.9 Frequency-Change Timing..........................................................6-10 6.2.10 Voltage-Change Timing...............................................................6-11 GPIO Timing Specifications ..................................................................... 6-11 Memory and Expansion-Card Timing Specifications................................6-12 6.4.1 Internal SRAM Read/Write Timing Specifications ....................... 6-12 6.4.2 SDRAM Parameters and Timing Diagrams.................................6-12 6.4.3 ROM Parameters and Timing Diagrams ..................................... 6-18 6.4.4 Flash Memory Parameters and Timing Diagrams.......................6-23 6.4.5 SRAM Parameters and Timing Diagrams ................................... 6-33 6.4.6 Variable-Latency I/O Parameters and Timing Diagrams.............6-36 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams.....6-40 LCD Timing Specifications ....................................................................... 6-43 SSP Timing Specifications ....................................................................... 6-44 JTAG Boundary Scan Timing Specifications............................................6-45

Glossary .............................................................................................................Glossary-1

Figures
2-1 Intel® PXA27x Processor Family Block Diagram, Typical System .................... 2-2 3-1 14 x 14 mm Intel® PXA27x Processor Family Package, Top View ................... 3-1 3-2 14 x 14 mm Intel® PXA27x Processor Family Package, Top View ................... 3-2 3-3 14 x 14-mm Intel® PXA27x Processor Family Package, Side View .................. 3-2 3-4 Processor Markings, Intel® PXA27x Processor Family ..................................... 3-4 3-5 Intel® PXA27x Product Information Decoder.....................................................3-4 4-1 1.8V Intel® PXA27x Processor Family Ball Map, Top Left Quarter ................... 4-3 4-2 1.8V Intel® PXA27x Processor Family Ball Map, Top Right Quarter.................4-4 4-3 1.8V Intel® PXA27x Processor Family Ball Map, Bottom Left Quarter .............. 4-5 4-4 1.8V Intel® PXA27x Processor Family Ball Map, Bottom Right Quarter............4-6 6-1 AC Test Load ..................................................................................................... 6-2 6-2 Power On Reset Timing ..................................................................................... 6-3 6-3 Hardware Reset Timing ..................................................................................... 6-4 6-4 GPIO Reset Timing ............................................................................................ 6-5 6-5 Sleep Mode Timing ............................................................................................ 6-7 6-6 Deep-Sleep-Mode Timing .................................................................................. 6-8 6-7 SDRAM Timing ................................................................................................ 6-15 6-8 SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing............................6-16 6-9 SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing ............... 6-17 6-10 SDRAM Fly-by DMA Timing.............................................................................6-18 6-11 32-Bit Non-burst ROM, SRAM, or Flash Read Timing ..................................... 6-20 6-12 32-Bit Burst-of-Eight ROM or Flash Read Timing ............................................ 6-21 6-13 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing ......... 6-22 6-14 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing .................................... 6-23 6-15 Synchronous Flash Burst-of-Eight Read Timing .............................................. 6-26 6-16 Synchronous Flash Stacked Burst-of-Eight Read Timing ................................ 6-27 6-17 First-Access Latency Configuration Timing......................................................6-28

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6-18 Synchronous Flash Burst Read Example.........................................................6-30 6-19 32-Bit Flash Write Timing ................................................................................. 6-31 6-20 32-Bit Stacked Flash Write Timing ................................................................... 6-32 6-21 16-Bit Flash Write Timing ................................................................................. 6-33 6-22 32-Bit SRAM Write Timing ...............................................................................6-35 6-23 16-bit SRAM Write for 4/2/1 Byte(s) Timing ..................................................... 6-36 6-24 32-Bit VLIO Read Timing ................................................................................. 6-38 6-25 32-Bit VLIO Write Timing..................................................................................6-39 6-26 Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41 6-27 Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42 6-28 LCD Timing Definitions.....................................................................................6-43 6-29 SSP Master Mode Timing Definitions...............................................................6-44 6-30 Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral...........................................................................................6-44 6-31 Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral...........................................................................................6-45 6-32 JTAG Boundary-Scan Timing...........................................................................6-46

Tables
1-1 Supplemental Documentation ............................................................................ 1-2 3-1 Intel® PXA27x Processor Family Package Information ..................................... 3-2 3-2 Intel® PXA27x Processor Family ID Markings ................................................... 3-5 4-1 1x256Mbit(x16) Flash and 1x256Mbit(x16) SDRAM - 1.8V ............................... 4-7 4-2 2x256 Mbit(x32) (x16 each die) Flash - 1.8V ................................................... 4-10 4-3 SCSP Pin Usage Summary..............................................................................4-13 4-4 Pin Usage and Mapping Notes.........................................................................4-27 4-5 Signal Types.....................................................................................................4-28 4-6 Memory Controller Pin Reset Values ............................................................... 4-28 4-7 SCSP 1.8V Power Supply Pin Summary ......................................................... 4-29 5-1 Absolute Maximum Ratings................................................................................5-1 5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2 5-3 Memory Voltage and Frequency Electrical Specifications ................................. 5-4 5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4 5-5 Internally Generated Power Domain Descriptions ............................................. 5-5 5-6 Core Voltage Specifications For Lower Power Modes ....................................... 5-6 5-7 Standard Input, Output, and I/O Pin DC Operating Conditions .......................... 5-6 5-8 Typical 32.768-kHz Crystal Requirements ......................................................... 5-7 5-9 Typical External 32.768-kHz Oscillator Requirements ...................................... 5-8 5-10 Typical 13.000-MHz Crystal Requirements........................................................5-9 5-11 Typical External 13.000-MHz Oscillator Requirements......................................5-9 5-12 CLK_PIO Specifications ................................................................................... 5-10 5-13 CLK_TOUT Specifications ...............................................................................5-10 5-14 48 MHz Output Specifications .......................................................................... 5-10 6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions .......................... 6-1 6-2 Power-On Timing Specifications(OSCC[CRI] = 0) ............................................. 6-3 6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) .................................. 6-4 6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) ................................. 6-5 6-5 GPIO Reset Timing Specifications ..................................................................... 6-6 6-6 Sleep-Mode Timing Specifications ..................................................................... 6-7 6-7 Deep-Sleep Mode Timing Specifications ........................................................... 6-8

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Contents

6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode ................................. 6-9 6-9 Standby-Mode Timing Specifications ............................................................... 6-10 6-10 Idle-Mode Timing Specifications ...................................................................... 6-10 6-11 Frequency-Change Timing Specifications ....................................................... 6-10 6-12 Voltage-Change Timing Specification for a 1-Byte Command.........................6-11 6-13 GPIO Timing Specifications ............................................................................. 6-11 6-14 SRAM Read/Write AC Specification ................................................................ 6-12 6-15 SDRAM Interface AC Specifications ................................................................ 6-13 6-16 ROM AC Specification ..................................................................................... 6-18 6-17 Synchronous Flash Read AC Specifications....................................................6-24 6-18 Flash Memory AC Specification ....................................................................... 6-30 6-19 SRAM Write AC Specification .......................................................................... 6-34 6-20 VLIO Timing ..................................................................................................... 6-37 6-21 Expansion-Card Interface AC Specifications ................................................... 6-40 6-22 LCD Timing Specifications ............................................................................... 6-43 6-23 SSP Master Mode Timing Specifications ......................................................... 6-44 6-24 Timing Specification for SSP Slave Mode Transmitting Data to External Peripheral...........................................................................................6-45 6-25 Timing Specification for SSP Slave Mode Receiving Data from External Peripheral...........................................................................................6-45 6-26 Boundary Scan Timing Specifications..............................................................6-45

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Revision History
§§
Date April 2004 June 2004 Revisio n -0 0 1 -0 0 2 Description First public release of the EMTS Re-release at same time as Intel® PXA270 Processor EMTS Modified Watchdog Reset timing description Chapter 6, "Reset and Power Manager Timing Specifications" June 2004 -0 0 3 Corrected 13MHz Oscillator slew rate specification Chapter 5, "Oscillator Electrical Specifications" Updated title reference to the Stacked Memory data sheet "Intel® PXA27x Processor Family Memory Subsystem Datasheet" Chapter 5, "Oscillator Electrical Specifications" Removed PXA273 details from this datasheet Modified PXA27x Processor Family Package top view, Chapter 3, "Package Information" Added note to VCC_BB voltage specifications, Chapter 5, "Electrical Specifications" April 2005 -0 0 4 Modified Core Voltage and Frequency Electrial Specifications, Chapter 5, "Electrical Specifications" Modified SDRAM Interface AC Specificatons ,Chapter 6, "AC Timing Specifications" Modified description about the basic material properties of the processor components,Chapter 3, "Package Information"

§§

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x

Electrical, Mechanical, and Thermal Specification

Introduction

1

The Intel® PXA27x Processor Family (referred to throughout this document as the Intel PXA27x processor family) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances in mobile technology over its predecessor, the Intel® PXA255 processor. The Intel PXA27x processor family redefines scalability by operating from 13 MHz up to 520 MHz, providing enough performance for the most demanding mobile applications. The Intel PXA27x processor family is the first Intel processor to include Intel® Wireless MMXTM technology, enabling high-performance, low-power multimedia acceleration with a generalpurpose instruction set. Intel® Quick Capture technology provides a flexible and powerful camera interface for capturing digital images and video. While performance is key in the Intel PXA27x processor family, power consumption is also a critical component. The new capabilities of Wireless Intel SpeedStep® technology set the standard for low-power consumption. The Intel PXA27x processor family is available in both discrete and stacked versions in the following configurations:

· Intel® PXA271 processor (Intel PXA271 processor )with 32 MBytes of Intel StrataFlash®
Memory and 32 MBytes of Low-Power SDRAM Memory

· Intel® PXA272 processor (Intel PXA272 processor) with 64 MBytes of Intel StrataFlash®

1.1

About This Document
This document constitutes the electrical, mechanical, and thermal specifications for the Intel PXA27x processor. It contains a functional overview, mechanical data, package signal locations, targeted electrical specifications, and functional bus waveforms. For detailed functional descriptions other than parametric performance, refer to the Intel® PXA27x Processor Family Developers Manual.

1.1.1

Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in hexadecimal and 0b110_1011 in binary.

1.1.2

Typographical Conventions
All signal and register-bit names appear in uppercase. Active low items are prefixed with a lowercase "n". Bits within a signal name are enclosed in angle brackets: EXTERNAL_ADDRESS<31:0> nCS<1>

Electrical, Mechanical, and Thermal Specification

1-1

Intel® PXA27x Processor Family Introduction

Bits within a register bit field are enclosed in square brackets: REGISTER_BITFIELD[3:0] REGISTER_BIT[0] Single-bit items have either of two states:

· clear -- the item contains the value 0b0. To clear a bit, write 0b0 to it. · set -- the item contains the value 0b1. To set a bit, write 0b1 to it.

1.1.3

Applicable Documents
Table 1-1 lists supplemental information sources for the Intel PXA27x processor family. Contact an Intel representative for the latest document revisions and ordering instructions.

Table 1-1. Supplemental Documentation
Do cu ment Title Intel® PXA27x Processor Family Developers Manual ARM® Architecture Version 5T Specification (Document number ARM* DDI 0100D-10), and ARM ® Architecture Reference Manual (Document number ARM* DDI 0100B) Intel® XScaleTM Core Developer's Manual Intel® Wireless MMXTM Technology Developer's Guide Intel® PXA27x Processor Design Guide Intel® PXA27x Processor Power Supply Requirements Application Note Intel® PXA27x Processor Family Memory Subsystem Datasheet

§§

1-2

Electrical, Mechanical, and Thermal Specification

Functional Overview

2

The Intel PXA27x processor family is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices. It incorporates the Intel XScale® technology which complies with the ARM* version 5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer's model. The Intel PXA27x processor family also provides Intel® Wireless MMXTM media enhancement technology, which supports integer instructions to accelerate audio and video processing. In addition, it incorporates Wireless Intel Speedstep® Technology, which provides sophisticated power management capabilities enabling excellent MIPs/mW performance. The Intel PXA27x processor family provides a scalable, bi-directional data interface to a cellular baseband processor, supporting seven logical channels and other features. The operating-system (OS) timer channels and synchronous serial ports (SSPs) also accept an external network clock input so that they can be synchronized to the cellular network. The processor also provides a Universal Subscriber Identity Module* (USIM) card interface. The Intel PXA27x processor memory interface gives designers flexibility as it supports a variety of external memory types. The processor also provides four 64 kilobyte banks of on-chip SRAM, which can be used for program code or multimedia data. Each bank can be configured independently to retain its contents when the processor enters a low-power mode. An integrated LCD panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. A 256-byte palette RAM provides flexible color mapping. A set of serial devices and general-system resources offers computational and connectivity capability for a variety of applications. Figure 2-1 shows the block diagram for a typical Intel PXA27x processor system.

Electrical, Mechanical, and Thermal Specification

2-1

Intel® PXA27x Processor Family Functional Overview

Figure 2-1. Intel® PXA27x Processor Family Block Diagram, Typical System
LCDC D L

R TC RT C OSSTimers O Tim ers
AAddeess andDa ta BBus d d r r ss a n d Data us

44xx PWM PWM Inte rrupt I nterru pt Connrtoo l le r C ot r ller 33xxSSP SSP USSIM U IM I2S I2S Pe iiphea l Bus Perrp h erralBus AC 997 AC 7

Int r r L CameeanalIn tern al LCD CD C trol r r Sa AM I nter fRce SR AM onC onlteol ler

Memory Memory Controller Controller Addrr es s Add ess and and Data Data Variia be Var ablle Lattency I/O La ency I/O Control Control

Gene a l Purpose /O Ge nerralPur pos e I I/O

ASIIC AS C
Sockett0 Soc ke 0

Full lFunction Fu l Function UART UA RT Blluetooth * B u et o ot h UART U AR T IrDA I rD A I22 C

DMA DMA Conttroll er C o nr o l l e r And and Bridgee Bri dg
In el l® Wireless MMXTM Int te® Wireless MMXTM

System Bus System Bus

PCMCIIA & CF P CMC A & CF Contt rol Con rol

XCVR Socket 1 X CVR Soc ket 1

IC

U SB U SB Clili e n t C ent BB Processorr B B Proce ss o Interr ace I n tef fac e
Keypp dd K e yaa Inneefaa c e I t t r rf ce S DCa r d /M M C S DC a rd / M MC Inneefacc e I t t r r fa e Meem oy Stick M morry Stick In tt eraac e I nerf f ce US B U SB OT G OT G Cam er a In ter face

MicroMicroarrchi te ctur e a chitecture
Dee bug D bug Conttrol err Conroll le 13 13 MH z M Hz O sc Os c

Intel® Intel® ® XScaleTM XScaleTM

US B U SB Host Host

Dynamic Dynam ic Memory Memor y Control Control Stt at ic Satic Memorry Memoy Control Control

SDRAM/ SDRAM Boot ROM

PowerrManagement P owe Management Clock Control l Clock Cont ro

32.768 32 .76 8 kH z kHz O sc Osc

ROM// ROM Flla sh/ Fash/ SRAM SRAM

Prrmarr yGPIO P i ima y GPIO

JTAG JTAG

§§

Electrical, Mechanical, and Thermal Specification

2-2

Package Information
This chapter provides the mechanical specifications for the Intel PXA27x processor family.

3

3.1

Package Information

Figure 3-1. 14 x 14 mm Intel® PXA27x Processor Family Package, Top View

The Intel PXA27x processor family has the following characteristics:

· · · ·

Ball pitch: 0.65mm Ball diameter: 0.30 mm Substrate thickness: 0.21 mm Mold thickness: 0.45 mm

The Intel PXA27x processor family is packaged in a 14- by 14-mm, 336-pin, 0.65-mm package, as shown in Figure 3-2 and Figure 3-3. Refer to Table 3-1 for package configuration information for Figure 3-1 and Figure 3-2.

Electrical, Mechanical, and Thermal Specification

3-1

Intel® PXA27x Processor Family Package Information

3.2

Processor Materials
D 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJKLMNPRTUVWY B a ll A1 C o rne r F T o p View - Bottom Package Ball side down C o m p le te Ink Mark Not Shown

Figure 3-2. 14 x 14 mm Intel® PXA27x Processor Family Package, Top View

G

E

Figure 3-3. 14 x 14-mm Intel® PXA27x Processor Family Package, Side View

A 2

A 1

A S ating e Pane l

Y

Table 3-1. Intel® PXA27x Processor Family Package Information (Sheet 1 of 2)
Dimension
Pacakge Height Ball Height Package Body Thickness

Symbol
A A1 A2

Min

Typical

Max
1 .5 5

0.180 1.121 1.195

Ball (Lead) Width Bottom Package Body Width Bottom Package Body Length

b D E

0.350 13.9 13.9

0.4 14 14

0.450 14.1 14.1

3-2

Electrical, Mechanical, and Thermal Specification

Intel® PXA27x Processor Family Package Information

Table 3-1. Intel® PXA27x Processor Family Package Information (Sheet 2 of 2)
Dimension
Top Package Body Width Top Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E

Symbol
F G [e ] N Y S1 S2

Min
10.9 12.9

Typical
11 13 0.650 336

Max
11.1 13.1

0.150 0.825 0.825

Table 3-2 describes the basic material properties of the processor components.
Component
Mold compound Solder balls(Leaded) Solder balls(Pb-free)

PXA271 FSCSP Material
ShinEtsu KMC 2500 VAT1
63% Sn/37% Pb

PXA272 FSCSP Material
ShinEtsu KMC 2500 VAT1
63% Sn/37% Pb

N /A

94.5% Sn/5.0% Ag/0.5% Cu

3.3

Junction To Case Temperature Thermal Resistance
Parameter
T heta Jc

Value and Units
2 degrees C/watt

3.4

Processor Markings
Figure 3-4 details the processor top markings, which identify the Intel PXA27x processor family in the 336-pin package. Refer to Table 3-1 for product information.

Electrical, Mechanical, and Thermal Specification

3-3

Intel® PXA27x Processor Family Package Information

Figure 3-4. Processor Markings, Intel® PXA27x Processor Family

Figure 3-5. Intel® PXA27x Product Information Decoder
R V P X A 2 7 1 F C 0 4 1 6

Package Type
LV=Leaded RV=Lead-Free

312 MHz 416 MHz 520 MHz

Speed

Intel XScale® Family
271=Product Number

Stepping Flash

Product Family Member

3-4

Electrical, Mechanical, and Thermal Specification

Intel® PXA27x Processor Family Package Information

3.5

Intel® PXA27x Processor Family Identification Markings
Table 3-2 shows the stacked memory configuration for each of the Intel PXA27x processor family packages.

Table 3-2. Intel® PXA27x Processor Family ID Markings
PXA PXA27x Package Stepping Level 1 Name1 Apps Processor CPU Stepping
C0

Stacked Memory Configuration
1x256 Mbit x 16 Flash + 1x256 Mbit x 16 SDRAM

Reference Documentation

PXA271

C0

LVPXA271FC0

-Intel® PXA27x Memory Subsytem (x16) with LPSDRAM Data Sheet Order No. 301855-001 -Intel® PXA27x Memory Subsystem (x32) Data Sheet Order No. 301854-001

PXA272

C0

LVPXA272FC0

C0

2x256Mbit x 32 Flash

NOTES: 1. From Top Package markings in figures above

3.6

Tray Drawing
For tray drawing information, refer to the Intel Developer website for the Intel® Wireless Communications and Computing Package Users Guide. §§

Electrical, Mechanical, and Thermal Specification

3-5

Intel® PXA27x Processor Family Package Information

3-6

Electrical, Mechanical, and Thermal Specification