Google Inc. v. Netlist, Inc.

Filing 153

EXHIBITS A, B, F, G, K, L, M re 152 Document E-Filed Under Seal filed by Google Inc.. (Attachments: # 1 Exhibit B, # 2 Exhibit F, # 3 Exhibit G, # 4 Exhibit K, # 5 Exhibit L, # 6 Exhibit M, # 7 Proposed Order)(Related document(s) 152 ) (Ezgar, Geoffrey) (Filed on 6/24/2010) (Counsel did not present papers as required by Civil L.R. 3-4) Modified on 6/25/2010 (jlm, COURT STAFF). Modified on 6/28/2010 (jlm, COURT STAFF).

JEDEC STANDARD

FBDIMM: Architecture and Protocol

JESD206

SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http://www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy of such patents or patent applications. Prospective users of the standard should act accordingly.

JANUARY 2007

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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JEDEC Standard No. 206 Page 63

Other Restrictions Only one outstanding configuration read or write register transaction is allowed on the channel. A configuration register read begins with the command and ends with the data being returned to the host. A configuration write begins with the command and ends when the read data would have been returned if the command were a Read Config Reg. This is the same point that an Alert Frame would be generated if there were a CRC error on the Write Config Reg command. Allowing only one outstanding configuration transaction on the bus allows for proper replay of the Write Config Reg command following an Alert Frame. A Soft Channel Reset requires NOP commands in all other command slots in the previous DRAM clock, the current DRAM clock, and the next 4 DRAM clocks. Only one In-band Debug event may be sent within a DRAM clock. The host controller is responsible for state and timing of the CKE pins vs. DRAM commands based on the DRAM specifications. A DRAM command and CKE command may target the same DIMM on the same DRAM clock provided that the DRAM specifications are met. Examples: A DRAM command may be issued to rank 1 on the same DRAM clock as a DRAM CKE per Rank command that changes the CKE of rank 0 while retaining a 1 on the CKE of rank 1. A DRAM command may be issued to DIMM 2 on the same DRAM clock as a DRAM CKE Command per DIMM that targets all DIMMs, but retains the state the CKEs of DIMM 2 as 1.

4.2.3 Command Encoding
Commands are encoded into the 24 bit C[23:0] fields of Command frames. Table 4-39 defines the bit mapping of an example DRAM configuration and the channel commands into the C[23:0] field. Table 4-39 -- Command Encoding
DRAM Cmnds Activate W rite Read Precharge All Precharge Single Auto (CBR) Refresh Enter Self Refresh Exit Self Refresh / Exit Power Down Enter Power Down reserved Channel Cmnds Debug: In-band Events Debug: Relative Timing Debug: Exposed Info reserved reserved DRAM CKE per DIMM DRAM CKE per Rank W rite Config Reg Read Config Reg reserved Soft Channel Reset Sync Channel NOP EV7 EV6 EV5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PH5 PH4 PH3 EX16 EX15 EX14 X X X X X X 23 22 21 20 1 0 0 0 0 0 0 0 0 0 19 1 1 0 0 0 0 0 0 0 18 1 0 1 1 1 1 1 1 1 17 RS RS RS RS RS RS RS RS RS X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 X DRAM Bank 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 X X X

DRAM Addr

DRAM Bank & Address DRAM Bank & Address DRAM Bank & Address X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

Note: The values in "X" fields in non-reserved commands above may be driven onto the DRAM device pins. OP3 OP2 OP1 OP0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 X 1 1 0 0 1 1 0 0 1 1 0 X X 1 0 1 0 1 0 1 0 1 0 X X BCST BCST DS3 DS3 X X X X EV4 EV3 EV2 EV1 RT9 X X X X A9 A9 X X X X EV0 RT8 EX8 X X X X A8 A8 X X X X PV7 RT7 EX7 X X PV6 RT6 EX6 X X PV5 RT5 EX5 X X PV4 RT4 EX4 X X PV3 RT3 EX3 X X PV2 RT2 EX2 X X PV1 RT1 EX1 X X PV0 RT0 EX0 X X PH2 PH1 PH0 X X X X TID X X X X X X X X X X X X X X X X X A10 A10 X X X X

EX13 EX12 EX11 EX10 EX9

DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 DS2 DS1 DS0 X X X X X X X X X X X X

DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 D3 D3 D2 D2 D1 D1 D0 D0 R1 R0 R1 R0 R1 R0 R1 R0 A7 A7 X X X X A6 A6 X X IER X A5 A5 X X X A4 A4 X X X A3 A3 X X X X A2 A2 X X X X 0 0 X X R1 X 0 0 X X R0 X

SD1 SD0

ERC EL0s

Note: All unused encodings are reserved. "X" values should be driven by the host to zero and ignored by the AMB.

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4.2.4 DRAM Commands
DRAM commands are generated by the host to access the DRAM devices behind each AMB buffer. The host has access to the DRAM devices as if the devices were directly connected to the host. The DS[2:0] field directs the command to one of the eight possible DRAM DIMMs on the FBD channel. The AMB decodes the DRAM commands and generates the control signals to the DRAM devices. The command delivery on the DRAM address and control signals (excluding CKE) use 1n command timing. 1n command timing means that the commands are present on the DRAM pins for a single clock cycle. The exact mapping of the control signals delivered to the DRAM devices are defined in the FBD AMB Specification. AMB buffers may support more than one DRAM technology. The details of the mapping of bank and address bits from the commands to the DRAM devices are specified in the FBD AMB Specification. An example mapping is shown in Table 4-40. For complete details of the DRAM command encoding refer to the JEDEC SDRAM data sheets. In the following table, the RS (Rank Select) bit specifies to the AMB which memory ranks located behind the buffer should be accessed. The other labels correspond to the familiar labels in the SDRAM data sheets. Rows labeled with an "*" are speculative and may change as the JEDEC SDRAM data sheets mature. Bit position 10 is used in the command encoding of the Precharge Single and Precharge All commands to allow the command bit to be mapped directly onto the DRAM address bit 10 to match the DRAM AP bit usage. Table 4-40 -- DRAM Command Mapping Examples
DDR2 Config 256Mb (64Mbx4)
20 1 0 1 0 1 0 1 0 1 0 1 0 19 X 1 X 1 X 1 X 1 A15 1 X 1 18 X r/w X r/w X r/w A14 r/w A14 r/w A14 r/w 17 RS RS RS RS RS RS RS RS RS RS RS RS 16 X X A13 X A13 X A13 X A13 X A13 X 15 X X X X B2 B2 B2 B2 B2 B2 B2 B2 14 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 13 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 12 A12 X A12 X A 12 X A12 X A12 X A12 A12 11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 10 A10 AP A10 AP A 10 AP A10 AP A10 AP A10 AP 9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0

Row 1KB page Col 512Mb (128Mbx4) Row 1KB page Col 1Gb (256Mbx4) Row 1KB page Col 2Gb (512Mbx4) Row 1KB page Col 4Gb (1Gbx4) * Row 1KB page Col 4Gb (1Gbx4) * Row 2KB page Col

DRAM Read and Write commands always transfer complete bursts of data determined by the Burst Length field programmed into the DRAM MRS registers. A burst length of 4 will transfer 36 bytes and a burst length of 8 will transfer 72 bytes to/from each ECC DIMM. Non-ECC memory DIMMs support the Data Mask function. Write accesses transfer the data from the write data FIFO located inside the AMB device on the DIMM. A register instructs the AMB when to drive the data after the Write command. The DDR2 specific Off-Chip Driver (OCD) Impedance Adjust command (EMRS access with A[9:7] = 100) also transfers data from the write data FIFO to the DRAM devices. The host is responsible for memory ordering, FBD channel scheduling, and error handling.

4.2.5 Channel Commands
Channel commands include the Sync command, miscellaneous DRAM commands, configuration register read and write commands, and miscellaneous maintenance commands. Channel commands may include a DS[2:0] field to specify which DIMM the command is addressing, a 4-bit operation code field to define the command type, and an 11bit address field. Table 4-41 defines the encoding of the Channel commands. The individual configuration registers are defined in the FBD AMB Specification Register chapter.

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