Google Inc. v. Netlist, Inc.

Filing 153

EXHIBITS A, B, F, G, K, L, M re 152 Document E-Filed Under Seal filed by Google Inc.. (Attachments: # 1 Exhibit B, # 2 Exhibit F, # 3 Exhibit G, # 4 Exhibit K, # 5 Exhibit L, # 6 Exhibit M, # 7 Proposed Order)(Related document(s) 152 ) (Ezgar, Geoffrey) (Filed on 6/24/2010) (Counsel did not present papers as required by Civil L.R. 3-4) Modified on 6/25/2010 (jlm, COURT STAFF). Modified on 6/28/2010 (jlm, COURT STAFF).

TIMOTHY T. SCOTT (SBN 126971/[e-mail]) GEOFFREY M. EZGAR (SBN 184243/ [e-mail]) LEO SPOONER III (SBN 241541/[e-mail]) KING & SPALDING LLP 333 Twin Dolphin Drive, Suite 400 Redwood Shores, CA 94065 Telephone: [phone] Facsimile: [phone] SCOTT T. WEINGAERTNER (pro hac vice/[e-mail]) ROBERT F. PERRY ([e-mail]) ALLISON ALTERSOHN (pro hac vice/[e-mail]) SUSAN KIM (pro hac vice/[e-mail]) MARK H. FRANCIS (pro hac vice/[e-mail]) DANIEL MILLER (pro hac vice/[e-mail]) King & Spalding LLP 1185 Avenue of the Americas New York, NY 10036-4003 Telephone: [phone] Facsimile: [phone] Attorneys for Plaintiff GOOGLE INC. UNITED STATES DISTRICT COURT FOR THE NORTHERN DISTRICT OF CALIFORNIA OAKLAND DIVISION GOOGLE INC. Plaintiff, v. NETLIST, INC., Defendant. I. Introduction 1. My name is William Hoffman, and I have written this Expert Report at the request of Civil Action No. C08 04144 SBA EXPERT REPORT OF WILLIAM HOFFMAN REGARDING INVALIDITY OF U.S. PATENT 7,289,386

Google Inc. ("Google") for consideration by the U.S. District Court, Northern District of

115.

To the extent that the above references are not deemed to be anticipatory, it is my opinion

that the asserted claims of the `386 Patent are invalid as obvious in view of the Dell `074 Reference in combination with the Wong `868 Reference. My detailed claim analysis is provided in Exhibit Y of this Expert Report. 116. A person of ordinary skill in the art would have combined these references because they

are both directed to addressing schemes in memory modules. F. Wong `868 Reference in View of Wong `281 Reference 117. To the extent that the above references are not deemed to be anticipatory, it is my opinion

that the asserted claims of the `386 Patent are invalid as obvious in view of the Wong `868 Reference in combination with the Wong `281 Reference. My detailed claim analysis is provided in Exhibit Z of this Expert Report. 118. A person of ordinary skill in the art would have combined these references because they

are both directed to addressing schemes in memory modules, are assigned to the same entity, and share common inventors. G. Amidi Reference in View of Dell `074 Reference 119. To the extent that the above references are not deemed to be anticipatory, it is my opinion

that the asserted claims of the `386 Patent are invalid as obvious in view of the Amidi Reference in combination with the Dell `074 Reference. My detailed claim analysis is provided in Exhibit AA of this Expert Report. 120. A person of ordinary skill in the art would have combined these references because they

are both directed to addressing schemes in memory modules. X. Invalidity Under Section 112 A. Violation of the Written Description Requirement and Lack of Enablement

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121.

Claim 1 of the `386 Patent recites in relevant part "the set of input control signals

corresponding to a second number of memory devices smaller than the first number of memory devices." This claim limitation requires that the control signals be for a number of logical memory devices less than the number of actual memory devices. For example, the claim language would apply to a memory module have four memory devices that receives input control signals for only two devices. 122. The `386 Patent only describes embodiments where the input signals are for fewer than

the actual number of ranks. For example, Figure 1A of the `386 Patent, reproduced below, shows that two received chip select signals, CS0 and CS1, are mapped to four chip select signals, CS0A, CS0B, CS1A, and CS1B.

123.

In describing the preferred embodiment, the `386 Patent explains: For example, in the exemplary embodiment as schematically illustrated by FIG. 1A, the first number of ranks is four while the second number of ranks is two. In the exemplary embodiment of FIG. 1B, the first number of ranks is two while the second number of ranks is one. Thus, in certain embodiments, even though the memory module 10 actually has the first number of ranks of memory

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devices 30, the memory module 10 simulates a virtual memory module by operating as having the second number of ranks of memory devices 30. In certain embodiments, the memory module 10 simulates a virtual memory module when the number of memory devices 30 of the memory module 10 is larger than the number of memory devices 30 per memory module for which the computer system is configure to utilize. (`386 Patent, Ex. A, 7:14-29.) In the exemplary embodiment schematically illustrated by FIG. 1A, the memory module 10 has four ranks of memory devices 30 and the computer system is configured for two ranks of memory devices per memory module. (`386 Patent, Ex. A, 7:45-48.) 124. The specification of the `386 Patent describes how to implement a memory module that

has more memory sub-arrays than the computer system is expecting. In fact, the specification shows that the Serial Presence Detect device ("SPD") only tells the computer system that there are fewer devices than are actually present. In certain embodiments, the SPD device 70 comprises data which characterize the memory module 10 as having fewer ranks of memory devices than the memory module 10 actually has, with each of these ranks having more memory density. For example, for a memory module 10 compatible with certain embodiments described herein having two ranks of memory devices 30, the SPD device 70 comprises data which characterizes the memory module 10 as having one rank of memory devices with twice the memory density per rank. Similarly, for a memory module 10 compatible with certain embodiments described herein having four ranks of memory devices 30, the SPD device 70 comprises data which characterizes the memory module 10 as having two ranks of memory devices with twice the memory density per rank. In addition, in certain embodiments, the SPD device 70 comprises data which characterize the memory module 10 as having fewer memory devices than the memory module 10 actually has, with each of these memory devices having more memory density per memory device. For example, for a memory module 10 compatible with certain embodiments described herein, the SPD device 70 comprises data which characterizes the memory module 10 as having one-half the number of memory devices that the memory module 10 actually has, with each of these memory devices having twice the memory density per memory device. (`386 Patent, Ex. A, 10:31-55.) 125. I understand that Netlist has asserted that this claim element is met by Google products

that practice Mode C of JEDEC Standard JESD 82-20A. (See Netlist Amended Preliminary
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Infringement Contentions, attached as Exhibit BB.) More specifically, I understand that Netlist has asserted that this claim element is met by four-rank memory modules that receive from the memory controller a first rank select in the field RS0 and a second rank select (RS1) in the field BA0. As a result, I understand that Netlist has asserted that a four-rank device that receives as input two rank select signals would infringe. 126. Two bits, such as those contained in two rank select signals, may be used to identify four

devices. As a result, the accused four-rank devices receive input control signals corresponding to the number of actual devices, four, not some smaller number of devices, such as two. 127. To the extent that Netlist's infringement contentions are directed to memory modules that

receive control signals corresponding to the number of actual memory devices, not some lesser number of logical memory devices, there is no support in the specification to enable this implementation. There is simply a logical contradiction in Netlist's application in view of the specification. The specification does not enable a system in which there is an input addressing a number of ranks that is less than the actual number of ranks while also at the same time being the same as the actual number of ranks. 128. In addition, to the extent that Netlist's infringement contentions are directed to memory

modules that receive control signals corresponding to the number of actual memory devices, not some lesser number of logical memory devices, there is no supporting written description. As seen in the examples above, the specification does not describe any addressing scheme where the computer system addresses the actual number of ranks.

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XI. Omission of Reference Material to Patentability A. Dell `827 Reference 129. The `386 Patent did not issue until October 30, 2007. I understand that a patentee has an

obligation to disclose all material references of which it is aware. 130. Netlist and its attorney, Bruce Itchkawitz, were aware of the Dell `827 Reference as early

as September 4, 2007, almost a month an a half before the issuance of the `386 Patent. (See Information Disclosure Statement, attached as Exhibit CC.) 131. The Dell `827 Reference is material to claims 1 and 11 of the `386 Patent, as can be seen

in my analysis above and in the attached claim chart, Exhibit L. XII. Reservation of Right to Supplement 132. I reserve the right to modify or supplement my opinions, if necessary, based on further

review and analysis of evidence in this case, including review and analysis of any information that may be provided to me subsequent to the filing of this report. I also reserve the right to modify or supplement my opinions based on any changes to the claim constructions I have used in my analysis for this matter. 133. In addition, I understand that Netlist has filed a motion to amend its infringement

contentions to include additional claims. I further reserve the right to supplement my opinions to include review and analysis of invalidity with regard to any claims that the Court may allow Netlist to add. XII. Conclusion 134. Based on my review and analysis to date, I hold the opinion that the `386 Patent is invalid

in view of at least the aforementioned prior art.

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