Netlist, Inc. v. Google Inc.

Filing 49

BRIEF: CLAIM CONSTRUCTION STATEMENT filed by Google Inc.. (Attachments: # 1 Affidavit, # 2 Exhibit A, # 3 Exhibit B, # 4 Exhibit C, # 5 Exhibit D)(Ezgar, Geoffrey) (Filed on 8/4/2010) Modified on 8/5/2010 (jlm, COURT STAFF).

Netlist, Inc. v. Google Inc.

Doc. 49 Att. 5

Dockets.Justia.com

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TIMOTHY T. SCOTT (SBN 126971/[e-mail]) GEOFFREY M. EZGAR (SBN 184243/ [e-mail]) LEO SPOONER III (SBN 241541/[e-mail]) KING & SPALDING LLP 333 Twin Dolphin Drive, Suite 400 Redwood Shores, CA 94065 Telephone: [phone] Facsimile: [phone] SCOTT T. WEINGAERTNER (pro hac vice/[e-mail]) ROBERT F. PERRY ([e-mail]) ALLISON ALTERSOHN (pro hac vice/[e-mail]) DANIEL MILLER (pro hac vice/[e-mail]) SUSAN KIM (pro hac vice/[e-mail]) MARK H. FRANCIS (pro hac vice/[e-mail]) KING & SPALDING LLP 1185 Avenue of the Americas New York, NY 10036-4003 Telephone: [phone] Facsimile: [phone] Attorneys for Defendant GOOGLE INC. UNITED STATES DISTRICT COURT FOR THE NORTHERN DISTRICT OF CALIFORNIA OAKLAND DIVISION NETLIST, INC., Plaintiff, v. GOOGLE INC., Defendant. DEFENDANT GOOGLE INC.'S INVALIDITY CONTENTIONS PURSUANT TO PATENT L.R. 3-3 AND 3-4 Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

GOOGLE INC.'S INVALIDITY CONTENTIONS Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

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Pursuant to Patent L.R. 3-3, Google Inc. ("Google") hereby serves its Invalidity Contentions on Plaintiff Netlist, Inc. ("Netlist"). In the absence of a claim construction order from the Court, Google has based its Invalidity Contentions in part upon the disclosure of the specification of U.S. Patent No. 7,619, 912 B2 ("the `912 Patent") and, to the extent any apparent construction of the asserted claims of the `912 Patent were advanced by Netlist in its Infringement Contentions served on April 8, 2010, on any such asserted construction. Nothing herein should be construed as an admission that Google agrees with Netlist's apparent claim constructions. Google expressly reserves the right to propose alternative constructions to those advocated by Netlist and to request Netlist's actual claim construction position during the claim construction portion of this case. Google expressly reserves the right to challenge the sufficiency of Netlist's Infringement Contentions and any claims or claim terms that Netlist purports to have explicitly or implicitly construed therein. Prior art not included in this disclosure, whether or not now known to Google, may become relevant depending on the claim constructions that Netlist asserts and the constructions that this Court may adopt. Google's own ongoing investigations may also uncover additional prior art. The obviousness combinations of references under 35 U.S.C. § 103 that are provided below and in the accompanying exhibits are merely exemplary and are not intended to be exhaustive. Additional obviousness combinations of the references identified below are possible, and Google reserves the right to use any such combinations in this litigation. In particular, Google is currently unaware of the extent, if any, to which Netlist will contend that the art identified by Google does not disclose limitations of the asserted claims. Should such an issue arise, Google reserves the right to identify other references that would have made the addition of the allegedly missing limitation to the disclosed device obvious. Accordingly, Google reserves the right to supplement or modify these Invalidity Contentions based on claim construction and further discovery and in a manner consistent with the Federal Rules of Civil Procedure and this Court's rules, including the Patent Local Rules. In addition to these Invalidity Contentions and prior art identified herein, Google expressly 2

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incorporates by reference in their entirety and reserves the right to rely upon any and all invalidity contentions and prior art served in any other action involving the `912 Patent. I. IDENTIFICATION OF PRIOR ART

Pursuant to Patent L.R. 3-3(a), and in light of Netlist's allegations set forth in its Infringement Contentions and accompanying claim charts served on April 8, 2010, Google lists below the prior art now known to Google which it contends anticipates or renders obvious Claims 1, 3, 4, 6-11, 15, 18-22, 24-25, 27-29, 31-34, 36-39, 41-45, and 50 (collectively, "the Asserted Claims") of the `912 Patent. Pursuant to Patent L.R. 3-3(a), Google identifies the following United States patents and publications as prior art that anticipate or render obvious the Asserted Claims of the `912 Patent. Google reserves the right to modify and/or supplement this list of prior art. Patents and Published Applications Number Country of Origin Date of Issue/Publication June 1, 2006 March 27, 2001 July 20, 1999 April 28, 1999 January 11, 1983 July 2, 2002 December 3, 1996 November 1, 2005 March 2, 2006

U.S. Pat. Appl. No. 2006/0117152 A1 United States (GNET 000552-000568) U.S. Pat. No. 6,209,074 (GNET 001088-001097) U.S. Pat. No. 5,926,827 (GNET 000894-000901) U.S. Pat. No. 5,745,914 (GNET 000845-000858) U.S. Pat No. 4,368,515 (GNET 000616-000625) U.S. Pat. No. 6,414,868 (GNET 001109-001120) U.S. Pat. No. 5,581,498 (GNET 000772-000790) U.S. Pat. No. 6,961,281 (GNET 001298-001309) U.S. Pub. No. 2006/0044860 A1 (GNET 002302-002313) United States United States United States United States United States United States United States United States

3

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Number U.S. Pat. No. 7,356,639 (GNET 001519-001571) U.S. Pat. No. 7,120,727 (GNET 001405-001418) U.S. Pat. No. 4,392,212 (GNET 000626-000635)

Country of Origin United States United States United States

Date of Issue/Publication April 8, 2008 October 10, 2006 July 5, 1983

Google further identifies those products and systems that practice the subject matter of the cited prior art and prior art that may be found in the future. Discovery relating to prior art products, systems, and inventions is ongoing, and Google reserves the ability to supplement these contentions with any additional prior art products, systems, and inventions it becomes aware of through this discovery. II. STATUTORY BASIS FOR INVALIDITY A. Anticipation (35 U.S.C. § 102) and Obviousness (35 U.S.C. § 103)

Pursuant to Patent L.R. 3-3(b) and 3-3(c), and in light of Netlist's Infringement Contentions and accompanying claim chart served on April 8, 2010, Google attaches hereto as Exhibits 1-13 claim charts identifying prior art references that anticipate the Asserted Claims as well as combinations of prior art references which render the Asserted Claims obvious. The attached charts identify specifically where, in each alleged item of prior art, each element of each asserted claim is found. Patent L.R. 3-3(b) requires Google to identify any combinations of prior art showing obviousness and "an explanation of why the prior art renders the asserted claim obvious." Pursuant to the Supreme Court's decision in KSR Int'l Co. v. Teleflex, Inc., to the extent an express motivation to combine references is required under current law at all this requirement is minimal. For example, "any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the element." KSR Int'l, 550 U.S. 398, 402 (2007). In addition, "common sense" teaches that "a person of ordinary skill often will be able to fit the teachings of multiple patents together like pieces of a puzzle." Id. GOOGLE INC.'S INVALIDITY CONTENTIONS 4

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Moreover, the rationale for combining any of these references with others exists within the references themselves, as well as within the knowledge of those of ordinary skill in the art. These references identify and address the same technical issues and suggest very similar solutions to those issues. If and to the extent Netlist challenges the correspondence of any of these references with respect to particular elements of the asserted claims, Google reserves the right to supplement these Invalidity Contentions to identify a reason to combine particular references with one another with additional particularity. An index identifying the prior art discussed in each of the attached exhibits is provided below. Invalidity Charts for the `912 Patent U.S. Pat. Appl. No. 2006/0117152 A1 U.S. Pat. No. 6,209,074 U.S. Pat. No. 5,926,827 U.S. Pat. No. 5,745,914 U.S. Pat No. 4,368,515 U.S. Pat. No. 6,414,868 U.S. Pat. No. 5,581,498 U.S. Pat. Appl. No. 2006/0117152 A1 in combination with U.S. Pat. No. 6,209,074 U.S. Pat. No. 6,209,074 in combination with U.S. Pat. No. 5,926,827 U.S. Pat. No. 6,209,074 in combination with U.S. Pat. No. 5,745,914 U.S. Pat. No. 6,209,074 in combination with U.S. Pat. No. 5,581,498 U.S. Pat. No. 6,209,074 in combination with U.S. Pat No. 4,368,515 U.S. Pat. No. 6,209,074 in combination with U.S. Pat. No. 6,414,868 Exhibit 1 Exhibit 2 Exhibit 3 Exhibit 4 Exhibit 5 Exhibit 6 Exhibit 7 Exhibit 8 Exhibit 9 Exhibit 10 Exhibit 11 Exhibit 12 Exhibit 13

In charts where Google identifies a combination of references, Google may rely upon a subset of the references or all of the references depending upon the Court's claim construction and GOOGLE INC.'S INVALIDITY CONTENTIONS 5

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Google's own further investigation. Further, Google's identification of multiple references in any given chart and contention that various combinations thereof render an asserted claim obvious under 35 U.S.C. § 103 is in no way an admission or suggestion that each reference does not independently anticipate the asserted claims under 35 U.S.C. § 102. The obviousness

combinations stated in the attached charts are merely exemplary and are not intended to be exhaustive. Any of the references listed above in Section I for the `912 Patent may be combined to render obvious, and therefore invalid, the asserted claims of the `912 Patent. B. Indefiniteness and Lack of Enablement (35 U.S.C. § 112 ¶¶ 1-2)

Pursuant to Patent L.R. 3-3(d), Google attaches hereto as Exhibit 14 a claim chart that identifies exemplary grounds of invalidity for the asserted claims based on indefiniteness and lack of enablement and/or written description, under 35 U.S.C. § 112 ¶¶ 1-2. III. DOCUMENT PRODUCTION ACCOMPANYING PRELIMINARY

INFRINGEMENT CONTENTIONS (PATENT L.R. 3-4) Pursuant to Patent L.R. 3-4, Google has served, either concurrently with these Invalidity Contentions or previously produced in related Case No. 08-04144-SBA, documentation required by Pat. L.R. 3-4 (a) and (b). If Google subsequently acquires or locates any further documents falling into the categories set forth in Patent L.R. 3-4, Google will produce such documents to Netlist. Google reserves the right to rely on any such subsequently acquired and produced documents. IV. ADDITIONAL PRIOR ART

In addition to the prior art references identified above, Google lists below the following patents, patent applications, printed publications, and products which are pertinent to the invalidity of the `912 Patent. Google has not provided claim charts for each of these references either because at this time Google does not intent to rely on them, because they have substantially similar disclosures to other prior art for which invalidity charts have been provided, or because they are used as supporting references in an obviousness combination. However, Google reserves the right to revise its invalidity contentions to rely on these references to prove the invalidity of the 6

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asserted claims of the `912 Patent in a manner consistent with the Federal Rules of Civil Procedure and this Court's Local Rules. Patent or Published Application Number / Title Dell 827 Information Disclosure Statement (NETLG00005198 ) U.S. Patent No. 4,392,212 (GNET 000626 - 000635)) U.S. Patent No. 5,247,643 (GNET 000697 - 000735) U.S. Patent No. 5,426,753 (GNET 000747 - 000753) U.S. Patent No. 5,703,826 (GNET 000835 - 000844) U.S. Patent No. 5,805,520 (GNET 000859 - 000869) U.S. Patent No. 5,959,930 (GNET 000902 - 000949) U.S. Patent No. 6,154,418 (GNET 001043 - 001055) U.S. Patent No. 6,453,381 (GNET 001121 - 001129) U.S. Patent No. 6,518,794 (GNET 001162 - 001180) U.S. Patent No. 6,681,301 (GNET 001199 - 001212) U.S. Patent No. 6,785,189 (GNET 001241 - 001245) U.S. Patent No. 6,807,125 (GNET 002254 - 002265) U.S. Patent No. 6,813,196 (GNET 001246 - 001251) U.S. Patent No. 6,944,694 (GNET 001275 - 001297) U.S. Patent No. 6,981,089 (GNET 001310 - 001323) U.S. Patent No. 6,982,893 (GNET 001342 - 001347) U.S. Patent No. 6,996,686 (GNET 001348 - 001356) U.S. Patent No. 7,046,538 (GNET 001393 - 001404) U.S. Patent No. 7,120,727 (GNET 001405 - 001418) U.S. Patent No. 7,200,021 (GNET 001467 - 001476) U.S. Patent Application Publication: US 2001/0052057 A1 (GNET 000369 - 000386) 7 Date of Issue/Publication September 4, 2007 July 5, 1983 September 21, 1993 June 20, 1995 December 30, 1997 September 8, 1998 September 28, 1998 November 28, 2000 September 17, 2002 February 11, 2003 January 20, 2004 August 31, 2004 October 19, 2004 November 2, 2004 September 13, 2005 December 27, 2005 January 3, 2006 February 14, 2006 May 16, 2006 October 10, 2006 April 3, 2007 December 31, 2001

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Patent or Published Application Number / Title U.S. Patent Application Publication: US 2002/0088633 A1 (GNET 000387 - 000405) U.S. Patent Application Publication: US 2003/0063514 A1 (GNET 000406 - 000417) U.S. Patent Application Publication: US 2003/0191995 A1 (GNET 002266 - 002276) U.S. Patent Application Publication: US 2003/0210575 A1 (GNET 002277 - 002301) U.S. Patent Application Publication: US 2004/0037158 A1 (GNET 000461 - 000472) U.S. Patent Application Publication: US 2005/0036378 A1 (GNET 000484 - 000528) U.S. Patent Application Publication: US 2005/0281096 A1 (GNET 000529 - 000551) U.S. Patent Application Publication: US 2006/0126369 A1 (GNET 000569 - 000578) U.S. Patent Application Publication: US 2006/0129755 A1 (GNET 000579 - 000589) U.S. Patent No. 6,961,281 (GNET 001298-1309) U.S. Patent No. 7,356,639 (GNET 001519-1571) U.S. Patent Application Publication: 2006-0044860 (GNET 002302 - 2313) U.S. Patent No. 4,633,429 (GNET000636-642) U.S. Patent No. 4,958,322 (GNET000643-653) U.S. Patent No. 4,961,172 (GNET000654-671) U.S. Patent No. 4,980,850 (GNET000672-696) U.S. Patent No. 5,345,412 (GNET000736-746) U.S. Patent No. 5,483,497 (GNET000754-771) U.S. Patent No. 5,699,542 (GNET000805-818) U.S. Patent No. 5,822,251 (GNET000870-888) U.S. Patent No. 5,966,736 (GNET000958-982) 8

Date of Issue/Publication July 11, 2002 April 3, 2003 October 9, 2003 November 11, 2003 February 26, 2004 February 17, 2005 December 22, 2005 June 15, 2006 June 15, 2006 March 17, 2005 April 8, 2008 March 2, 2006 December 30, 1986 September 18, 1990 October 2, 1990 December 25, 1990 September 6, 1994 January 9, 1996 December 16, 1997 October 13, 1998 October 12, 1999
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Patent or Published Application Number / Title U.S. Patent No. 6,108,745 (GNET001019-1042) U.S. Patent No. 6,185,654 (GNET001056-1087) U.S. Patent No. 6,487,102 U.S. Patent No. 6,646,949 (GNET001181-1189) U.S. Patent No. 6,674,684 (GNET001190-1198) U.S. Patent No. 6,697,888 (GNET001213-1222) U.S. Patent No. 6,742,098 (GNET001223-1240) U.S. Patent No. 6,834,014 (GNET001252-1274) U.S. Patent No. 6,982,892 (GNET001324-1341) U.S. Patent No. 7,007,130 (GNET001357-1392) U.S. Patent No. 7,124,260 (GNET001419-1436) U.S. Patent No. 7,133,960 (GNET001437-1444) U.S. Patent No. 7,181,591 (GNET001445-1466) U.S. Patent No. 7,266,639 (GNET001477-1487) U.S. Patent No. 7,281,079 (GNET001488-1504) U.S. Patent No. 7,346,750 (GNET001505-1518) U.S. Patent Application Publication: US 20030090879 (GNET000418-0460) U.S. Patent Application Publication: US 20040201968 (GNET000473-0483) U.S. Patent Application Publication: US 20060179206 (GNET000590-0599) U.S. Patent Application Publication: US 20060267172 (GNET000600-0615) WO 1992/002879 WO 1994/007242 WO 1995/034030 WO 2002/058069 9

Date of Issue/Publication August 22, 2000 February 6, 2001 November 26, 2002 November 11, 2003 January 6, 2004 February 24, 2004 May 25, 2004 December 21, 2004 January 3, 2006 February 28, 2006 October 17, 2006 November 7, 2006 February 20, 2007 September 4, 2007 October 9, 2007 March 18, 2008 May 15, 2003 October 14, 2004 August 10, 2006 November 30, 2006 February 20, 1992 March 31, 1994 December 14, 2005 July 25, 2002
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Patent or Published Application Number / Title WO 2003/017283 WO 2003/069484 WO 2006/055497 U.S. Patent No. 6,502,161 (GNET001141-1161) U.S. Patent No. 6,553,450 U.S. Patent No. 6,639,820 U.S. Patent No. 6,683,372 U.S. Patent No. 6,968,440 U.S. Patent No. 6,970,968 U.S. Patent No. 7,078,793 U.S. Patent No. 7,266,634 U.S. Patent No. 7,363,422 U.S. Patent No. 7,155,627

Date of Issue/Publication February 27, 2003 August 21, 2003 May 26, 2006 December 31, 2002 April 22, 2003 October 28, 2003 January 27, 2004 November 22, 2005 November 29, 2005 July 18, 2006 September 4, 2007 April 22, 2008 December 26, 2006

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Publication Title A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates, Kornaros, G., 5.1, pp. 54 - 59 (GNET001953-1958) Accelerating system integration by enhancing hardware, firmware, and co-simulation, Schubert, K., et al. , IBM J. Res. & Dev. Vol. 48, No. 3/4, May/July 2004 (GNET001959-1971) Access Rate/Availability Improvement Logic for Dynamic Memories, Grimes, WD, IBM Techn. Discl. Bulletin, pp. 2678-2681, Oct. 1982, (GNET0019721974)

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May/July 2004

October 1982

MPC8260 SDRAM Support, Freescale Semiconductor, October 2006 Appl. Note, Doc. Number: AN2165/D, Rev. 1, 10/2006 An 88-Way Multiprocessor Within An FPGA With Customizable Instructions, Hoare, R., Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS'04), 2004 (GNET001974-1982) An Enable Signal Circuit for Multiple Small Banks, IBM Techn. Discl. Bulletin, IP.com number: IPCOM000015887D, June 1, 2002, IP.com Electronic Publication: June 21, 2003 (GNET001983-1987) An on-chip cache compression technique to reduce decompression overhead and design complexity, Lee, J., Journal of Systems Architecture Vol. 46, pp. 13651382, (2000) (GNET001988-2005) Bank Striping Of Data Across Internal Sdram Banks, IBM Technical Disclosure Bulletin, IP.com number: IPCOM000013697D, August 1, 2000, IP.com Electronic Publication: June 18, 2003 (GNET002006-2008) Chip Select Circuit for Multi-Chip RAM Modules, Fitzgerald, B.F., et al., IBM Technical Disclosure Bulletin, pp. 3932-3934, Dec. 1, 1984, IP.com number: IPCOM000044404D, IP.com Electronic Publication: February 5, 2005 (GNET002028-2030) Chip Select Decoder Circuit, Smith, B.A., IBM Technical Disclosure Bulletin, pp. 5826-5827, March 1, 1985, IP.com Number: IPCOM000063400D, IP.com Electronic Publication: February 18, 2005 (GNET002031-2033) April 2004

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December 1, 1984

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Publication Title Chip Select Technique for Multi Chip Decoding, Hession, J., IBM Technical Disclosure Bulletin, pp. 1563-1564, Sept. 1, 1978, IPCOM000070404D, IP.com Electronic Publication: February 21, 2005 (GNET002034-2036)

Date of Publication September 1, 1978

Concurrency, Latency, or System Overhead: Which July 2001 Has the Largest Impact on Uniprocessor DRAMSystem Performance?, Cuppu, V., et al., IEEE, pp. 6271, 2001,.Proceedings of the 28th International Symposium on Computer Architecture, June 30­July 4, 2001 (GNET002037-2046) Continuous RAS Access Method in Multiple-bank DRAM Chip, Sunaga, T, et al., IBM Technical Disclosure Bulletin, Vol. 41, No. 414, pp. 10-48, Article 41473, October 1, 1998, IP.com No: IPCOM0001233750, IP.com Electronic Publication: April 4, 2005 (GNET002047-2049) Designing a Modern Memory Hierarchy with Hardware Prefetching, Lin, W., IEEE Transactions On Computers, Vol. 50, No. 11, pp. 1202-1217, Nov. 2001 (GNET002050-2065) Designing And Implementing A Fast Crossbar Scheduler, Gyupta, P., IEEE Micro, pp. 20-28, 1999 (GNET002066-2074) Distributed Memory Mapping, IBM Technical Disclosure Bulletin, October 1, 2000, IP.com No: IPCOM0000147880, IP.com Electronic Publication: June 20, 2003 (GNET002075-2077) Dual Addressable Memory, Pellinger, R.D., et al., IBM Technical Disclosure Bulletin, January 1, 1978, pp. 3259-3260, IP.com No: IPCOM000068610D, IP.com Electronic Publication: February 20, 2005 (GNET002080-2082) Embedded Memory in System-on-Chip Design: Architecture and Prototype Implementation, Jin, H., et al., IEEE, pp. 141- 146, 2003 (GNET002083-2088) Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion, Implementation, Arlington, DL, IBM Technical Disclosure Bulletin, pp. 507-509, July 1987 (GNET002089-2090) October 1, 1998

November 2001

January-February 1999

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Publication Title Fast Multichip Memory System With Power Select Signal, Blum, A, IBM Technical Disclosure Bulletin, pp. 1057-1058, Aug. 1979 (GNET002091-2092) Fet Ram Chip Double Density Scheme, Gray, K., IBM Technical Disclosure Bulletin, p. 2927, Oct. 1, 1984, IP.com No: IPCOM000043942D, IP.com Electronic Publication: Feb. 5, 2005 (GNET002093-2095) FPGA: take Five, www.electronicsnews.com, Aug. 26, 2002, p. 24 (GNET002096)

Date of Publication August 1979

October 1, 1984

August 26, 2002

High Density Memory Selection Circuit, Yao, YL, December 1, 1972 IBM Technical Disclosure Bulletin, pp. 2042-2044, Dec. 1, 1972, IP.com No: IPCOM000078218D, IP.com Electronic Publication: Feb. 25, 2005 (GNET002097-2100) High-Performance DRAMs in Workstation Environments, Cuppu, V., IEEE Transactions On Computers, Vol. 50, No. 11, pp. 1133-1153, Nov. 2001 (GNET002101-2120) IBM's S/390 G5 Microprocessor Design, Siegel, T., (IBM Corp.), IEEE - March-April 1999, pp. 12-23 (GNET002121-2132) November 2001

March-April 1999

Input/Output Chip Select Doubler, Bennayoun, A, IBM April 1, 1995 Technical Disclosure Bulletin, April 1, 1995, Vol. 38, No. 4, p. 237-240, IP.com No: IPCOM000115289D, IP.com Electronic Publication: March 30, 2005 (GNET002133-2137) Interface Synthesis using Memory Mapping for an FPGA Platform, Luthra, M., Proceedings of the 21st International Conference on Computer Design (ICCD'03), IEEE 2003 (GNET002138-2143) WSI Aims Programmable MCU Peripherals At DSPs Integrated Solution Can Stand In For Two Chips, Electronic Buyer's News, n. 927 , p. 39, 1994 Logic and Decoder Arrangement for Controlling Spill/Wrap Boundaries of a Bit-Addressable Memory Decoder, Matick, R., IBM Technical Disclosure Bulletin, pp 3699-3702, Dec. 1984 (GNET0021562158) Logic Processor for Logic Simulation Machine, Denneau, M., IBM Technical Disclosure Bulletin, Vol. 25, No. 1, pp. 91-94, June 1982 (GNET002158) 13 October 2003

1994

December 1984

June 1982

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Publication Title Memory Expansion Technology (MXT): Software Support and Performance, Abali, B., IBM J. Res. & Dev. Vol. 45, No. 2, pp. 287-300, March 2001 (GNET002160-2173) Method for a high-performance DRAM address mapping mechanism, IP.com No: IPCOM000008164D, IP.com Electronic Publication: May 22, 2002 (GNET002174-2178) Method For Memory Probing On A Multiple-DIMM Bus, IP.com No: IPCOM000019063D, IP.com Electronic Publication: August 27, 2003 (GNET002179-2181) Method for Multiple Device Interface Testing Using A Single Device, IP.com Electronic Publication: October 16, 2002, IP.com number: IPCOM000010054D (GNET002182-2185) Method of Executing Manufacturing ROM Code Without Removing System Roms, Arroyo, RX, IBM Technical Disclosure Bulletin, Nov. 1, 1989, pp. 479480, IP.com Electronic Publication: January 29, 2005, IP.com No: IPCOM000037214D (GNET002186-2188) Partial Two Way Mapping Technique, Ofek, H., IBM Technical Disclosure Bulletin, pp. 429-430, Aug. 1969 (GNET002189-2190)

Date of Publication March 2001

May 22, 2002

August 27, 2003

October 16, 2002

November 1, 1989

August 1969

Planar Memory Boundary Registers with Remap November 1993 Feature, Stelzer, K., IBM Technical Disclosure Bulletin, pp. 627-628, Nov. 1993 (GNET002191-2192) Program Controlled Paging Scheme for Memory Expansion, IBM Technical Disclosure Bulletin, Dec. 1, 1982, p. 3865, IP.com number: IPCOM000050954D , IP.com Electronic Publication: February 10, 2005 (GNET002193-2195) Programmable Memory Address Decoding For Microprocessor Memory Devices, Paldan, D., Motorola Technical Disclosure Bulletin, March 1, 1983, IP.com number: IPCOM000005486D, IP.com Electronic Publication: October 9, 2001 (GNET002196-2198) December 1, 1982

March 1, 1983

"Programmable Logic: What's it to Ya?," How June 1999 Programmable Logic Works, Barr, Michael, Embedded Systems Programming, June 1999, pp. 75-84. (GNET002122-2206) 14
GOOGLE INC.'S INVALIDITY CONTENTIONS Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

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Publication Title Prototype Implementation and Evaluation of a Multibank Embedded Memory Architecture in Programmable Logic, Jin, H., IEEE, 2003, pp. 13-16 (GNET002207-2210) Read-Select Capability for Static Random-Access Memory, Matick, R., IBM Technical Disclosure Bulletin, pp. 6640-6642, April 1985 (GNET0022142216) Shuffle Your Chips For Better Performance, Plotnick, N., PC Week - Netweek, p. 90, Aug. 17, 1998 (GNET002217) Use Of Partially Good Memory Chips, Meyers, R., IBM Technical Disclosure Bulletin, Feb. 1, 1979, pp. 3582-3583, IP.com number: IPCOM000066246D, IP.com Electronic Publication: February 19, 2005 (GNET002233-2235) Read Only Store Memory Extension, Kane, M., et al., IBM Technical Disclosure Bulletin, Feb. 1, 1975, pp. 2695-2696, IP.com No: IPCOM000082845D, IP.com Electronic Publication: Feb. 28, 2005 (GNET002211-2213) QBM Alliance, "Quad Band Memory: DDR 200/266/333 devices producing DDR 400/533/667," January 23-24, 2002. Miles J. Murdocca and Vincent P. Heuring, Principles of Computer Architecture, 2000. U.S. Patent Application Publication: US 2005/0138267 A1 A Performance Comparison of Contemporary DRAM Architectures, Cuppu, V., Proceedings of the 26th International Symposium on Computer Architecture, May 2-4, 1999 (GNET 002236 - 002247) Micron DDR SDRAM RDIMM MT36VDDF12872 ­ 1GB MT36VDDF25672 ­ 2GB Products ProLiant 7000 Server Company Compaq 15

Date of Publication August 2003

April 1985

August 17, 1998

February 1, 1979

February 1, 1975

January 23-24, 2002

2000 June 23, 2005 May, 1999

2002

Date of First Sale/Public Use June 1998
GOOGLE INC.'S INVALIDITY CONTENTIONS Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

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GOOGLE INC.'S INVALIDITY CONTENTIONS Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

DATED: May 14, 2010

KING & SPALDING LLP

By: /s/ Allison Altersohn _________ Allison Altersohn Attorneys for Defendant GOOGLE INC.

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CERTIFICATE OF SERVICE I hereby certify that a true and correct copy of DEFENDANT GOOGLE INC.'S INVALIDITY CONTENTIONS PURSUANT TO PATENT L.R. 3-3 AND 3-4 is being served by electronic mail upon the following counsel of record on this 14th day of May, 2010: PRUETZ LAW GROUP LLP Adrian M. Pruetz (Bar No. CA 118215) Email: [e-mail] Erica J. Pruetz (Bar No. CA 227712) Email: [e-mail] 200 N. Sepulveda Blvd., Suite 1525 El Segundo, CA 90245 Telephone: [phone] Facsimile: [phone] LEE TRAN & LIANG APLC Enoch H. Liang (Bar No. CA 212324) Email: [e-mail] Steven R. Hansen (Bar No. CA 198401) Email: [e-mail] Edward S. Quon (Bar No. CA 214197) Email: [e-mail] 601 S. Figueroa Street, Suite 4025 Los Angeles, CA 90017 Telephone: [phone] Facsimile: [phone]

/s/ Allison Altersohn Allison Altersohn

17

GOOGLE INC.'S INVALIDITY CONTENTIONS Case No. CV09-05718 SBA [Related to Case No: CV08-04144 SBA]

Exhibit 14: Invalidity under 35 U.S.C. § 112 Claim 1 of the `912 Patent recites in relevant part "the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals corresponding to the first number of DDR memory devices arranged in the first number of ranks." The '912 patent does not contain any disclosure relating to generation of a set of output control signals that corresponds to the first number of ranks (which is the number of ranks on the printed circuit board). Instead, the '912 patent discloses only that the circuit generates a command signal that is sent to an individual rank or ranks selected by the circuit, and does not "correspond to" any number of ranks at all, under any interpretation of the word "correspond." Not only is there a lack of support in the `912 specification for the claimed element, but also the claimed invention is not supported in the Figures presented as required under 37 CFR § 1.83 and MPEP § 608.02(d). The testimony of Dr. Turley in the '386 litigation has confirmed that there is no illustration that shows the claimed element of a second control signal that corresponds to the first number of ranks. Dr. Turley stated that command signals are not shown at all in Figure 1A and B and to the extent that they are shown as Column address strobe (CAS) signals in Figure 3, they do not correspond to the first number of ranks since they address only one rank each. Turley Rough Dep. Trans. at 121:13-123:3. The '912 patent does not show that the inventors of the '912 patent were in possession of the claimed invention at the time the patent was issued, nor does it enable a person of skill in the art to make and use the claimed invention without undue experimentation. Therefore, at least claim 1 is invalid for lack of written description and/or enablement under 35 U.S.C. § 112 ¶ 1 as interpreted by MPEP §§ 2161, 2162, 2163.01, 2163.02, 2163.03, 2164 and 2164.08.