STC.UNM v. Intel Corporation

Filing 55

MEMORANDUM in Support re 54 MOTION to Compel filed by STC. UNM. (Attachments: # 1 Exhibit A, # 2 Exhibit B, # 3 Exhibit C, # 4 Exhibit D, # 5 Exhibit E, # 6 Exhibit F, # 7 Exhibit G, # 8 Exhibit H)(Pedersen, Steven)

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STC.UNM v. Intel Corporation Doc. 55 Att. 5 Exhibit E Technical and Manufacturing Challenges and the Prospect for HVM using ArF Pitch Division, S. Sivakumar Excerpts from Dockets.Justia.com Technical and Manufacturing Challenges and the Prospect for HVM using ArF Pitch Division Sam Sivakumar Intel Corporation 22nm Process ­ 2011 HVM 1.2 1.35NA ArF PD EUV 0.9 1.35NA ArF k1 0.6 0.93NA ArF 0.3 k1 = 0.3 0 100 90 80 70 60 1/2 Pitch (nm) 50 40 30 20 45nm Siva kuma r 15 32nm 22nm 6 th International Symposium on Immersion Lithography Extensions 22nm SRAM Test Chip SRAM, Logic, Mixed-Signal Test Circuits SRAM, Logic, Mixed-Signal Test Circuits Discrete Test Structures Intel is first in the industry to demonstrate working 22 nm circuits Siva kuma r 16 6 th International Symposium on Immersion Lithography Extensions 22nm SRAM Test Chip 0.092 um2 SRAM cell for high density applications 0.108 um2 SRAM cell for low voltage applications 0.092 um2 is the smallest SRAM cell in working circuits reported to date 6 th International Symposium on Immersion Lithography Extensions Siva kuma r 17 15nm Process ­ 2013 HVM 1.2 1.35NA ArF PD EUV 0.9 1.35NA ArF k1 0.6 0.93NA ArF 0.3 k1 = 0.3 0 100 90 80 70 60 1/2 Pitch (nm) 50 40 30 20 45nm Siva kuma r 18 32nm 22nm 15nm 6 th International Symposium on Immersion Lithography Extensions Pitch Division Double Patterning LELE LFLE Spacer Siva kuma r 19 6 th International Symposium on Immersion Lithography Extensions Double Patterning for L/S - LELE Siva kuma r 20 6 th International Symposium on Immersion Lithography Extensions Double Patterning for Vias - LELE + Several different PD options will be picked and used depending on layer-by-layer applicability Siva kuma r 21 6 th International Symposium on Immersion Lithography Extensions

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