Imperium (IP) Holdings, Inc. v. Apple Inc. et al

Filing 1

COMPLAINT FOR PATENT INFRINGEMENT against Apple Inc., Kyocera Communications, Inc., LG Electronics Mobilecomm U.S.A., Inc., LG Electronics U.S.A., Inc., Motorola Mobility Holdings, Inc., Nokia Inc., Research In Motion Corporation, Sony Ericsson Mobile Communications (USA) Inc. ( Filing fee $ 350 receipt number 0540-2962750.), filed by Imperium (IP) Holdings, Inc.. (Attachments: # 1 Exhibit A - US Patent No. 6,271,884, # 2 Exhibit B - US Patent No. 6,838,651, # 3 Exhibit C - US Patent No. 6,838,715, # 4 Exhibit D - US Patent No. 7,064,768, # 5 Exhibit E - US Patent No. 7,109,535, # 6 Civil Cover Sheet)(Fisch, Alan)

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Imperium (IP) Holdings, Inc. v. Apple Inc. et al Doc. 1 Att. 2 Exhibit B Dockets.Justia.com (12) United States Patent Mann (10) (45) Patent NO.: US 6,838,651 ~1 Date of Patent: Jan. 4,2005 (54) HIGH SENSITIVITY SNAP SHOT CMOS IMAGE SENSOR (75) Inventor: Richard A. Mann, Torrance, CA (US) (74) Attorney, Agent, or F i r m q a r j a m i & Farjami LLP (57) ABSTRACT (73) Assignee: ESS Technology, Inc., Fremont, CA (US) ( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. (21) Appl. No.: 10/113,545 (22) Filed: Mar. 28, 2002 The present invention is directed to a solid state imaging device comprising a red pixel, a blue pixel, a first green pixel, a second green pixel, two analog-to-digital converters and a color interpolation circuit. The first analog-to-digital converter converts the output of the red pixel and output of the blue pixel into digital signals. The second analog-todigital converter converts the output of the first green pixel and output of the second green pixel into digital signals. The color interpolation circuit combines the digital signals to determine the color of the pixel. The solid state imaging device may further comprise a third analog-to-digital converter, a fourth analog-to-digital converter, a programmable clock generator and a control. The third analog-to-digital converter converts the output of the blue pixel into a digital signal and the fourth analog-todigital converter converts the output of the second green pixel into a digital signal. The programmable clock generator has a first clock frequency and a second clock frequency, where the first clock frequency is slower than the second clock frequency. The control is coupled to the programmable clock generator, the third analog-to-digital converter and the fourth analog-to-digital converter. The control deactivates the third and fourth analog-to-digital converters if the programmable clock generator is at the first clock frequency, and the control activates the third and fourth analog-todigital converters if the programmable clock generator is at the second clock frequency. 22 Claims, 3 Drawing Sheets (51) Int. CL7 ................................................ HOlL 27/00 (52) U.S. C1. ............................. 250/208.1; 2501214 DC; 2501226 (58) Field of Search ....................... 2501208.1, 214 DC, 2501226, 214 R; 3561416, 419; 3411155; 3481272, 294, 273, 280, 266; 3581474, 482 (56) 3,971,065 5,461,425 6,380,880 6,611,289 A A B1 B1 References Cited U.S. PATENT DOCUMENTS * * * * 711976 1011995 412002 812003 Bayer ......................... 3481276 Fowler et al. .............. 3481294 Bidermann ................. 3411155 Yu et al. ..................... 3481265 * cited by examiner Primary Examiner-Thanh X. Luu Assistant ExaminerSeung C. Sohn ---- AID converter Circuit U.S. Patent Jan. 4,2005 Sheet 1 of 3 U.S. Patent Jan. 4,2005 Sheet 2 of 3 FIG. 3 300 lnterpolati Circuit In video systems, CMOS technology is capable of higher frame rates than CCD technology at the same or lower levels of circuit noise because many of the elements can be designed to operate in parallel. In CCD circuits, a single TECHNICAL FIELD 5 amplifier transforms the received charge to voltage and supports the total data rate of the solid-state image sensor's This invention relates generally to solid-state imaging frame rate. In CCD solid-state image sensors, the amplifier devices such as Complementary Metal Oxide Semiconducnoise generally becomes dominant when 30 frames per tor ("CMOS') solid-state imagers. More particularly the second (FPS) is employed for image sizes over several invention relates to a solid-state imaging device implement- 10 hundred thousand pixels. ing multiple analog-to-digital ("A/Dn)converters to obtain CMOS solid-state image sensors, on the other hand, high frame rates. utilize multiple amplifiers that allow a longer settling time between applications and higher frame rate while maintainBACKGROUND OF THE INVENTION ing excellent noise rejection. In addition, CMOS solid-state Solid-state image sensors (also known as "image 1s image sensors may easily be equipped with a precision sensors," "imagers," or "solid-state imagers") have broad analog-to-digital ("A/Dn) converter on the solid-state image applications in many areas including commercial, consumer, sensor chip. industrial, medical, defense and scientific fields. Solid-state In many imaging applications, it is often desirable to take image sensors convert a received image such as from an a snap shot of a video image (i.e., to obtain a still image). object into a signal indicative of the received image. 20 Unfortunately, because video images are not generally of the Examples of solid-state image sensors including charge highest quality, the snap shot of the still image will also not coupled devices ("CCD"), photodiode arrays, charge injecbe of the highest quality. Such snap shots are especially tion devices ("CID"), hybrid focal plane arrays and compleinferior when compared with typical still images generated mentary metal oxide semiconductor ("CMOS") imaging in accordance with any one of a number of still image devices. 25 techniques or standards generally known in the art. Solid-state image sensors are fabricated from semiconTypically, these higher quality still images are generated ductor materials (such as silicon or gallium arsenide) and utilizing specialized image generation software. include imaging arrays of light detecting (i.e., Generally, conventional CCD solid-state imager sensors photosensitive) elements (also known as photodetectors) provide snap shot capability through an interline transfer interconnected to generate analog signals representative of 30 approach. In the interline transfer approach, when a short an image illuminating the device. These imaging arrays are exposure is required to freeze the action, the charge is typically formed from rows and columns of photodetectors transferred from the light collection junction to a junction (such as photodiodes, photoconductors, photocapacitors or shielded from light. The information regarding the light photogates), each of which generate photo-charges. The level is then stored on a storage node in the dark until the photo-charges are the result of photons striking the surface 35 frame can be read. This method typically reduces motion of the semiconductor material of the photodetector, which blur and allows motion to be frozen even when the time to generate free charge carriers (electron-hole pairs) in an read the entire frame is much longer than the integration amount linearly proportional to the incident photon radiatime for the exposure. tion. Conventional CMOS solid-state image sensors have also Each photodetector in the imaging array receives a por- 40 attempted to solve this snap shot capability problem by tion of the light reflected from the object received at the incorporating a storage node in the cell. However, this solid-state image sensor. Each portion is known as a picture storage node must allow the transfer of the charge from the element or "pixel." Each individual pixel provides an output light collection nodes to the storage nodes, which requires an signal corresponding to the radiation intensity falling upon additional transistor in the cell. Such active pixel sensors are its detecting area (also known as the photosensitive or 45 often termed four-transistor cells to distinguish them from detector area) defined by the physical dimensions of the the three-transistor active pixel sensor in CMOS solid-state photodetector. The photo-charges from each pixel are conimage sensors. Typically, the transfer of charge from the verted to a signal (charge signal) or an electrical potential light collection node to the storage node introduces addirepresentative of the energy level reflected from a respective tional reset or kT/C noise unless a very specialized field portion of the object. The resulting signal or potential is read 50 effect transistor ("FET") design is used. Additionally, cross and processed by video processing circuitry to create an talk may cause the storage node to continue to respond to electrical representation of the image. This signal may be light at 10% to 20% of the response of the lighted node. utilized, for example, to display a corresponding image on a Moreover, the area required to implement the storage node monitor or otherwise used to provide information about the also reduces the area available for light collection. optical image. 55 Generally, for small pitch solid-state image sensor cells, the CCDs are commonly utilized as solid-state image sensors. installation of a storage node reduces the available area for However, CMOS technology has made significant strides in light collection by about 30% to 50%. The combined effects competing with CCD technology as the solid-state image of less light collection area, transfer kT/C noise and cross sensor of choice for use in various applications such as talk may cause the four-transistor cell to have a signal-tostand-alone digital cameras and digital cameras embedded in 60 noise performance that is about ! that of a conventional h other imaging devices (e.g., cellular phones and personal three-transistor cell of the same pitch. Therefore, there is a digital assistants). The principal advantages of CMOS techneed for a high performance solid-state image sensor that nology are lower power consumption, higher levels of solves the snap shot capability problem. system integration that enable the creation of "camera-onSUMMARY a-chip" capabilities, the ability to support very high data 65 Anumber of technical advances are achieved in the art by rates and the ease of manufacturing through the utilization of combining multiple A/D converters in a single CMOS standard CMOS wafer fabrication facilities. HIGH SENSITIVITY SNAP SHOT CMOS IMAGE SENSOR US 6,838,651 B1 3 imager camera chip to attain very high frame rates. There are four color channels (one red, one blue and two greens) used to define a color image based upon the Bayer Pattern of color filters. Since each of the color signals must receive an independent gain and offset adjustment as Part of the image color reconstruction, it is natural to use a separate A/D converter for each of the color channels. In the alternative, two A/D converters may be employed, where one A/D converter is used for the red and blue channels and the second A/D converter is used for the green channels. In this manner, there is no addition to the fixed pattern noise of the imager that would arise from mismatch or offset in the two AID converters. ACMOS imager system with a variable frame rate can be employed to accommodate very high frame rates (>60FPS) for digital still applications to freeze motion, and lower frame rates (-30 FPS) for viewfinder or motion picture application. The variable frame rate saves power during continuous operation as the high frame rate for digital still application is employed only during the capture of a still picture at high shutter speed. Preferably, the variable frame rate is controlled by a programmable clock frequency for the imager core. When the frame rate is low, the imager core is As the frame rate is increased, a higher 'lock rate is to the imager 'Ore' For power savings, only two of the four analog-to-digital converters will be selected for low frame rates. When a high frame rate is selected, the additional analog-to-digital converters will be powered. F~~example, a solid state imaging device of the present invention comprises a red pixel, a blue pixel, a first green pixel, a second green pixel, two analog-to-digital converters and a color interpolation circuit. The first analog-to-digital converter converts the outputs of the red pixel and the blue pixel into digital signals. The second analog-to-digital converter converts the outputs of the first green pixel and the second green pixel into digital signals. The color interpolation circuit combines the digital signals. The solid state imaging device may further comprise a third analog-to-digital converter, a fourth analog-to-digital converter, a programmable clock generator and a control, The third analog-to-digital converter converts the output of the blue pixel into a digital signal and the fourth analog-todigital converter converts the output of the second green pixel into a digital signal. The programmable clock generator has a first clock frequency and a second clock frequency, where the first clock frequency is slower than the second clock frequency. The control is coupled to the programmable clock generator, the third analog-to-digital converter and the fourth analog-to-digital converter. The control deactivates the third and fourth analog-to-digital converters if the programmable clock generator is at the first clock frequency, and the control activates the third and fourth analog-todigital converters if the programmable clock generator is at the second clock frequency. In another example, a solid state imaging device of the present invention comprises a red pixel, a blue pixel, a first green pixel, a second green pixel, four analog-to-digital converters and a color interpolation circuit. The first analogto-digital converter converts the output of the red pixel into a digital signal. The second analog-to-digital converter converts the output of the blue pixel into a digital signal. The third analog-to-digital converter converts the output of the first green pixel into a digital signal. The fourth analog-todigital converter converts the output of the second green pixel into a digital signal. The color interpolation circuit combines the four digital signals. 4 Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional s systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims, lo BRIEF DESCRIPTION OF THE FIGURES The invention can be better understood with reference to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principals of the invention. Moreover, in the figures, like reference numerals designate corresponding Parts throughout the different views. FIG. 1 illustrates a block diagram of a solid state imaging device having two analog-to-digital converters, in accordance with the present invention. FIG. 2 illustrates a block diagram of a solid state imaging device having four analog-to-digital converters, in actordance with the present invention, FIG, illustrates a block diagram of a solid state imaging device having four analog-to-digital converters and a variable frame rate, in accordance with the present invention, DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 20 25 FIG. 1 illustrates a solid state imaging device 100 in accordance with the present invention. The imaging device 100 comprises a two-dimensional array of image pixels 102 On a lo4 using four red, One and greens) define a image. Each pixel 35 102 is either a red pixel 106 having a red ~hotodiode, blue a pixel lo8 having a photodiode Or a green pixel 1 112 1, having a green photodiode. The standard uses identical photodiode construction for each of the sensing The green photodiode green light green light is to strike the photodiode 40 since through the In a manner, a preferential response is created to and red light. The output of each pixel 102 is a signal ~ r o ~ o r t i o nto lthe a amount of light incident on the pixel 102.Accordingly, the 45 Output of the red pixel 106 is a signal ~ r o ~ o r t i o n tol the a amount of red light incident on the pixel 106.Similarly, the Output of the blue pixel 108 is a signal ~ r o ~ o r t i o ntol the a amount of blue light incident on the pixel 108 and the output of the green pixels 110, 112 is a signal ~ r o ~ o r t i o ntol the a so amount of green light incident on the pixels 110, 112. The solid state imaging device of the present invention defines a color image based upon the Bayer pattern of color filters. In particular, the imager system comprises green pixels 110, 112 in checkerboard pattern. Thus, the green 55 pixels 110,112 exist in both odd rows (110) and even rows (112). The blue pixels 108 are shown alternating with the green pixels 110 in the odd rows, and the red pixels 106 are shown alternating with the green pixels 110 in the even ~ o w sAlternatively, the blue pixels 108 may alternate with . 60 the green pixels 112 in the even rows and the red pixels 106 may alternate with the green pixels 110 in the odd mws. The imaging device 100 also comprises a first analog-todigital converter 114, a second analog-to-digital converter 116,an error compensating circuit 118 and a color interpo65 lation circuit 120. The first analog-to-digital converter 114 is disposed on the chip 104,and converts the outputs of the red pixels 106 and the blue pixels 108 into digital signals. The 30 US 6,838,651 B1 5 second analog-to-digital converter 116 is also disposed on the chip 104, and converts the outputs of the green pixels 110, 112 into digital signals. The error compensation circuit 118 provides an independent gain to correct the gain for each color channel. The error compensation circuit 118 also provides an independent offset to correct the fixed pattern noise offset for each color channel. Small adjustments to the gain and offset can be self-calibrated by the imager 100 by the self-testing of black and white reference rows each time the imager 100 is powered. The correction coeficients for the pair of green AID converters 116 can then be automatically derived and stored on chip static RAM. is used determine the red, green and blue light incident on each pixel. This process averages the Outputs pixels 6 fixed pattern noise offset for each pixel 302, and the color interpolation circuit 324 performs the interpolation for each pixel 302 to determine the color of the pixel 302. The color interpolation circuit 324 may be located on a second 326, as shown in FIG, 3, Alternatively, the color interpolation circuit 324 may be located on chip 304, The imaging device 300 further comprises a programmable clock generator 328 and a control 330. The programmable clock generator 328 controls the frame rate of the solid state imaging device 300. The programmable clock generator 328 has a plurality of clock frequencies, including a first clock frequency and a second clock frequency. The first ,-lock frequency is slower than the second ,-lock fiequency, The control 330 is coupled to the programmable clock generator 328 and the analog-to-digital converters 314,316,318,320. The control 330 deactivates the third and fourth analog-to-digital converters 318,320 if the programmable ,-lock generator 328 is at the first ,-lock frequency and activates the third and fourth analog-to-digital converters 3318, 320 if the programmable clock generator 328 is at the second ,-lock frequency, In addition, the control 330 sets the first analog-to-digital converter 314 to convert only the outputs of the red pixels 306 into digital signals, and sets the second analog-to-digital converter 316 to convert only the outputs of the first green pixels 310 into digital signals when the programmable clock generator 328 is at the second clock frequency, The imaging device 300 can be employed to accommodate a plurality of frame rates. Very high frame rates (>60 FPS) are used for digital still applications to freeze motion, and lower frame rates (-30 FPS) are used for viewfinder or motion picture application. The variable frame rate saves power during continuous operation as the high frame rate for digital still application is employed only during the capture of a still picture at high shutter speed. When the frame rate is low, the imager core is clocked more slowly. As the frame rate is increased, a higher clock rate is applied to the imager two of the four 'Ore' For power savings, digital converters will be selected for low frame rates. When a high frame rate is selected, the additional analog-to-digital converters will be powered, 5 10 15 to approximate each unknown data. For for any given pixel lo8, process of the determines the green the pixel lo8 averaging the Outputs the green pixels 11, 112 the left and the right the pixel 20 the red the pixel lo8 determined is averaging the outputs of the red pixels 106 diagonally adjacent to the pixel The circuit 120 performs the interpolation for each pixel 102 to determine the color of the pixel 102. The color interpolation circuit 120 may be located 2s On a 122, as in the color interpolation circuit 120 may be located on chip 104. FIG. 2 illustrates a second example of a solid state imaging device 200 in accordance with the present invention. Similar to the imaging device 100 of FIG. 1, the 30 imaging device 200 comprises a two-dimensional array of image pixels 202 disposed on a chip 204. Each pixel 202 is a red pixel 206, a blue pixel 208, or a green pixel 210,212. The imaging device 200 also comprises four AID converters 214,216,218,220, an error compensation circuit 222 and a 35 color interpolation circuit 224. The first A/D converter 214 converts the outputs of the red pixels 206 into digital signals, the second AID converter 216 converts the outputs of the blue pixels 208 into digital signals, the third AID converter 218 converts the outputs of the green pixels 210 into digital 40 signals and the fourth A/D converter 220 converts the outputs of the green pixels 212 into digital signals. The error compensation circuit 222 corrects the gain and the fixed The use and A/D ers in a CMOS imager architecture raises the possibility of pattern noise offset for each color channel, and the color To minimize fixed pattern interpolation circuit 224 performs the interpolation for each 45 increased fixed pattern pixel 202 to determine the color of the pixel 202. The color it is that averaging adjacent interpolation circuit 224 may be located on a second chip green pixels be applied to blur any small offset between the third and fourth AID converters. Since the rest of the color 226, as shown in FIG, 2, dternatively, the color interpolareconstruction is done by averaging over neighboring pixels, tion circuit 224 may be located on chip 204. of mismatch between A/D converters FIG, 3 illustrates a third example of a solid state imaging so the be device 300 in accordance with the present invention. As with For digital still applications, the low light level perforthe previous examples, the solid state imaging device 300 mance will be at least 50% better with the high frame rate comprises a two-dimensional array of image pixels 302 approach of the Present invention. When low light pictures disposed on a chip 304, where each pixel 302 is either a red pixel 306, a blue pixel 308, or a green pixel 310, 312. The ss are taken, the high-speed capability will not be employed. imaging device 300 also comprises four analog-to-digital The improved performance comes from increased light collection area afforded by the absence of a Per pixel storage converters 314,316,318,320, an error compensation circuit 322 and a color interpolation circuit 324. The first analogelement. For example, a 4.0-micron pitch CMOS imager in to-digital converter 314 converts the outputs of the red deep submicron design rules will have a 25% fill factor for pixels 306 and the blue pixels 308 into digital signals, ~h~ 60 light collection when a four-transistor pixel with an integral Storage node is employed. If this same 4.0-micron pixel second analog-to-digital converter 316 converts the outputs of the first and second green pixels 310, 312 into digital pitch is employed to render a 3.0-transistor pixel without a storage node, then the fill factor of the pixel is 65%. This is signals, The third analog-to-digital converter 318 converts a2.6~ improvement in signal-to-noise at low light levels. the outputs of the blue pixels 308 into digital signals, and the fourth analog-to-digital converter 320 converts the outputs 65 The conventional four-transistor approach will not work of the second green pixels 312 into digital signals. The error as well as the 3.0-transistor pixel without a storage node in strong illumination. In addition, cross talk of 10% to 20% compensation circuit 322 is used to correct the gain and the US 6,838,651 B1 7 adds noise to the storage element when a conventional four-transistor cell is employed. In this instance, a high frame rate is still needed for exposures under strong illumination. Without a high frame rate, the four-transistor cell image data will be highly distorted by the cross talk from 5 light received after the "electronic shutter is closed" but before the information can be read. Therefore, unless the cross talk can be completely suppressed, the four-transistor approach requires a high frame rate to succeed and collects only 39% of the low light signal as the new high frame rate 10 approach. The conventional four-transistor approach will not work as well as the high frame rate approach when working with modest light levels. With the four-transistor approach, a 2 . 6 ~ longer exposure will be required just to achieve an accept- 15 able signal-to-noise ratio. Thus, the range of situations in which suficient light is available to freeze action is reduced compared to the high frame rate approach of the Present invention. In a 0.25 micron design rule, it is possible to have less 20 than 10 electrons read noise while sustaining high data rates by multiplexing the per column analog circuits. To sustain a high overall frame rate, a very high speedA/D converter can be designed with up to 50 megapixel data rates. However, significantly lower power consumption can be achieved by 25 the use of multiple A/D converters with each running at 25 to 30 megapixels per second. Acceptable performance can be achieved by comparison to that of more commonly used cameras with a mechanical 30 shutter. It is well accepted that for normal focal length lens (near 45 degree field of view), a minimum shutter speed for snap shot applications is about %oth of a second. Acceptable results can be achieved for typical non-action subjects with in the very steady shutter speeds as low as x O t h Of a photographer, shutter speeds of x Z 5 t h Of 35 hands of a a second achieve acceptable motion capture for most casual photography. When shutter speed faster than about l/looth of a second are called for, the typical 35 mm camera no longer speed, A 40 can open and close the shutter with moving slit approach is used with the width of the slit adjusted to control the exposure. This moving slit is very similar to the electronic scrolling shutter of a digital still camera. Therefore, it is safe to assume that frame rages of %oth of a frame per second are adequate for low-end 45 photography. It can also be estimated that a frame rate of ~ 2 of a second ~ 5 ~ would do an excellent job (comparable to low end 35 mm camera systems) of stopping action for most camera users. The minimum 60 frames per second can be achieved with up to about 2.0 million pixels and the application of four A/D converters. This can be accomplished without serious compromise on signal-to-noise and fixed pattern noise. The overall performance will be superior to a four-transistor design of the same pitch. Video frame rates of 30 frames per 55 second can be achieved with four low power AID converters for imager sized up to four million pixels. In addition, for applications such as movie making and television where power consumption is not an issue, even higher data rates and frame rates can be achieved by a CMOS approach with 60 multiple AID converters. While various embodiments of the application have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. 65 Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents. 8 What is claimed: 1.A solid state imaging device, comprising: a red pixel having an output; a blue pixel having an output; a first green pixel having an output; a second green pixel having an output; a first analog-to-digital converter connected to the output of the red pixel for converting the output of the red pixel into a first digital signal and connected to the output of the blue pixel for converting the output of the blue pixel into a second digital signal; a second analog-to-digital converter connected to the output of the first green pixel for converting the output of the first green pixel into a third digital signal and connected to the output of the second green pixel for converting the output of the second green pixel into a fourth digital signal; and a color interpolation circuit for combining the first, second, third and fourth digital signals. 2. The solid state imaging device of claim 1, further comprising an error compensation circuit for correcting a gain of one of the output of the red pixel, the output of the blue pixel, the output of the first green pixel and the output of the second green pixel. 3. The solid state imaging device of claim 1, further comprising an error compensation circuit for correcting a fixed pattern noise offset from one of the output of the red pixel, the output of the blue pixel, the output of the first green pixel and the output of the second green pixel. 4. The solid state imaging device of claim 1 further comprising a first chip and a second chip, wherein the red pixel, the blue pixel, the first green pixel, the second green pixel, the first analog-to-digital converter and the second analog-to-digital converter are disposed on the first chip and the color interpolation circuit is disposed on the second chip. 5 . The solid state imaging device of claim 1 further comprising a chip, wherein the red pixel, the blue pixel, the first green pixel, the second green pixel, the first analog-todigital converter, the second analog-to-digital converter and the color interpolation circuit are disposed on the chip. 6. The solid state imaging device of claim 1, further comprising: a third analog-to-digital converter connected to the output of the blue pixel for converting the output of the blue pixel into a fifth digital signal; a fourth analog-to-digital converter connected to the output of the second green pixel for converting the output of the second green pixel into a sixth digital signal; a programmable clock generator having a first clock frequency and a second clock frequency, wherein the first clock frequency is slower than the second clock frequency; and a control coupled to the programmable clock generator, the first analog-to-digital converter, the second analogto-digital converter, the third analog-to-digital converter and the fourth analog-to-digital converter, wherein, if the programmable clock generator is at the first clock frequency, the control deactivates the third and fourth analog-to-digital converters, and sets the first analog-to-digital converter to convert the output of the blue pixel into the second digital signal and the second analog-to-digital converter to convert the output of the second green pixel into the fourth digital signal, and wherein, if the programmable clock generator is at the second clock frequency, the control activates the third US 6,838,651 B1 9 10 analog-to-digital converter to convert the output of the analog-to-digital converter, the second analog-to-digital blue pixel into the fifth digital signal and the fourth converter and the color interpolation circuit are disposed on analog-to-digital converter to convert the output of the the chip. second green pixel into the sixth digital signal, and sets 16, The solid state imaging device of claim 13, further the first analog-to-digital converter not to convert the 5 comprising: Output of the pixel into the second digita1 a third analog-to-digital converter connected to the output and the second analog-to-digital converter not to conof the blue pixel for converting the output of the blue vert the output of the second green pixel into the fourth pixels into a fifth digital signal; digital signal. a fourth analog-to-digital converter connected to the out7. The solid state imaging device of claim 6, wherein the lo put of the second green pixel for converting the output first analog-to-digital converter converts the output of the of the second green pixels into a sixth digital signal; red pixel and the second analog-to-digital converter converts the output of the first green pixel when the programmable a programmable clock generator having a first clock clock generator is at the second clock frequency. frequency and a second clock frequency, wherein the 8. The solid state imaging device of claim 6, wherein the first clock frequency is slower than the second clock programmable clock generator controls a frame rate of the l5 frequency; and solid state imaging device. a cOntrO1 the programmable generator, 9, The solid state imaging device of claim 6, wherein the the first analog-to-digital converter, the second analogprogrammable clock generator comprises a plurality of to-digital converter, the third analog-to-digital conclock frequencies. 10. The solid state imaging device of claim 6 further 20 verter and the fourth analog-to-digital converter, comprising a first chip and a second chip, wherein the red wherein, if the programmable clock generator is at the pixel, the blue pixel, the first green pixel, the second green first clock frequency, the control deactivates the third pixel, the first analog-to-digital converter, the second and fourth analog-to-digital converters, and sets the analog-to-digital converter, the third analog-to-digital first analog-to-digital converter to convert the output of converter, the fourth analog-to-digital converter, the pro- 25 the blue pixels into the second digital signal and the grammable clock generator and the control are disposed on second analog-to-digital converter to convert the output the first chip and the color interpolation circuit is disposed of the second green pixels into the fourth digital signal, on the second chip. and 11. The solid state imaging device of claim 6 further wherein, if the programmable generator is at the comprising a ,-hip, wherein the red pixel, the blue pixel, the 30 second clock frequency, the control activates the third first green pixel, the second green pixel, the first analog-toanalog-to-digital converter to convert the output of the digital converter, the second analog-to-digital converter, the blue pixels into the fifth digital signal and the fourth third analog-to-digital converter, the fourth analog-to-digital analog-to-digital converter to convert the output of the converter, the programmable clock generator, the control second green pixels into the sixth digital signal, and and the color interpolation circuit are disposed on the chip. 35 sets the first analog-to-digital converter not to convert 12. The solid state imaging device of claim 6, wherein the the output of the blue pixels into the second digital fifth digital signal is substantially the same as the second signal and the second analog-to-digital converter not to digital signal and the sixth digital signal is substantially the convert the output of the second green pixels into the same as the fourth digital signal. fourth digital signal. 13. A solid state imaging device, comprising: 40 17. The solid state imaging device of claim 16, wherein groups of pixels, wherein each of said groups of pixels the fifth digital signal is substantially the same as the second include: digital signal and the sixth digital signal is substantially the a red pixel having an output; same as the fourth digital signal. a blue pixel having an output; 18. An imaging method comprising: a first green pixel having an output; and 45 converting an output of a red pixel into a first digital a second green pixel having an output; signal using a first analog-to-digital converter; a first analog-to-digital converter connected to the output converting an output of a blue pixel into a second digital of the red pixel for converting the output of the red signal using the first analog-to-digital converter; pixels into a first digital signal and connected to the converting an output of a first green pixel into a third output of the blue pixel for converting the output of the digital signal using a second analog-to-digital conblue pixels into a second digital signal; verter; a second analog-to-digital converter connected to the converting an output of a second green pixel into a fourth output of the first green pixel for converting the output digital signal using the second analog-to-digital conof the first green pixels into a third digital signal and verter; and connected to the output of the second green pixel for 5s converting the output of the second green pixels into a combining the first, second, third and fourth digital sigfourth digital signal; and nals using a color interpolation circuit. 19. The imaging method of claim 18 further comprising: a color interpolation circuit for combining the first, second, third and fourth digital signals. correcting a gain of one of the output of the red pixel, the 14. The solid state imaging device of claim 13 further 60 output of the blue pixel, the output of the first green pixel comprising a first chip and a second chip, wherein the and the output of the second green pixel. groups of pixels, the first analog-to-digital converter and the 20. The imaging method of claim 18 further comprising: second analog-to-digital converter are disposed on the first correcting a fixed pattern noise offset from one of the output chip and the color interpolation circuit is disposed on the of the red pixel, the output of the blue pixel, the output of the 65 first green pixel and the output of the second green pixel. second chip. 15. The solid state imaging device of claim 13 further 21. The imaging method of claim 18, wherein the red comprising a chip, wherein the groups of pixels, the first pixel, the blue pixel, the first green pixel, the second green US 6,838,651 B1 11 pixel, the first analog-to-digital converter and the second analog-to-digital converter are disposed on a first chip and the color interpolation circuit is disposed on a second chip. 22. The imaging method of claim 18, wherein the red pixel, the blue pixel, the first green pixel, the second green 12 pixel, the first analog-to-digital converter, the second analog-to-digital converter and the color interpolation circuit are disposed on a chip. * * * * *

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