Imperium (IP) Holdings, Inc. v. Apple Inc. et al

Filing 1

COMPLAINT FOR PATENT INFRINGEMENT against Apple Inc., Kyocera Communications, Inc., LG Electronics Mobilecomm U.S.A., Inc., LG Electronics U.S.A., Inc., Motorola Mobility Holdings, Inc., Nokia Inc., Research In Motion Corporation, Sony Ericsson Mobile Communications (USA) Inc. ( Filing fee $ 350 receipt number 0540-2962750.), filed by Imperium (IP) Holdings, Inc.. (Attachments: # 1 Exhibit A - US Patent No. 6,271,884, # 2 Exhibit B - US Patent No. 6,838,651, # 3 Exhibit C - US Patent No. 6,838,715, # 4 Exhibit D - US Patent No. 7,064,768, # 5 Exhibit E - US Patent No. 7,109,535, # 6 Civil Cover Sheet)(Fisch, Alan)

Imperium (IP) Holdings, Inc. v. Apple Inc. et al

Doc. 1 Att. 3

Exhibit C

Dockets.Justia.com

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United States Patent
Bencuya et al.
CMOS IMAGE SENSOR ARRANGEMENT WITH REDUCED PIXEL LIGHT SHADOWING
Inventors: Selim Bencuya, Irvine, CA (US); Richard Mann, Torrance, CA (US); Erik Stauber, San Diego, CA (US) Assignee: ESS Technology, Inc., Fremont, CA (US) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 25 days.

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Patent NO.: US 6,838,715 ~1 Date of Patent: Jan. 4,2005

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References Cited
U.S. PATENT DOCUMENTS
6,171,885 B1 6,242,769 B1

* 112001 Fan et al. ..................... 438170 * 612001 Chang et al. ............... 2571291

* cited by examiner
Primary ExaminerAong Pham Assistant Examiner-Wai-Sing Louie (74) Attorney, Agent, or F i r m q a r j a m i & Farjami LLP (57)

ABSTRACT

Appl. No.: 101425,488 Filed:

Apr. 29, 2003 Related U.S. Application Data

Provisional application No. 601376,750, filed on Apr. 30, 2002.

Int. CL7 .............................................. HOlL 311062 U.S. C1. ....................... 2571291; 2571184; 2571187;
2571203; 2571292; 2571293; 2571433; 2571461; 2571462; 2571929 Field of Search ................................. 2571184, 187, 2571203,221, 291-293, 462, 929

An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing. 20 Claims, 6 Drawing Sheets

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the photodetector, the transistor region, and the metal interconnect segments, as well other structural elements, has presented problems. A major problem which conventional CMOS image sensors exhibit is pixel light shadowing (also RELATED APPLICATIONS s referred to as "geometric shadowing"). Pixel light shadowing is caused when the average ray or principal ray striking The present application claims the benefit of U.S. provithe pixel deviates significantly from normal (or ~erpendicusional patent application Ser. No. 601376,750, filed on Apr. la' to the imaging array plane). Under these conditions, one 30, 2002, the disclosure of which is hereby fully incorpoor more of the pixel elements situated over the photodetector rated by reference in the present application. 10 may block a significant amount of light from being directed BACKGROUND OF THE INVENTION at the photodetector. As a result, the brightness of the resulting image is significantly reduced, resulting in poor 1. Field of the Invention image quality. the pixels situated at the periphery The present invention is generally in the field of solid state the imaging array are 'knificantly more to imaging devices, More specifically, the invention is in the field of Complementary Metal Oxide S e m ~ c o n ~ u c t oIS pixel light shadowing. As a result, the resulting images have r significant and undesirable brightness falls off at the edges ("CMOS") imaging devices. of the field of view. This problem is further exacerbated due 2. Related Art to the loss of brightness at the edge of field of view common image as to most lens systems due to l/Cosine effects. Consequently, imagers," ''image sensors," and ''imagers") have broad 20 the resulting image exhibits unacceptable signal-to-noise applications in many areas and in a number of fields. (SNR), particularly at the corners of the images. These image sensors 'Onvert a received image into a problems are further aggravated under low light conditions, signal indicative of the received image. Examples of solidAccordingly, there is a strong need in the art for a CMOS state image sensors include charge coupled devices image sensor arrangement and method for arranging image ("CCD"), photodiode arrays, charge injection devices 25 sensor elements, which significantly reduces pixel light ("CID"), hybrid focal plane arrays and CMOS imaging shadowing. devices (also known as "CMOS image sensors" or "CMOS SUMMARY OF THE INVENTION imaging arrays"). Solid-state image sensors are fabricated from semiconThe present invention is directed to a CMOS image sensor ductor materials, such as silicon or gallium arsenide, and 30 arrangement and method for arranging image sensor elements which significantly reduce pixel light shadowing. In comprise imaging arrays of light detecting, i.e., one exemplary embodiment, the CMOS image sensor cornphotosensitive, elements (also known as "photodetectors" or "photoreceptors") interconnected to generate analog signals prises a plurality of pixels arranged in an array. The plurality representative of an image illuminating the device. A typical of pixels includes a first pixel proximate an optical center of imaging array comprises a number of photodetectors 35 the array, and a second pixel proximate a peripheral edge of arranged into rows and columns, each photodetector generthe array. The CMOS image sensor further comprises a first ating photo-charges. The photo-charges are the result of metal interconnect segment associated with the first pixel photons striking the surface of the semiconductor material of situated in a first metal layer, and a second metal interconthe photodetector, and generating free charge carriers nect segment associated with the second pixel situated in the (electron-hole pairs) in an amount linearly proportional to 40 first metal layer. In accordance with the present invention, the incident photon radiation. The photo-charges from each the second metal interconnect segment is shifted closer to pixel are converted to a "charge signal" which is an electhe optical center of the array than the first metal intercontrical potential representative of the energy level reflected nect segment so that the second metal interconnect segment from a respective portion of the object and received by the approximately aligns with a principle ray angle incident the solid-state image sensor. The resulting signal or potential is 45 second pixel. The photodiode elements and transistor eleread and processed by videolimage processing circuitry to ments of the pixels of the array remain on a fixed pitch. create a signal representation of the image. However, the metal interconnect segments and other pixel In recent years, CMOS image sensors have become a elements associated with the pixels of the array are posipractical implementation option for imagers and provide tioned on a variable pitch such that these metal interconnect cost and power advantages over other technologies such as so segments and pixel elements are shifted towards the optical CCD or CID. A conventional CMOS image sensor is typicenter in proportion to the distance of the metal interconnect cally structured as an imaging array of pixels, each pixel segment or associated pixel element from the optical center including a photodetector and a transistor region, and as and in proportion to the distance of the metal interconnect discussed above, each pixel converts the incoming light into segment or pixel element from the surface of the photodiode. an electronic signal. In a typical three-transistor active pixel 5s Thus metal interconnect segments and pixel elements can design for a CMOS image sensor, each pixel includes four be positioned at a designated offset position so that the shifts of the metal interconnect segments and pixel elements wires (or "metal interconnect lines" or "metal interconnect segments") and three transistors, namely, a reset transistor, approximately align to the principle ray angle of the lens a source-follower transistor, and a select transistor. TWO incident to the pixel in each location in the array, thereby metal interconnect segments are disposed horizontally to 60 substantially reducing pixel light shadowing. Proximate the optical center where the principle ray angle is aligned provide row selection for either resetting the pixel or reading the pixel. Two other metal interconnect segments are dissubstantially perpendicular to the wafer, the metal interconposed vertically (or substantially perpendicular to the first nect segments are all aligned above the transistor and isolation regions of the pixel leaving the photodiode unobtwo metal interconnect segments) to provide column selection for both reading and resetting the pixel. 65 scured to collecting light. In comparison, proximate the In conventional CMOS image sensors, the arrangement of corners of the array or proximate the periphery of the array, the pixel's structures, including the relative positioning of the metal interconnect segments associated with those pixels

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are shifted so as to appear to be "tilted" towards the optical FIG. 4 illustrates a simplified cross-sectional view of center of the array to thereby align the light collection path camera system in accordance with one embodiment of the with the principle ray angle incident the respective pixels. present invention. Such tilts can be typically in the range of 15 to 25 degrees s DETAILED DESCRIPTION OF THE for certain lenses. INVENTION This offset positioning (or shift) of the interconnect elements and other pixel elements towards the optical center of The present invention is directed to a CMOS image sensor the array progressively increases in small intervals at the arrangement and method for arranging image elesubsequent pixel placements in proportion to the distance of ments. The following description contains specific informathe pixel from the optical center of the array, ~h~~~shifts can tion pertaining to the implementation of the present invenbe applied along a horizontal dimension of the array, a tion. One skilled in the art will recognize that the present vertical dimension of the arrav., or both a horizontal , invention may be implemented in a manner different from and vertical dimension of the array, Wi;h this arrangement that specifically discussed in the present application. the transistor and diode elements of the pixel are always Moreover, some of the specific details of the invention are placed in positions corresponding to a fixed pixel pitch interval. not discussed in order to not obscure the invention. The specific details not described in the present application are According to another embodiment, the CMOS image within the knowledge of a person of ordinary skill in the art. sensor further comprises a third metal interconnect associated with the first pixel, and a fourth metal interconnect The drawings in the present application and their accomsegment associated with the second pixel, where the third panying detailed description are directed to merely exemand fourth metal interconnect segment are situated in a 20 plary embodiments of the invention. To maintain brevity, second metal layer. In this case, the fourth metal interconother embodiments of the invention which use the principles nect segment is shifted closer to the optical center than the of the present invention are not specifically described in the third metal interconnect segment. Where the first metal layer present application and are not specifically illustrated by the is situated below the second metal layer, the fourth metal present drawings. It is noted that, for ease of illustration, the interconnect segment is shifted closer to the optical center 25 various elements and dimensions shown in the drawings are than the second metal interconnect segment. These metal not drawn to scale. interconnect elements may comprise metal lines and vertical ~ ~first to FIG, 1 ~ a ,top view of a portion of f ~ ~ ~ i via structures to connect the different layers of metal CMOS imaging array 100 is shown including a plurality of together. 1n certain embodiments, a first via is situated 30 pixels 102, arranged into rows and columns, each pixel 102 between the first metal interconnect segment and the third generating photo-charges. The photo-charges generated by metal interconnect segment, and a second via is situated pixels 102 are the result of photons striking the surface of the between the segment and the semiconductor material of the photodetector, and generating fourth metal interconnect segment. free charge carriers (electron-hole pairs) in an amount linAccording to another embodiment, the CMOS image 35 early proportional to the incident photon radiation. Pixel 102 sensor further comprises a first micro lens associated with in region 104 of imaging array 100 will now be described the first pixel, and a second micro lens associated with the with reference to FIG. 1B. second pixel. In this particular embodiment, a second micro 1, FIG, 1 ~region 104 and pixel 102 are shown in an , lens is shifted closer to the optical center than the first micro enlarged view, pixel 102 illustrates a three-transistor active lens. 40 pixel design including photodetector 106 (such as a According to another embodiment, the CMOS image photodiode), reset transistor 108, source-follower transistor sensor further comprises a first color filter associated with 110, and select transistor 112. The active area of transistors the first pixel and a second color filter associated with the 108,110 and 112 is depicted as region 114 in FIG, 1 ~ .an second pixel. In this particular embodiment, a second color effort to avoid blocking photodetector 106, multiple layer filter is shifted closer to the optical center than the first color 45 metal construction is typically used in CMOS imaging filler. arrays. For example, in FIG. l B , metal interconnect segIn another embodiment, the invention is a method for ments 116 and 118 are vertically positioned and may, for arranging the pixel elements according to the aboveexample, be provided in metal layer two. Metal interconnect described arrangement. Other features and advantages of the segments 120 and 122 are horizontally positioned and may, present invention will become more readily apparent to 50 for example, be provided in metal layer three and metal layer those of ordinary skill in the art after reviewing the followone, respectively. Metal interconnect segments 116 and 118 ing detailed description and accompanying drawings. may be used to provide column selection for both reading and resetting of photodetector 106. Metal interconnect s e c BRIEF DESCRIPTION OF THE DRAWINGS ment 120 may be used to provide resetting of photodetector lAillustrates a top view of a imaging 55 106, while metal interconnect segment 122 may be used to array. provide reading of photodetector 106. FIG. 1B illustrates an enlarged view pixel of FIG. 1A. Referring now to FIG. 2A, a cross sectional-view of FIG. 2A illustrates a cross sectional-view of a known known CMOS imaging array 200 is generally shown, CMOS imaging array. Known CMOS imaging array 200 includes pixels 202, 204 FIG. 2B illustrates the effect of a non-~erpendicular 60 and 206, wherein pixel 202 is situated in closer proximity to principle ray upon a known CMOS imaging array. optical center axis 236 than pixel 206. Optical center axis FIG. 3 A illustrates a cross sectional-view of a CMOS 236 of imaging array 200 corresponds to a reference line imaging array in accordance with one embodiment of the perpendicular to the surface plane of CMOS imaging array present invention. 200, intersecting a center point of CMOS imaging array 200. FIG. 3B illustrates the effect of a non-perpendicular 65 By way of illustration, pixel 202 may be situated adjacent or principle ray upon a CMOS imaging array according to one proximate to optical center axis 236, and pixel 206 may be embodiment of the present invention. at or proximate the edge or periphery of known CMOS

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9 6 imaging array 200. Each pixel 202 and 206 comprises 270 and ray bundle 274 are redirected by micro lens 234 and passed through color filter 232. However, because of the respective photodetector 208 and 224, transistor region 210 initial incident angles of ray 270 and ray bundle 274, and 224, metal one interconnect segments 212 and 226, redirected rays 272 and 276 do not strike photodetector 222 metal two interconnect segments 214 and 228, metal three interconnect segment 216 and 230, color filter 218 and 232 s but are blocked by pixel elements situated over photodetector 222, including one or more of metal one interconnect and micro lens 220 and 234. segments 226, metal two interconnect segments 228 and Transistor regions 210 and 224 represent an active pixel metal three interconnect segment 230. A significant amount design employing a reset transistor, a source follower tranof illumination will be blocked and prevented from striking sistor and a select transistor, as described above in conjuncphotodetector 222 in this manner, resulting in significantly tion with FIG. 1B. Respective isolation elements 205 are 10 reduced brightness of the resulting image produced by pixel positioned between transistor regions and photodetectors, 206. e.g., between transistor region 210 and photodetector 108, Moreover, light incident pixels proximate optical center and between adjacent pixels, e.g., between pixel 202 and axis 236, e.g., pixel 202, strike surface 235 of those pixels 204. at angles near normal, whereas, pixels near the edge or In known CMOS imaging array 200, metal one interconperiphery of known CMOS imaging array 200, i.e., near the nect segments 212 and 226, metal two interconnect segedge of the field of view of the optical system, e.g., pixel ments 214 and 228, and metal three interconnect segments 206, experience an average ray angle which deviates sig216 and 230 are routed over respective transistor regions nificantly from normal. The resulting image produced by 210 and 224 and isolations regions 205 of pixels 202 and CMOS imaging array 200 thus exhibits significant pixel 206, respectively, to provide electrical connectivity for read- 20 light shadowing as pixels proximate the edges of the field of ing andlor resetting operations involving photodetectors 208 view will produce images that have significant and undesirand 222, respectively, as discussed above. able brightness falls off. This aroblem is further exacerbated a Color filters 218 and 232 allow light of only specific due to the loss of brightness at the edge of field of view wavelengths to be transmitted to respective photodetectors 25 common to most lens systems due to 11Cosine effects. 208 and 222. With the use of color filters, such as filters 218 Consequently, the resulting image exhibits unacceptable and 232, known CMOS imaging array 200 may be used to signal-to-noise (SNR), particularly at the corners of the capture color images. Typically, such color filters are images. These problems are further aggravated under low arranged in a repeating Bayer pattern of red, green, and blue light conditions. filters. Micro lens 220 and 234 are typically formed of a 30 Furthermore, as pixels are scaled to smaller pitches to clear polymer and are situated over respective color filters reduced device size, pixel light shadowing becomes even 218 and 232 to redirect light toward respective photodetecmore pronounced as the available area for the photodetector tors 208 and 222. element is reduced. The conventional approach to addressKnown CMOS imaging array 200 is configured in a ing this problem has been to implement telecentric lenses. conventional arrangement where each pixel, including pix- 35 Telecentric lenses, however, require more optical elements, thereby increasing the height of the lens, which is undesirels 202,204 and 206, are identical in layout and placement of its pixel elements, including corresponding metal interable in many applications, such as pocket-sized or portable connect segments, color filters and micro lenses. Stated electronic devices. In addition, the constraints on the optical differently, each pixel 202, 204 and 206 and its associated design of telecentric lenses can result in adverse reduction in pixel elements, i.e., metal interconnect segments, color filter, 40 Modulation Transfer Function ("MTF), contrast and other and micro lens, is identically arranged with a fixed pitch. important image quality properties. Finally, telecentric Thus, dimension 240 defining the placement of the transistor lenses add undesirable increased costs to the camera system, region 210 of pixel 202 is the same as dimension 242 rendering telecentric lenses unpractical in many applicadefining the placement of transistor region 224 of pixel 206. tions. Likewise the dimension 244 and dimension 246 45 Referring now to FIG. 3A, CMOS imaging array 300 (corresponding to metal one interconnect segments 212 and which addresses and resolves pixel light shadowing in a 226, respectively) are the same, dimension 248 and 250 simplified and cost-effective manner according to one (corresponding to metal two interconnect segments 214 and embodiment of the invention is shown. Pixels 302,304 and 228, respectively) are the same, dimension 252 and 254 306 are shown as part of CMOS imaging array 300 for (corresponding to metal three interconnect segments 216 so illustrative purposes, although CMOS imaging array 300 and 230, respectively) are the same, dimension 260 and 262 typically include a larger number of pixels. As shown in (corresponding to color filters 218 and 232, respectively) are FIG. 3A, pixel 302 is situated in closer proximity to optical the same, and dimension 256 and 258 (corresponding to center axis 336 than aixel 306. Oatical center axis 336 of micro lenses 220 and 234, respectively) are the same. This imaging array 300 corresponds to a reference line perpenidentical layout scheme is carried out in both the horizontal 5s dicular to the surface plane of CMOS imaging array 300, and vertical dimensions in known CMOS imaging array intersecting a center point of CMOS imaging array 300. By 200. way of illustration, pixel 302 may be situated adjacent or proximate to optical center axis 336, and pixel 306 may be This arrangement of pixel elements in known CMOS at or proximate the edge or periphery of CMOS imaging imaging array 200 results in significant pixel light shadowing in the resulting image, particularly under low light 60 array 300. conditions. As discussed above, pixel light shadowing is Each pixel 302 and 306 comprises respective photodetector 308 and 324, transistor region 310 and 324, metal one caused when the average ray or principal ray striking the interconnect segments 312 and 326, metal two interconnect pixel deviates significantly from normal (or perpendicular to the imaging array plane). Referring now to FIG. 2B, prinsegments 314 and 328, metal three interconnect segment cipal ray 270 and ray bundle 274 are shown having incident 65 316 and 330, color filter 318 and 332 and micro lens 320 and angles significantly away from normal or away from per334. As described more fully below, the particular arrangependicular to imaging array surface 235 of pixel 206. Ray ment and placement of metal one interconnect segments 312

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and 326, metal two interconnect segments 314 and 328, performance on the computer system. Once the maximum principle ray angle is determined, the various pixel elements metal three interconnect segment 316 and 330, color filters for one or more pixels of CMOS imaging array 300 are 318 and 332 and micro lenses 320 and 334 of pixels 302 and shifted toward optical center axis 336 to approximately align 306, respectively, results in significantly reduced pixel light 5 with the principle ray angle. According to one embodiment, shadowing and superior resulting images. shifts are applied by using the maximum design grid supTransistor regions 310 and 324 represent an active pixel ported as described more fully below. design employing a reset transistor, a source follower tranWay of i11ustration2 a 22-degree principle sistor and a select transistor, as described above. Respective for an f2.8 lens with a of view ray isolation elements 305 are positioned between transistor 'ystem regions and photodetectors, e.g., between transistor region 10 may be defined for a particular 310 and photodetector 308, and between adjacent pixels, imaging array 300. In with the vertical structure of metal interconnect segments, e.g., metal e,g,, between pixel 302 and 304, By way of illustration, interconnect segments 312, 314, 316, 326, 328, and 330, and isolation elements 305 may comprise shallow trench isolation regions, for example, although other isolation structures the principle ray are used define a required Or shift in the placement of each of the metal interconnect may also be used. segments 312,314,316,326,328, and 330, as well as color One segments 312 and 326, filters 318 and 332 and micro lenses 320 and 334, This shift segments 314 and 328, and three interin the metal interconnect segments 312, 314, 316, 326, 328, connect segments 316 and 330 associated with pixels 302 and 330, filters 318 and 332 and micro lenses 320 and 334 and 306, provide for is directed toward optical center axis 336, and, as shown reading andlor resetting operations involving photodetectors O more clearly below, results in significantly reduced blockage ' 308 and 322, as discussed of incoming light from being directed at photodetectors 308 shown in FIG. 3A for ease of illustration, vias are typically and 322, positioned to provide vertical interconnections between The amount of shift for each pixel element is dependent metal levels corresponding to metal one interconnect seg25 upon the distance of the pixel element from surface 335 of ments 312 and 326, metal two interconnect segments 314 the pixel, the distance of the pixel to optical center axis 336, and 328, and metal three interconnect segments 316 and and the principle ray angle. By way of example, suppose 330. Also not shown in FIG. 3A for ease of illustration is a pixel 306 is situated at the extreme corner of CMOS imaging transparent dielectric that supports and encapsulates metal array 300, dimension 380 defining the distance between one interconnect segments 312 and 326, metal two inter30 micro lens 334 and photodetector 322 is approximately 5 connect segments 314 and 328, and metal three interconnect microns @m), and the camera system has a principle ray segments 316 and 330. angle of 20-degrees, micro lens 334 is shifted by amount 378 318 and 332 light of 'pecific towards the optical center axis 336, Shift 378 is approxiwavelengths to be transmitted to respective photodetectors mately 0,8 pm depending on the shape of the micro lens and 318 and 332. With the Ilse of color filters, such as filters 318 35 its refractive power, The amount of offset or shift for pixel and imaging array 300 may be wed to capture elements situated below micro lens 334, e.g., color filter 332, images. such are arranged in a and metal interconnect segments 326, 328 and 330, are pattern of red, green, and Micro scaled to a lower value in proportion to the relative distance lens 320 and 334 are formed of a polymer and above photodetector 322. In the above example, where pixel are situated over respective color filters 318 and 332 to 40 306 is at the extreme corner of CMOS imaging array 300, redirect light toward respective photodetectors 308 and 322. shift 376 for color filter 332 is approximately 0,64 pm, shift In axordance with the Present invention, the pixel 374 for metal three interconnect segment 330 is approxielements, i.e.9 metal interconnect segments, color filter, mately 0.48 pm, shift 372 for metal two interconnect segmicro lens, etc., a~sociatedwith one or more pixels in ments 328 is approximately 0.32pm, and shift 370 for metal CMOS imaging array 300 are physically shifted towards 45 one interconnect segments 326 is approximately 0.16 pm. optical center axis 336 in order to approximately align with Vias (not shown for ease of illustration) which connect metal the principle ray angle incident each pixel. It is noted that the interconnect segment are also shifted a proportional amount. positioning and arrangement of ~hotodetectors and 322 308 Thus, any vias connecting metal three interconnect segment 300 and metal two interconnect segment 328 would be and transistor regions 310 and 324 of pixels 302 and 306, respectively, are identical and have a fixed pitch. Thus, 50 shifted by an intermediate value of 0.40 pm, and any vias dimension 340 and 342 are the same. connecting metal one interconnect segment 326 and metal Referring to FIG. 4, a simplified cross-sectional view of two interconnect segment 328 would be shifted by an camera system 400 is shown including image sensor 402 intermediate value of 0.24 pm. It is further noted that, situated on substrate 404, where, for example, image sensor contact structures of transistor regions 324 are not shifted, 402 corresponds to CMOS imaging array 300 of FIG. 3A. 5s although the metal one interconnect segment 326 overlap of such contact structures is adjusted to provide adequate Lens holder 406 is positioned over substrate 402 and houses lens assembly 408. As discussed above, in pocket-sized and overlap between contacts structures and metal one interconportable electronic devices, it is desirable to reduce height nect segment 326 after shifting of metal one interconnect 410 of camera system 400. Thus, maximum principal ray segment 326. Thus, transistor regions 324, photodetector 412 and its incident angle 414 are dependent upon on the 60 322, and its respective isolation regions 305 are not shifted. various physical dimensions of camera system 400 as well According to one embodiment, shifts are applied in as the position of image sensor 402 on substrate 404. groups of pixels by an amount equivalent to the supported Continuing with FIG. 3A, the layout and design of CMOS maximum design grid. For example, in 0.25 micron CMOS, imaging array 300 can be carried out using a computer the typical minimum design grid is 0.01 pm. By way of program executed on a computer system. For example, the 65 illustration, a VGA imaging array comprises 640 columns maximum principle ray angle for a particular lens system and 480 rows of pixels. The number of pixels in each shift may be determined by modeling the optical system and pixel group is determined after the maximum shift value is
3323

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determined at the edge of the field of view, i.e., for pixels benefits are achieved without resort to use of telecentric lenses and its associated disadvantages. Thus, lens size can situated at the edge of CMOS imaging array 300, as described above. If, for example, the maximum shift for a be reduced, and lens performance is increased. Moreover, pixel element at the edge or periphery of CMOS imaging since the dimensional tolerance of the manufacturing proarray 300 is determined to be 0.8 pm, smaller shifts will be 5 cess is several times greater than a minimum design grid, applied in increments of 0.01 pm based upon the radial these small shift or offsets will not interfere with the normal distance from optical center axis 336. In the horizontal wafer manufacturing process. dimension, for example, there will be 80 groups of shifts, From the above description of exemplary embodiments of the invention it is manifest that various techniques can be each group including 6 columns (or 6 pixels), each group further away from optical center axis 336 being shifted 0.01 lo used for implementing the concepts of the present invention without departing from its scope. Moreover, while the closer to optical center axis 336. Shifts to the pixel elements invention has been described with specific reference to are also applied in the vertical dimension of CMOS imaging certain embodiments, a person of ordinary skill in the art array 300 in the manner described above. that changes be made in form and In general, shifts are applied in greater magnitudes to pixels elements situated further away from optical center detail the and the the invention. For example, it is manifest that the shift amount axis 336 than pixels structures situated closer to optical values and the number of metal interconnect segments center axis 336. Thus, larger shifts will be applied to metal described above are merely exemplary and may be modified interconnect segments 326, 328 and 330 of pixel 306 than without departing from the scope and spirit of the invention. metal interconnect segments 312,314 and 316 of pixel 302. The described exemplary embodiments are to be considered Likewise, larger shifts will be applied to color filter 332 and 20 in all respects as illustrative and not restrictive. It should also micro lens 334 of pixel 306 than color filter 318 and micro be understood that the invention is not limited to the lens 320 of pixel 302' Referring to One segment 326 particular exemplary embodiments described herein, but is of pixel 306, for example, shift 370 indicates that that metal capable of many rearrangements, modifications, and substione segment 326 is shifted closer to optical center axis 336 tutions without departing from the scope of the invention. relative to pixel 306 than metal one segment 312 relative to 25 a image arrangement and method for pixel 302. Thus, dimension 344 of pixel 302 is greater than arranging image sensor elements with reduced pixel light dimension 346 of pixel 306 by shift amount 370, Likewise, Shadowing has been described. shift 372 indicates that metal two segment 328 of pixel 306 What is 'laimed is: is shifted closer to optical center axis 336 than metal two segment 314 of pixel 302, and shift 374 indicates that metal 30 A image comprising: a plurality of pixels arranged in an array; three segment 330 of pixel 306 is shifted closer to optical said plurality of pixels including a first pixel proximate an center axis 336 than metal three segment 316 of pixel 302. optical center of said array, and a second pixel proxiFurthermore, shift 376 indicates that color filter 332 of pixel mate a peripheral edge of said array; 306 is shifted closer to optical center axis 336 than color a first metal interconnect segment associated with said filter 318 of pixel 302, and shift 378 indicates that micro lens 35 first pixel; and 334 of pixel 306 is shifted closer to optical center axis 336 a second metal interconnect segment associated with said than micro lens 320 of pixel 302. It is noted that exceptions second pixel, wherein said first metal interconnect to this difference in shift amounts between pixels 302 and 306 arise when pixel elements of pixel 302 and 306 are in segment and second metal interconnect segment are situated in a first metal layer, wherein said second metal the same "shift group," in which case those pixel elements 40 in the same shift group are shifted by the same amount, as interconnect segment is shifted closer to said optical noted above. center than said first metal interconnect segment so that said second metal interconnect segment approximately Also as discussed above, pixel elements situated further aligns with a principal ray angle incident said second above pixel surface 335 are shifted by a greater amount in pixel. order to properly align the pixel elements with the principle 45 2. The CMOS image sensor of claim 1, wherein said ray angle. Thus, shift amount 378 is greater than shift second metal interconnect segment is shifted along a horiamount 376. Shift amount 378 is in turn greater than shift zontal dimension of said array. amount 374; shift amount 374 is greater than shift amount 3. The CMOS image sensor of claim 1, wherein said 372; and shift amount 372 is greater than shift amount 370. ~ ~to FIG, 313, principal ray 370 and ray bundle so second metal interconnect segment is shifted along a vertical f ~ ~ ~ i ~ ~ dimension of said array. 374 are shown having incident angles significantly away 4. The CMOS image Sensor of claim 1, wherein said from normal or away from perpendicular to imaging array second metal interconnect segment is shifted along both a surface 335 of pixel 306, R~~ 370 and ray bundle 374 are horizontal and a vertical dimension of said array. redirected by micro lens 334 and passed through color filter 5. The CMOS image Sensor of claim 1, further com~ris332. Due to the particular arrangement of CMOS imaging ss array 300, redirected rays 372 and 376 of principal ray 370 a third metal interconnect segment associated with said and ray bundle 374 strike photodetector 322 but are not first pixel; blocked by metal interconnect segment 326, 328 and 330 a fourth metal interconnect segment associated with said because each of metal interconnect segments 326,328 and 330, color filter 332, and micro lens 334 have been shifted 60 second pixel, wherein said third metal interconnect toward optical center axis 336 to approximately align with segment and said fourth metal interconnect segment are situated in second metal layer, wherein said fourth principle ray 370, as described above. As a result, camera performance is significantly increased, resulting in signifimetal interconnect segment is shifted closer to said cant or complete elimination of pixel light shadowing at the optical center than said third metal interconnect segedges of CMOS imaging array 300. According to one 65 ment so that said fourth metal interconnect segment embodiment, 25%-50% increases in light collection at the approximately aligns with said principal ray striking said second pixel. edges of CMOS imaging array 300 is achieved. These

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6. The CMOS image sensor of claim 5, wherein said first at least a first micro lens element associated with said first pixel, said first micro lens element having a first offset metal layer is situated below said second metal layer, and position; wherein said fourth metal interconnect segment is shifted wherein said first pixel is situated at a periphery of said closer to said optical center than second metal interconnect imaging array, and wherein said first micro lens elesegment. s ment is fabricated at said first offset position so that said 7. The CMOS image sensor of claim 5, further comprising micro lens element approximately aligns with said a first via situated between said first metal interconnect principle ray angle incident said first pixel. segment and said third metal interconnect segment. 16. The CMOS imaging array of claim 15 further corn8. The CMOS image sensor of claim 7, further comprising a second via situated between said second metal intercon- 10 prising: a first color filter associated with said first pixel, said first nect segment and said fourth metal interconnect segment. color filter having a second offset position; 9. The CMOS image sensor of claim 1, further compriswherein said second offset position is derived by proporing: tionally scaling said first offset position according to a a first micro lens situated associated with said first pixel; distance of said first color filter above said photodeand tector relative to a distance of said first micro lens a second micro lens associated with said second pixel, element above said photodetector; wherein said second micro lens is shifted closer to said wherein said first color filter is fabricated over said optical center than said first micro lens. photodetector at said second offset position, and said 10. The CMOS image sensor of claim 1, further comprisfirst micro lens is fabricated over said first color filter. 20 17. The CMOS imaging array of claim 15 further coming: prising: a first color filter associated with said first pixel; and a first metal interconnect segment associated with said a second color filter associated with said second pixel, first pixel, said first metal interconnect segment having wherein said second color filter is shifted closer to said a second offset position; optical center than said first color filter. 2s wherein said second offset position is derived by propor11. A CMOS imaging array comprising: tionally scaling said first offset position according to a a plurality of pixels arranged in rows and columns, each distance of said first metal interconnect segment above said pixel including a photodetector; said photodetector relative to a distance of said first said plurality of pixels including a first pixel proximate an micro lens element above said photodetector; center said imaging array, and a 30 wherein said first metal interconnect segment is fabricated second pixel proximate a peripheral edge of said array; over said photodetector at said second offset position. a first metal interconnect segment associated with said 18. The CMOS imaging array of claim 17, further comfirst pixel; and prising: a second metal interconnect segment associated with said 3s a second metal interconnect segment associated with said second pixel, wherein said first metal interconnect first pixel, said second metal interconnect segment segment and second metal interconnect segment are having a third offset position; situated in a first metal layer, wherein said second metal wherein said third offset position is derived by proporinterconnect segment is shifted closer to said optical tionally scaling said first offset position according to a center than said first metal interconnect segment so that 40 distance of said second metal interconnect segment said second metal interconnect segment approximately above said photodetector relative to a distance of said aligns with a principal ray angle incident a photodefirst micro lens element above said photodetector. tector of second pixel. 19. The CMOS imaging array of claim 18, wherein said 12. The CMOS imaging array of claim 11, wherein each second metal interconnect segments is fabricated above said of said first and second transistor regions comprises a 4s first metal interconnect segment, said third offset position in respective reset transistor, a respective source-follower closer proximity to an optical center axis of said imaging transistor, and a respective select transistor. array than said second offset position. 13. The CMOS imaging array of claim 11, wherein said 20. The CMOS imaging array of claim 19 further cornphotodetector is a photodiode. prising: 14. The CMOS imaging array of claim 11, wherein said so a via fabricated between said first metal interconnect second metal interconnect segment is shifted along at least segment and said second metal interconnect segment, one of a horizontal or a vertical dimension of said array. said via having a fourth offset position having an 15. A CMOS imaging array of a lens system having a intermediate position between said second offset posiprinciple ray angle, said CMOS imaging array comprising: tion and said third offset position. a plurality of pixels including a first pixel, said first pixel * * * * * having a photodetector;