Goodard v. Google, Inc.

Filing 158

Goodard v. Google, Inc.

Doc. 158 Att. 10

Dockets.Justia.com

fosure Bulletin

Val. 36 No. 02 February 1993

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High Performance Dual Architecture Processor

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RISClClSC Block Diagram

Disclosed is the IBiLI RISC/CISC, a unique processor that exhibits exter- n d y two major arcbitectures. It can appear as:
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A high performance Rcduccd Instruction Set Computcr (RISC) This Native manifestation of the RISC/CISC provides the typical RISC concepts of a User Mode and Privilcgcd Mode.
a 100% compatibtc emulation of an industry standard CIS(: processor provided by a combination of hardware and microcode; the rnicrcicodc uscs the Yative architecture, plus extensions, to emulate thc CISC. The RISC/CISC emulation performs at least as wcl1 as the red industry standard processor.

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T h e CISC manifestation is

The RISC/ClSC proccssor provides thc ability to run softwarc compatible with both aspects of the processor. Thus, it provides a migration path from thc OlSC cnvironrncnt l thc o

High Performance Dual Architecture Processor

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RISC environment. It does so without software emulation of a CISC processor by a RISC proces- sor, a solution with severe performanc:: problems. The important aspects of the RISC/CISC are:
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Full 32-bit architecture

64,32-bit General Purpose Registers (architecturalIy)
Several Special Purpose Registers Pipelined instruction processing Internal instruction and data cache

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Virtual memory support
Demand paging support

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Translator for CISC emulation Internal ROS for CISC emulation

The fipre shows a block diagram of the RISC/CISC. It contains thc foUowing major components:
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The Memory Management Urut contains vanocs registers and control logic for virtual to real address translation and cache management. Cache Unit - The cache unit contains a s r n d on-chip cache, cachc tags for a larger, off-chip cache and cache management logic. CISC Instruction Buffer The CISC Instruction Buffer accepts instruction fetch results, and i the buffer to facilitate CISC instmcn tion decoding.
allows sophisticated manipulation of the information

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CISC Decode and Translate Unit The CISC Dccodc and Translate Unit decodes the data in the CISC Instruction Buffer into complete CISC instructions, and then translates the instruction into:
a Hative instruction the only instruction, or the fust instruction of a sequence required to implement the CISC instruction a ROS address for the rest of an instruction sequence, if any CISC data from various CISC instruction fields, and state information kept by the Translation Unit, both used by subse- quent units to implement CISC instructions

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CISC Instruction Fetch Unit T h e CISC Instruction Fetch Unit is responsible for calculating CISC instruction addrcsses and fetching CISC instructions.

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ROS - The ROS contains instructions for implementing complex CISC instructions and for implementing some microcoded Native instructions.
R iSClCISC Instruction Qucuc - The RISC/CISC Instruction Qucuc accepts instructions from the bus, the cache, ROS and the Translator. It feeds the instructions to the Decode Unit.

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Decode Unit The Decode Unit decodes Hative instructions, addrcssing the registen as required, to feed control and data to the ALU and CISC Effective Address Unit. ALU CThc ALU contains a faed point arithmetic unit, and a sophisticatcd logical unit. These work on bytes, half words and words.

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CISC Effective Address Unit The CISC Effetive Addrcss Unit calculates CISC addtesscs like the CISC, with a b a d , index and displacement, and t!Icn produces a CISC Linear Address (the EA plus a segment base).

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To exhibit the difftrent external architectures, the RISClCrSC runs in several modes that prescrlt
dinerent environments by allowing:
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execution of some (proper) subset of the RlSClCISC instructions access to some (proper) subset of the RISC/CISCregisters. Native U r n Mode provides the Native Uscr environment, for running Native applications Privileged Mode provides the Native Privileged environment (Native User environrncnt plus Privileged extensions), for implementing operating systems that support Native applications

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The modes are:
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* Emulator Mode

- provides an environment for CISC instruction emulation (Native I'rivileged

environment plus Emulator iMode extensions} Native Mode exhibits the following 32-bit RISC processor character- istics: 32, 32-bit General Purpose Registers (GPRs) Reference to stora only through Ioad and store instructions Three operand instructions Intempt handling Storage control

In addition to the "standard" instructions in a RISC processor for arithmetic, shifting and rotating, logical operations and branching, the RISCjCISC h t i v e hlode exhibits some discriminating features:
Powerful rotate and merge instructiors Mukiply and divide instructions Support for branch prefetch optimization Support for branch "scheduling" optimization Emulator Mode extends Native Modc in scved areas; the extensions allow high performance CISC emulation.
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Additional registers The additional registers provide additional hi& speed general purpose registers, CISC-likestatus and storage control regstcrs and various special p u v s e regjstcrs.

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' Additional register addressing capability - 'I'his capabiIity permits addrcssjng of Some spcial P'Tose regsten as Sneral Purpose regsters and indircct addrcssing of gencnl pupose and
some special purposc registers.

Additional operand sizes This capability allows the RJSC/CISC to work cflicientjy with 8and I6-bit operands as well as 32-bit operands.
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* Additional instructions

Emulation requires various new instructions for acccssing nonNative registers, and to implement other functions not possible or that perform poorly using oniy Sative instructions. An example of the latter category is the set of dewriptor based storage access instructions. These fonn addresses for storage accesses like the CISC,with basc and index registers, a displacement and a segment base; Native instructions cannot Hcccss the registers that contain descriptors, and implementation would require many Native instructions to do the same task that a single cycle descriptor bascd instruction can accomplish.

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CISC condition code setting T h i s capability allows the RISC/CISC to set CISC condition codes after various operations.
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Hidden Address Space Access Hidden Address Space Access is avdable in Emulator Mode. Instruction fetches and Native loads and stores access Hidden Address Space; this leaves all of "normal" storage for external programs written with either Native or CISC instructions. Intempt and Exception Processing CISC emulation requires additianal interrupts and exceptions that the RISQCISC must handle. For example, descriptor based storage accesses require segment protection violation exceptions.

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In summary, the RISC/CISC dual architecture processor thus exhibits:
the ability to operate efficiently a a RISC and a s
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CISC

emulation of a CISC via a Native architecture plus extensions,