Elan Microelectronics Corporation v. Apple, Inc.
Filing
214
Declaration of Jennifer Liu in Support of 212 MOTION for Partial Summary Judgment of Infringement of U.S. Patent 5,875,352 [Public Version] MOTION for Partial Summary Judgment of Infringement of U.S. Patent 5,875,352 [Public Version] filed byElan Microelectronics Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3-6 MFN, # 4 Exhibit 7, # 5 Exhibit 8, # 6 Exhibit 9, # 7 Exhibit 10, # 8 Exhibit 11, # 9 Exhibit 12, # 10 Exhibit 13, # 11 Exhibit 14, # 12 Exhibit 15, # 13 Exhibit 16, # 14 Exhibit 17, # 15 Exhibit 18, # 16 Exhibit 19, # 17 Exhibit 20, # 18 Exhibit 21, # 19 Exhibit 22, # 20 Exhibit 23-25 MFN, # 21 Exhibit 26, # 22 Exhibit 27 MFN, # 23 Exhibit 28, # 24 Exhibit 29-33 MFN, # 25 Exhibit 34, # 26 Exhibit 35-37 MFN, # 27 Exhibit 38 Part 1, # 28 Exhibit 38 Part 2, # 29 Exhibit 38 Part 3, # 30 Exhibit 39-45 MFN, # 31 Exhibit 46, # 32 Exhibit 47 MFN, # 33 Exhibit 48)(Related document(s) 212 ) (Liu, Jennifer) (Filed on 5/24/2011)
EXHIBIT 38
PSoC Mixed-Signal
Sheet
Final Data
Array
CY8C2I 234 CY8C2I 334
CYPRESS
CY8C21434 CY8C21534 and CY8C21634
PERFORM
Features
Powerful
M8C
Harvard
Architecture
Processor Speeds
Low
Power
2.4Vto
at High
5.25V
Opereting
On-Chip
Indastrial
Advanced
Voltages
PS0C
PSoC
Type
or
Dael
.OV
Blocks
32-Bit
liwers
SRAM
Serial
85CC
to
Flash
Flexible
50000
Complete
Designer
Additional
Coanters
and
CRC
end
PRS
Connectabla
Complex
UART
to
Peripherals
All
Master
GPIO
by
Combining
Trace
and
and
Precision
Programmable
Internal
2.5%
Internal
Oscillator
24/48
for
Combinations
10
Capability
Clocking
MHz
to
Low
Precision
On-Chip
Detection
Voltage
Circuit
Supervisory
Reference
Voltage
Oscillator
and
Watchdog
Sleep
PSoC
replace
consists
family
low cost
one
PSoC device includes
well
as
allows
the
and
ory
CPU
Flash
digital
configurations
SRAM
of
range
in
and
architecture
application
memory
included
are
This
individual
program
10
configurable
component
peripheral
each
to
components
analog
interconnect
customized
of
of
with
designed
system
blocks
configurable
create
are
programmable
single-chip
requirements
fast
tionally
to
Mixed-Signal Array
devices
MCU-baSed
as programmable
user
the
match
many
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traditional
multiple
with
logic
of
devices
Controller
On-Chip
Overview
Functional
PSoC
The
to
Multi-Master
limers
Sleep
Memory
Integrated
Blocks
of
Resources
Slave
User-Configurable
Slave
128K
Bus
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or
OPIO
kHz
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Emulation
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on
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Speed
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on
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in
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to
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on
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Provide
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Modes
Emulation
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Drain
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mA
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Pin
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Bytes
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Blocks
28 Chennel
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Blocks
DAC
with
Memory
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8K
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Mode Pump
-2 Comparators
Digital
Flexible
MHz
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Switch
Processor
24
Speed
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to
data
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mem
convenient
pinouts
The PSoC
four
architecture
main
Core
and
System
resources
includes
the
allow
four
included
and
analog
up
GPIO
28
is
left
to
four
general
to
PSoC
bus
into
device
Depending
10
the
Digital
global
blocks
purpose
access
provide
the
be combined
analog
of
comprised
Resources
CY8C21x34
Each
to
the
Configurable
resources
and
blocks
The
System
System
system
digital
PSoC package
the
also
the
device
the
on
illustrated
Analog
all
custom
complete
on
as
the
areas
GPIO
global
are
digital
interconnects
The PSoC Core
The
PSoC
instruction
interrupt
nal
March
HIGHLY
29
2006
CONFIDENTIAL
Cypress Semiconductor
ATTORNEYS
Corp
2004-2006
main
Core
set
is
It
controller
oscillator
and
and
sleep
Document
engine
powerful
encompasses
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ILO
38-1
that
SRAM
for
watchdog
internal
2025
timers
low speed
and
rich
an
storage
IMO inter
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CONFIDENTIAL
supports
data
APCY00009757
ATTORNEYS
EYES ONLY
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LOOl 0822
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CPU
ture
called
core
MHz
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to
up
Data
Final
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the
M8C
The
PSoC
Sheet
is
powerful
four
is
with
processor
MIPS
speeds
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8-bit
architec
microprocessor
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to
arrays
12C
increase
an
off
single
by
ported
digital
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number
that
and
various
of
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blocks
buses
from
an
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be
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volt
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in
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to
signal
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conversion
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can
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tions
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references
blocks
alone
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to
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bit
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or
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allow
operations
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straints
of
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resources
teristics
March
of
are
on
29
be
connected
can
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for signal
to
support
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available
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with
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up
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to
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Resource
analog
absolute
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to
three
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rows
in
provided
in
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to
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limited
through
Capacitor
functionality
CT
The
tains
one
performing
for
any pin
logic
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P5cC
from
con
detailed
your designs
the
Type
analog
block
Type
and
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information
provided
in
columns
one
bit
any
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CT Continuous
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blocks
The CY8C21x34
devices
provide
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on
the
one
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Technical
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column
block
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Type
con
Refer
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flows
comparator
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be
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blocks
configurable
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below
listed
Pin-to-pin
slave
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of
analog
tion
with
and
for
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bit
slave
and
requirements
functions
are
flexible
very
application
analog
to
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with
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Analog
allowing
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The Analog System
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listed
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to
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Diagram
combined
or
specific
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blocks
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Digital
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with
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precision
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block
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digital
number
constraints
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of
array
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composed
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comparators
supporting
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SYSTEM
DIGITAL
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The Analog
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controller
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ToAnsiog
slave
provides
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romcore
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blocks
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capability
of
flexibility
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functionality
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additional
provide
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clocks
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for
titled
where
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your
the
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Device
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page
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
APCY00009758
ATTORNEYS
EYES ONLY
APE
LOOl 0823
CY8C21x34
Data
Final
PSoC
Sheet
Additional
Resources
System
System
Resources
some
provide
additional
which
resources
and
detection
merits
both
the
use
in
provide
three
using
The
12C
over
analog
PSoC
digital
module
two wires
pump
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as
the
describing
clock
kHz
routed
be
to
can
be
clocks
and
400
master
and
fre
clock
can
clocks
blocks
Addi
voltage
below
100
dividers
multi-master
provides
Slave
low
customizable
systems
listed
systems
presented
The
applications
and
digital
generated
are
previously
statements
Brief
resource
dividers
for
reset
been
complete
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switch
on
system
clock
Digital
quencies
to
include
power
each
of
of
have
useful
capability
tional
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communication
modes
are
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supported
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cation
of
voltage
On Reset
Power
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Detection
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signal
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advanoed
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the
while
eliminates
circuit
can
interrupts
levels
need
system
for
supervise
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internal
ence
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integrated
switch
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boost
cost
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connected
bus
and
log
input
to the
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ously
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to the
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surement
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individually
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analog
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or
in
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pin
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path
to
bring
com
ana
with
additional
analog
on
enables
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Port
available
pins
as
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mux
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data
sheet
device
is
mea
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PSoCPart
table
groups
highlighted
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lists
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or
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and
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and
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system
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Bytes
Limited
March
HIGHLY
29
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
Rev
analog
funotionality
3J
EYES ONLY
CONFIDENTIAL
APCY00009759
ATTORNEYS
EYES ONLY
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LOOl 0824
CY8C21x34
Data
Final
PSoC
Sheet
Getting Started
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CONFIDENTIAL
APCY0000976O
ATTORNEYS
EYES ONLY
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LOOl 0825
CY8C21x34
Data
Final
PS0C
Sheet
PSoC
Designer Software
Device
Editor
The
device
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editor
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PSoC
different
contains
and
for
source
creates
configuration
Designer
PS0C
time
and
The framework
components
operating
tables
initialization
configurations
selected
between
switch
power-on
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the
than
up
block
application
more
run
sets
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provide
also
allow
data
CPU
write
time
run
debugger
PS0C
and
read
write
the
view
internal
an
hardware
provides
to test
designer
providing
and
read
multiple
registers
subsystem
the
commands
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points
uration
Debugger
allowing
while
system
physical
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also
and
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emulation
in-circuit
program
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Overview
or
addressing
with
other
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can
be
link
compiled
modules
software
code
auto
libraries
to
get
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in
absolute
addressing
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that
supports
never
worked
allows
you
Compiler
the
PS0C
in
the
create
to
language
family
of
before
language
complete
compiler
devices
Even
the
if
available
quickly
provides
all
PSoC
the
have
you
product
for
programs
is
family
devices
The embedded
of
tailored
embedded
keypad
and
March
29
HIGHLY
to
compiler
optimizing
the
PSoC
architecture
libraries providing
display
support
port
and
and
It
the
extended
math
features
standard
functionality
Document
ATTORNEYS
with
complete
bus operations
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Data
Final
PSoC
Sheet
Overview
Designing with User Modules
The development
traditional
of
and
analog
unique
change
to
Each
has
block
ware
well
as
ether
lowering
PSoC
cycles
have
to
adapt
the
to
the
10
hard
the
lowers
meet
to
and
function
its
and
you
the
functions
buses
substantially
part
costs
inventory
Blocks
determine
permit
This
different
architecture
specification
user-selectable
multiplexers
software
select
of
that
registers
blocks
the
as
to
having
by
variety
development
Iterative
pins
wide
PSoC
called
that
configurable
managing
in
from
differs
The
the
give
and
resources
several
to
connectivity
blocks
dividends
pays
implement
device
microprocessor
development
configurable
ability
of
that
during
These
function
hardware
digital
flexibility
P5cC
for the
process
fixed
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design
final
requirements
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the
development
pre-built
hardware
pre-tested
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peripheral
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of
bits
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resolution
establish
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provide
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application
level
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optional
time
API
to
you
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at
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directly
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inter
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linker
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last
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runs
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developing
Application
code
step
for the
This
project
the
device
module
March
HIGHLY
to
API
29
generate
your
source
specification
and
that
causes
automatically
provides
the
PSoC
configures
high-level
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HEX
values
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buffer
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define
address
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down
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features
allows
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you
inside
place
Emulator
to
is
all
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addition
takes
programming
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capabilities
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displayed
message
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for
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subsystem
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image
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for both
patterns
compiler and
the
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speed
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system
run
HEX
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provides
code
capabilities
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costing
to
in
step
the
search
Manager
offending
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at
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builds
and
loads
test
to the
directly
editor
features
compiler and
window
gener
code
source
edit
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allows
all
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grep-style
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advanced
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map them
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user modules
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by
starts
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specifications
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write
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ated
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using
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directly
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each
modules
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for
permit
User
interface
particular
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one
your development
are documented
functions
explain
provide
to
parameters
respond
provides
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viewed
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and
control
parameters
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cycle
that
settings
provides
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that
cut
sections
provides
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duty
programming
to
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time
and
to
software
functions
register
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user module
width
pulse
peripherals
filter
analog
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digital
DACs Tim
ADCs
common
configuration
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more
or
con
basic
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precise
its
and
library
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the
example
one
configures
and
digital
Module
User
not-so
function
tailor
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other
establishes
selected
you
application
and
implementing
analog
in
such
peripherals
UARTs
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as
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ule
common
50
Counters
standard
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User
called
and
selecting
of
library
functions
come
Inte
Designer
provides
peripheral
and
simple
varieties
signal
IDE
make
modules
PSoC
the
process
Environment
Development
grated
and
Debugger
complex
data
bus
signals
functions
Document
2006
CONFIDENTIAL
ATTORNEYS
No
38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
APCY00009762
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Data
Final
PSoC
Sheet
Document Conventions
For an
in
table
following
the
lists
that
acronyms
are
used
in
this
doc
ence
ument
and
discussion
depth
obtain
device
The
of Contents
Table
Acronyms Used
Overview
PSoC
the
Manual
on
more
is
the
into
organized
Teohnioal
This
http/lwww.cypress.com
encompasses and
PSoC
on your
information
Mixed-Signal Array
Refer
document
and
chapters
following
sections
Acronym
Description
AC
aiternating
ADC
analog-to-digital
API
application
cu
centrul
01
continuous
DAC
digitni-to-unulog
current
Pin Information
converter
1.1
interfucu
progrumming
1.1.1
direct
ECO
usturnui
EEPROM
uiectricully
Pinout
Part
Pinout
10
32-PinPartPinout
11
1.1.5
current
Part
28-Pin
1.1.4
converter
20-Pin
1.1.3
time
16-PinPartPinout
1.1.2
unit
processing
DC
Pinouts
56-Pin
12
Part
Pinout
oscilietor
crystal
Reference
Register
erasable
programmable
read-only
memory
14
2.1
FSR
scale
full
GPI0
general
GUI
graphicui
Register
Mapping
Electrical
interface
ICE
in-circuit
Absolute
3.2
oc
ILD
internal
low
IMO
internal
main
oscillator
speed
DC
DC
DC
DC
3.3.1
oscillator
input/output
3.3.3
IPOR
LSb
on
power
imprecise
3.3.4
bit
least-significant
LVD
low
M5b
progrum
PLL
phase-locked
POR
power
3.3.6
bit
most-significant
3.3.7
counter
3.4
PPDR
precision
P5o0
Progrummuble
PWIV1
pulse
AC
AC
3.4.2
on
power
AC
AC
AC
AC
3.4.3
reset
3.4.4
System-on-Chiptm
3.4.5
modulator
width
3.4.6
50
switched
SLiMO
siowlMO
capacitor
AC
AC
3.4.7
3.4.8
SMP
switch
SRAM
stutic
mode
chip-Level
General
Switch
rundom
uccess
section
used
to
Table
measure
3-1
is
on
located
in
the
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17
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represented
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10
24
Amplifier
Mux Bus
Specifications
...
Specifications
..
27
Specifications
27
Specifications
Clock
26
27
29
Specifications
30
Specifications
31
32
36
Impedances
Peak Temperature
36
Information
Ordering
and
32
Code
37
Definitions
Information
Service
Revision
Copyrights and
37
38
38
History
Code
39
Protection
upper
14h
example
for
or
represented
by
Ox
Binary
numbers
have
an
OlOlOlOOb
or
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convention
with
also
or
be
Ox
are
OlOOOOllb
decimal
Document
2006
CONFIDENTIAL
23
Specifications
6.2
are
appended
Hexidecimal
prefix
March
numbers
an
with
22
Dimensions
Thermal
5.1
Numeric Naming
case
22
Specifications
Programming
6.1
Hexidecimal
21
Specifications
24
Purpose
Block
Digital
19
20
Specifications
Characteristics
Analog
Packaging
Specifica
PSoC devices
the
...
Information
Packaging
memory
Ordering
tions
Amplifier
Operational
4.3
table
measure
18
Specifications
pump
Measure
of
IC
Mode Pump
General
4.2
units
Purpose
Chip-Level
4.1
Units of
18
Specifications
Operational
Electrical
3.4.1
ioop
reset
on
AC
18
characteristics
DC Analog Mux Bus Specifications
DC POR and LVD Specifications
DC Programming Specifications
3.3.5
detect
noltage
PC
reset
18
Ratings
Temperature
Electrical
3.3.2
10
17
Maximum
Operating
body
14
Specifications
3.1
emulator
human
model
3.3
HBM
14
Tables
10
purpose
user
Register
2.2
range
conventions
ATTORNEYS
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38-1
2025
Rev
EYES ONLY
CONFIDENTIAL
APCY00009763
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