Apple Inc. v. Samsung Electronics Co. Ltd. et al

Filing 661

EXHIBITS re #660 Administrative Motion to File Under Seal Apple Inc.'s Notice of Motion and Motion for Partial Summary Judgment Exhibits to Mueller Declaration ISO Apple's Motion for Partial Summary Judgment [660-9] filed byApple Inc.(a California corporation). (Attachments: #1 Exhibit Mueller Decl Exhibit 2, #2 Exhibit Mueller Decl Exhibit 3, #3 Exhibit Mueller Decl Exhibit 4, #4 Exhibit Mueller Decl Exhibit 5, #5 Exhibit Mueller Decl Exhibit 6, #6 Exhibit Mueller Decl Exhibit 7, #7 Exhibit Mueller Decl Exhibit 8, #8 Exhibit Mueller Decl Exhibit 9, #9 Exhibit Mueller Decl Exhibit 10, #10 Exhibit Mueller Decl Exhibit 11, #11 Exhibit Mueller Decl Exhibit 12, #12 Exhibit Mueller Decl Exhibit 13, #13 Exhibit Mueller Decl Exhibit 14, #14 Exhibit Mueller Decl Exhibit 15, #15 Exhibit Mueller Decl Exhibit 16, #16 Exhibit Mueller Decl Exhibit 17, #17 Exhibit Mueller Decl Exhibit 18, #18 Exhibit Mueller Decl Exhibit 19, #19 Exhibit Mueller Decl Exhibit 20, #20 Exhibit Mueller Decl Exhibit 21, #21 Exhibit Mueller Decl Exhibit 22, #22 Exhibit Mueller Decl Exhibit 23, #23 Exhibit Mueller Decl Exhibit 24)(Related document(s) #660 ) (Selwyn, Mark) (Filed on 1/25/2012)

Mueller Exhibit 14

3GPP_TSG_RAN_WG1 Archives -- August 1999 (#334)

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Thu, 26 Aug 1999 01:08:58 KST
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"3GPP TSG RAN WGI: TSG RAN Working Group 1"
<[log in To unmask]>
"(Changsoo PARK)" <[log in to unmask]>
From:
Subject:
AH10, R1-99b59 multiple scrambling code
CorrLments: cc: [log in to unmask]
Content-Type: multipart/mixed;

Dear all,
Please find the attached "Text proposal regarding
multiple scrambling codes" from SAMSUNG.
R1-99b59.zip(R1-99b59.pdf) :Text proposal regarding
Hultiple Scrambling Codes
Source : SAMSUNG
Best regards,
Jaeyoel KIM.

R1-99b59. PDF [application/octet-stream]

R1-99b59.zip [application/zip]

Back to: Top of message I Previous page I Main 3GPP TSG RAN WG1 page

http://~ist.etsi.~rg/scripts/wa.exe?A2=ind99~8&L=3GPP-TSG-RAN-WG~&P=R3~3~~8&I... 8/1/2011
!~.Pv,NDC-WI-I-A 0000012262

TSG-RAN Working Group 1 meeting #7

TSGR1#7(99)99b59

Hanover, Germany
August 30 - September 3, 1999

Agenda item:
Source:
Title:
Document for:

Samsung
Decision

Abstract
Samsung proposed about the multiple scrambling code generation in [1]. This text proposal
describe the text change of the multiple scrambling code section to the contribution.

Proposed Text

5.2.2 Scrambling code
There are a total 512"~5-12!6= 2-62-,-144~6,.!.92 scrambling codes, numbered 0 ...262-;44%.6J9!. The
scrambling codes are divided into 512 sets each of a primary scrambling code and
secondary scrambling codes.
The primary scrambling codes consist of scrambling codes
The i:th set of secondary scrambling codes consists of scrambling codes ~
k=-1---.-,5-1-11..6.*.j..+.k,...w...h...e.r..e..k.=...1....,,..1..5..
There is a one-to-one mapping between each primary scrambling code and 511 secondary
scrambling codes in a set such that i:th primary scrambling code corresponds to i:th set of
scrambling codes.
The set of primary scrambling codes is further divided into 32 scrambling code groups, each
consisting of 16 primary scrambling codes. The j:th scrambling code group consists of
scrambling codes
Each cell is allocated one and only one primary scrambling code. The primary CCPCH is always
transmitted using the primary scrambling code. The other downlink physical channels can be

APLNDC-WH-A 0000012258

transmitted with either the primary scrambling code or a secondary scrambling code from the
set associated with the primary scrambling code of the cell.

<Editor’s note: it is not standardised how many scrambling codes a UE must decode in
parallel. >

The scrambling code sequences are constructed by combining two real sequences into a
complex sequence. Each of the two real sequences are constructed as the position wise
modulo 2 sum of [40960 chip segments of] two binary m-sequences generated by means of two
generator polynomials of degree 18. The resulting sequences thus constitute segments of a set
of Gold sequences. The scrambling codes are repeated for every 10 ms radio frame. Let x and
y be the two sequences respectively. The x sequence is constructed using the primitive (over
GF(2)) polynomial I+XT+X~8. The y sequence is constructed using the polynomial I+XS+XT+

X~o+x~8.
<Editor’s note: [] is due to the fact that only 4.096Mcps is a working assumptions. 1.024, 8.192,
and 16.384Mcps are ffs.>
" ....
L-et-~l.~o___
o
I~eiag-the-~eaet-signffiear~t-Mt= The x sequence depends on the chosen scrambling code number
n and is denoted xn, in the sequel. Furthermore, let xn(i) and y(i) denote the i:th symbol of the
sequence x~ and y, respectively
The m-sequences x~ and y are constructed as:
Initial conditions:
x~(O)=no, x~(1)= nl .... =x~(16)= n~, x~(17)=
y(O) =y(1) =... =y(16) = y(17) = 1
Recursive definition of subsequent symbols:
x~(i+18) =x~(i+ 7) + x~(i) modulo 2, i=O, ....2~-20,
y(i+18) = y(i+lO)+y(i+7)+y(i+5)+y(i) modulo 2, i=O, ....2~e-20.
The n:th Gold code sequence zn is then defined as
z~(i) = x~(i) + y(i) modulo 2, i=O, .... 21~-2.
Xo..i~..~D.~t~u~t.~.~!.with Zo.(~2)..~..~o (~).~.,,,..~<~ (,.~.(~).~.(?..~(.!..7:).~.!...~..iD.i~i~.!..~.r2~!it[~.~....
These binary code words are converted to real valued sequences by the transformation ’g ->
’ +1’ ,’ 1’ ->’-1’.
Finally, the n:th complex scrambling code sequence C, .... is defined as (the lowest index
~
corresponding to the chip scrambled first in each radio frame): (see Table 1 for definition of N

APLNDC-WH-A 0000012259

and M)
b(i) = Z’n(i) +jZ’n(i+M), i=0,1,...,N-1.
<Editor’s note: the values 40960 is based on an assumption of a chip rate of 4. 096 Mcps. >
Note that the pattern from phase 0 up to the phase of 10 msec is repeated.
MSB

/SB

shift register 1 (18 bit)

shift register 2 (18 bit)

L17 ....
10

7 ....

~]

5

0

ExOR

Figure 1. Configuration of downlink scrambling code generator
<Edito[’s note: a replacement figure for the above is to be prepared showing both I & Q
generation.>
chip rate
(Mcps)

IQ Offset

N
[1.024]
4.096
[8.192]
[16.384]

Period

M

[10240]
40960
[81920]
[163840]

[131072]
131072
[131072]
[131072]

Range of phase (chip)

~rin-phase
component
0 -N-1

~r

quadrature
component

M - N+M-1

Table 1. Correspondence between chip rate and downlink scrambling code phase
range

APLNDC-WH-A 0000012260

Reference
[1]

3GPP TSGRI#6 (99)924,’ Multiple scrambling code’, Source: Samsung

[2]

3GPP TSGRI#7 (99)a86,’ TS 25.213 V2.0.1 (1999-08) Spreading and modulation(FDD)’

APLNDC-WH-A 0000012261