Bose Corporation v. Beats Electronics LLC et al

Filing 1

COMPLAINT filed with Jury Demand - against Beats Electronics International Limited, Beats Electronics LLC - Magistrate Consent Notice to Pltf. ( Filing fee $ 400, receipt number 0311-1560024.) - filed by Bose Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3, # 4 Exhibit 4, # 5 Exhibit 5, # 6 Exhibit 6, # 7 Exhibit 7, # 8 Exhibit 8, # 9 Exhibit 9, # 10 Exhibit 10, # 11 Civil Cover Sheet)(rwc)

Exhibit 2

u 7484958

t!Q)Mffi,'!lQ)WHQMrl!.HrE-Sj£ ~:g.JESiEN{!l~ SBM.m, ~OMIE!;j
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
July 01, 2014
THIS IS TO CERTIFY THAT ANNEXED HERETO IS A TRUE COPY FROM
THE RECORDS OF THIS OFFICE OF:

U.S. PATENT: 6,717,537
ISSUE DATE: April 06,2004

By Authority of the
Under Secretary of Commerce for Intellectual Property
and Director of the United States Patent and Trademark Office

~- ~N-Yi(_Q_
T. LAWRENCE
Certifying Officer

111111

1111111111111111111111111111111111111111111111111111111111111
US006717537Bl

United States Patent

(10)

Fang et al.

(12)

(45)

(54)

METHOD AND APPARATUS FOR
MINIMIZING lATENCY IN DIGITAL
SIGNAL PROCESSING SYSTEMS

(75)

Inventors: Xiaoling Fang, Irvine, CA (US); Keith
L. Davis, Salt Lake City, UT (US);
Martin R. Johnson, Draper, UT (US)

(73)

Assignee: Sonic Innovations, Inc., Salt Lake City,
UT(US)

( *)

Notice:

(21)

Appl. No.: 10/179,930

(22)

Filed:

Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.

Jun.24,2002
Related U.S. Application Data

(60)

Provisional application No. 60/301,308, filed on Jun. 26,
2001.

(51)
(52)
(58)

Int. Cl.7 ................................................. H03M 3/00
U.S. Cl. .......................................... 341/143; 381/74
Field of Search ................................. 341/143, 155,
341/144; 381/94, 55, 92

References Cited

(56)

U.S. PATENT DOCUMENTS
4,025,721
4,122,303
4,185,168
4,249,128
4,309,570
4,423,442
4,432,299
4,455,675
4,473,906
4,494,074
4,589,133
4,603,429
4,622,660
4,644,581
4,654,871
4,658,932

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

5/1977
10/1978
1/1980
2/1981
1/1982
12/1983
2/1984
6/1984
9/1984
1/1985
5/1986
7/1986
11/1986
2/1987
3/1987
4/1987

Graupe et al. .............. 179/1 P
Chaplin et al. ............. 179/1 P
Graupe et al. .............. 179/1 P
Karbowski .................. 324/329
Carver ...................... 179/1 G
Bitting et al. . ................ 360/68
Smith ..................... 116/137 R
Bose et al. ................... 381/74
Wamaka et al. .............. 381/71
Bose .......................... 330/109
Swinbanks .... ... ... ... ... .. . 381171
Carver .... .. ... ... ... ... ... .. ... 381/1
Cowans et al. ............. 369/134
Sapiejewski ................. 381/74
Chaplin et al. ............... 381/72
Billingsley .. .. ...... ... ... .. 181/175

Patent No.:
US 6, 717,537 Bl
Date of Patent:
Apr. 6, 2004

4,731,850 A
4,736,751 A

3/1988 Levitt et al ................ 381/68.2
4/1988 Gevins et al. .............. 128!732

(List continued on next page.)
FOREIGN PATENT DOCUMENTS

wo
wo

wo 94/11953
wo 98/43567

5/1994
8/1998

........... A61F/11/06

OTHER PUBLICATIONS
Saunders, et al., "A Hybrid Structural Control Approach for
Narrow-Band and Impulsive Disturbance Rejection", 1996,
Noise Control Eng. J., vol. 44, No. 1, pp 11-21.
PCT International Search Report, PCT/US 02/20223, International filing date Jun. 25·, 2002, date Search Report mailed
Apr. 25, 2003.

Primary Examiner-Jean Bruner Jean Glaude
Assistant Examiner-Joseph Lauture
(74) Attorney, Agent, or Firm-Thelen Reid & Priest LLP;
Steven J. Robbins
(57)

ABSTRACT

A method and an apparatus for minimizing latency in digital
signal processing paths. One example is an active noise
cancellation device. The system includes a digital closed
feedback loop having a forward path and a feedback path.
The forward path includes a compensation filter, a digitalto-analog converter, and an output transducer. The feedback
path includes an input transducer, a feedback delta-sigma
modulator, and a feedback sampling-rate converter. An input
signal is processed in one of several ways into a processed
digital input signal having a preselected intermediate sampling rate. Through the feedback path, an analog output
signal is processed into a digital feedback signal having
substantially the same preselected intermediate sampling
rate. The processed digital input signal and the digital
feedback signal are combined and processed through the
forward path to produce an anti disturbance signal that is
combined with a disturbance signal to form the analog
output signal.

19 Claims, 6 Drawing Sheets

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Input

66

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US 6,717,537 Bl
Page 2

U.S. PATENT DOCUMENTS
4,783,818
4,827,280
4,833,719
4,868,870
4,878,188
4,879,749
4,905,090
4,922,542
4,939,600
4,953,217
4,985,925
5,001,763
5,083;538
5,105,377
5,107,379
5,109,410
5,159,639
5,164,984
5,177,755
5,181,252
5,182,774
5,222,189
5,251,263
5,259,033
5,267,321
5,276,739
5,287,398
5,361,303
5,363,444
5,381,485
5,402,497
5,452,361

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

11/1988
5/1989
5/1989
9/1989
10/1989
11/1989
2/1990
5/1990
7/1990
8/1990
1/1991
3/1991
1/1992
4/1992
4/1992
4/1992
10/1992
11/1992
1/1993
1/1993
1/1993
6/1993
10/1993
11/1993
11/1993
1/1994
2/1994
11/1994
11/1994
1/1995
3/1995
9/1995

Graupe et a!. ................ 381/71
Stamer et a!. ............... 346/1.1
Carme et a!. ................. 381/72
Schrader .. .. ... ... ... ... ... .. . 381/96
Ziegler, Jr. ............. 364/724.01
Levitt et a!. ............... 381/68.4
Miyake ...................... 358/296
Sapiejewski ................ 381/187
Desai et a!. ............. 360/78.04
Twiney et a!. ................ 381/72
Langberg et a!. ............. 381/72
Moseley .. ..... ... ... ...... .. . 381/71
Hubbell ... ... ..... ... .. .. 123!198 E
Ziegler, Jr. ............. 364/724.01
Huber .. ... .. ...... ... ...... .. . 360/46
Suhami et a!. .............. 379/430
Shannon et a!. ........... 381/68.5
Suhami eta!. .............. 379/444
Johnson .............. ......... 372/38
Sapiejewski et a!. ....... 381/187
Bourk .. ... . .. .. ... ... ... .. ... . 381/71
Fielder . ... .. ...... ... . .. ... .. ... 395/2
Andrea eta!. ................ 381/71
Goodings et a!. ............. 381/68
Langberg ..................... 381/72
Krokstad et a!. .......... 381/68.2
Briault ......... ... ............ 379/38
Eatwell ....................... 381/71
Norris ........................ 379/430
Elliott .. . . .... .. ... ... ... ... .. . 381/71
Nishimoto et a!. ........... 381/95
Jones ... . ...................... 381/71

5,481,615
5,497,426
5,523,715
5,539,831
5,600,729
5,602,928
5,604,813
5,610,987
5,638,022
5,727,566
5,793,875
5,815,582
5,848,169
5,850,453
5,937,070
5,965,850
5,990,818
5,999,631
6,072,884
6,078,672
6,118,878
6,160,893
6,163,610
6,173,063
6,181,801
6,208,279
6,219,427
6,278,786
6,339,647
6,373,953
6,396,930

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B1
B1
B1
B1
B1
B1
B1
B1

*

*
*

1/1996
3/1996
6/1996
7/1996
2/1997
2/1997
2/1997
3/1997
6/1997
3/1998
8/1998
9/1998
12/1998
12/1998
8/1999
10/1999
11/1999
12/1999
6/2000
6/2000
9/2000
12/2000
12/2000
1/2001
1/2001
3/2001
4/2001
8/2001
1/2002
4/2002
5/2002

* cited by examiner

Copy provided by USPTO from the PIRS Image Database on 06/27/2014

Eatwell et a!. ... ... .......... 381/71
Jay ............................. 381/67
Schrader .. ... ... ... .. .. . .... .. 330/10
Harley . ... ... ... ... .. .. ....... 381/67
Darlington et a!. ........... 381/71
Eriksson et a!. . ............. 381/71
Evans et a!. .. ... . .. . ... ... . .. 381/71
Harley . ... ... ... ... .. .. . ...... 381/67
Eatwell ...................... 327/551
Leight
128/857
Lehr et a!. ................. 381/68.1
Claybaugh et a!. ........ 381/71.6
Clark, Jr. et a!. ........ 381/71.13
Klayman et a!. ... ... .. ... ... 381/1
Todter et a!. . ... ... ... .. .. 381/71.6
Fraser .. ... ... ... ... .. ... ... .. 181/129
McGrath .................... 341/141
Porayath et a!. .............. 381/93
Kates ......................... 381/318
Saunders et a!. ... ... .. .. 381/71.6
Jones .......................... 381/72
Saunders et a!. ... ... .. .. 381/71.6
Bartlett et a!. .............. 379/433
Melanson ................... 381/318
Puthuff et a!. ... ... ... .. ... 381/380
Oprescu ..................... 341/143
Kates et a!. ................ 381/318
Mcintosh ................... 381/71.6
Andersen eta!. ........... 381/312
00 0 0 0 0 0 0 0 0 0 0 0 0 00 • • 0 0 0 0 0 0

Flaks ························ 381/94.7
Vaudrey et a!. .. .. .... .. ... .. 381/60

U.S. Patent

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1

2

METHODANDAPPARATUSFOR
MINIMIZING LATENCY IN DIGITAL
SIGNAL PROCESSING SYSTEMS

a gain as possible in the overall loop within a predetermined
frequency range while maintaining the system stability. The
forward path of the system 10 includes a compressor 12, a
compensator 14, a power amplifier 16, and a receiver 18. For
example, the receiver 18 could be any output transducer
including a loudspeaker. The feedback path of the system 10
includes a microphone 20 as an input transducer and a
microphone preamplifier 22. The Vin signal and the feedback path signal are combined in a first summation node 24.
The forward path signal and the Noise signal are combined
in a second summation node 26.
Turning now to FIG. 2, a block diagram of a second prior
art feedback active noise cancellation system 30 as disclosed
in U.S. Pat. No. 5,182,774 is shown. One will note that the
system 30 has similarities with the system 10 of FIG. 1
except that the forward path includes a high-pass filter 32, a
low-pass filter 34, and a mid-range filter 36 in combination
with the receiver 18. Further, the feedback path adds a
high-pass filter 38 to the microphone 20 and the microphone
preamplifier 22.
Turning now to FIG. 3, a block diagram of a third prior
art feedback active noise cancellation system 40 as disclosed
in U.S. Pat. No. 5,604,813 is shown. In this case, a boost
circuit 42 has been added outside of the closed loop, that is,
before the first summation node 24, to equalize the desired
signal. The feedback path of the system 40 includes the
microphone 20, a plurality of band-pass filters 44, and a
low-pass filter 46.
While widely used in the art, the conventional analog
approach for reducing noise in a system is not without its
problems. ANC systems are theoretically able to null the
noise by generating a phase-inverted antinoise signal,
however, as a practical concern, the various components of
the system such as the input and output transducers will
introduce certain undesirable delays. These delays may
adversely affect the frequency range over which noise can be
cancelled, the degree to which noise can be cancelled, and
the stability of the noise-cancellation system. It is therefore
desirable to be able to minimize the associated delays in the
circuit. Likewise, it is also desirable to be able to adjust the
circuit to compensate for component variation and manufacturing tolerances and for usage conditions to maximize
the noise-cancellation frequency range and noisecancellation ratio. Such adjustability is difficult to achieve
using analog techniques. Another desirable function that can
prove difficult in the analog domain is the equalization of the
signal for frequency-dependent attenuation caused by subsequent processing functions.

RELATED US PATENT APPLICATION DATA

5

The present non-provisional patent application claims the
benefit of U. S. provisional patent application Ser. No.
60/301,308, filed on Jun. 26, 2001.
FIELD OF TilE INVENTION

10

The present invention is generally directed to digital
signal processing. More specifically, the present invention is
directed to minimization of system latency in signal pro15
cessing paths including digital control loops.
BACKGROUND OF TilE INVENTION

The use of digital signal processing for communication
systems, such as cable and satellite transmission systems, 20
has long been known in the art. Presently, these digital
communications are in widespread use in establishing links
between nearly all types of communication devices in which
two or more such devices are in need of high quality
communication with one another. As a result, these systems
25
allow for the utilization of sophisticated communication
applications in which each member can communicate with
other members and other devices. Such digital signal processing devices have been developed in a the intended use.
One form of digital signal processing device in use today in
communication systems is an active noise cancellation 30
(ANC) device. The ANC-device is most often used in a
sound environment where there are one or more disturbance
or noise signals that tend to obscure the desired or target
signal. The conventional ANC device generally includes a 3
feedback circuit which uses an input transducer such as a 5
microphone to detect ambient noise and an output transducer
such as a loudspeaker or receiver to both generate an
antinoise signal to cancel the ambient noise and to deliver
the desired signal. The particular circuit elements vary from
40
implementation to implementation.
Currently,ANC is achieved in analog form by introducing
a canceling antinoise signal. The actual noise is detected
through one or more microphones. An antinoise signal of
equal amplitude and opposite phase is generated and com- 45
bined with the actual noise. If done properly, this should
result in cancellation of both noises. The amount of noise
cancellation depends upon the accuracy of the amplitude and
BRIEF DESCRIPTION OF TilE INVENTION
phase of the generated antinoise signal. ANC can be an
effective method of attenuating low-frequency noise which 50
A method and an apparatus for minimizing latency in
can prove to be very difficult and expensive to control using
digital signal processing paths is disclosed. One example is
passive noise control techniques.
an active noise cancellation device. The system includes a
digital closed feedback loop having a forward path and a
Turning first to FIG. 1, a block diagram of a first prior art
feedback path. The forward path includes a compensation
feedback active noise cancellation system 10 as disclosed in
U.S. Pat. No. 4,455,675 and 4,644,581 is shown. The system ss filter, a digital-to-analog converter, and an output transducer.
The feedback path includes an input transducer, a feedback
10 has as input a desired signal and a Noise signal and
delta-sigma modulator, and a feedback sampling-rate congenerates an output signal. For discussion purposes, it will
verter. An input signal is processed in one of several ways
be assumed that the desired signal is an input voice (Vin)
into a processed digital input signal having a preselected ·
signal and that the output signal is an output voice (Vout)
signal. The Noise signal is considered to be any disturbance 60 intermediate sampling rate. Through the feedback path, an
analog output signal is processed into a digital feedback
signal in the sound environment other than the desired
signal having substantially the same preselected intermedisignal. The Vout signal is a combination of the Vin signal,
ate sampling rate. The processed digital input signal and the
the Noise signal, and an antinoise signal generated by the
digital feedback signal are combined and processed through
system 10. As noted above, in theory the antinoise signal
exactly cancels the Noise signal leaving only the Vin signal 65 the forward path to produce an anti disturbance signal that
is combined with a disturbance signal to form the analog
without attenuation as the Vout signal. In fact, this is not
output signal.
always the result. The system 10 attempts to achieve as high

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US 6,717,537 Bl

3

4

BRIEF DESCRIPTION OF TilE DRAWINGS

50 according to the present invention is shown. Outside of
the closed loop, the system 50 includes an input processor
52. The details of the input processor 52 will be discussed in
more detail below. In general, the input processor 52 takes
an INPUT signal, either analog or digital, and produces a
processed digital input signal having an intermediate (I)
sampling rate equal to I times Fs where I has a value greater
than one and Fs is the sampling rate which is twice the
Nyquist rate (Finax) of the INPUT signal. The forward path
includes a compensation filter 54, a digital-to-analog converter (DAC) 56, and an output transducer 58. The result of
the forward path is an analog forward path signal. The
feedback path includes an input transducer 60, a feedback
delta-sigma modulator 62, and a feedback sampling-rate
converter 64. The output of the feedback delta-sigma modulator 62 has a sampling rate equal to N times Fs where N is
greater than one. N is also greater than I. However, since IPs
is the desired sampling rate, the output NFs needs to be
down-sampled to the lower rate by the feedback samplingrate converter 64. The result is a digital feedback signal that
has the same sampling rate as the processed digital input
signal. The intermediate sampling rate is chosen to produce
an acceptably low delay in the feedback path. The tradeoff
is increased circuit complexity and cost. The digital feedback signal is subtracted from the processed digital input
signal at a first summation node 66. It is also possible to
combine the feedback delta-sigma modulator 62 and the
feedback sampling-rate converter 64 into a feedback analogto-digital converter (ADC) with an output rate of IPs. The
analog forward path signal is combined with an analog
DISTURBANCE signal in a second summation node 68.
The output of the second summation node 68 is the input of
the feedback path and the output of the system 50 and is an
analog acoustic output signal (Vout).
Turning now to FIG. 5, a block diagram of another
exemplary embodiment of a feedback active noise cancellation system 70 according to the present invention is shown.
The system 70 is essentially the same as the system 50 of
FIG. 4 except that the compensation filter 54 has been
moved from the forward path to the feedback path as shown.
A whole array of block diagram manipulations are possible
and well known to those of ordinary skill in the art. Any
embodiment that can be the result of such manipulations is
considered to be within the scope of the present invention as
exemplified in FIGS. 4 and 5. Further such embodiments
will not be presented in detail for the sake of brevity.
Turning now to FIG. 6, a block diagram of an exemplary
embodiment of the input processor 52 of FIGS. 4 and 5
according to the present invention is shown. Recall from
above that the input processor 52 takes an INPUT signal,
either analog or digital, and produces the processed digital
input signal having the intermediate sampling rate (IPs). The
elements of the input processor 52 will depend in part on the
characteristics of the INPUT signal. Various combinations of
elements will be outlined below as examples, but other
combinations may be possible depending on design choice
and circumstances. The example elements shown assume
that the INPUT signal is an analog signal (Xin). The
elements of the input processor may include an input deltasigma modulator 72, a first input sampling-rate converter 74,
an equalizer 76, and a second input sampling-rate converter
78. The output of the input delta-sigma modulator 72 has a
sampling rate equal to M times Fs where M is greater than
one and greater than 1. This output is then down-sampled by
the first sampling-rate converter 74 to a rate equal to K times
Fs. K is greater than or equal to one and less than I.
Consequently, the output of the first sampling-rate converter

The accompanying drawings, which are incorporated into
and constitute a part of this specification, illustrate one or
more embodiments of the present invention and, together
with the detailed description, serve to explain the principles
and implementations of the invention.
In the drawings:
FIG. 1 is a block diagram of a first prior art feedback
active noise cancellation system;
FIG. 2 is a block-diagram of a second prior art feedback
active noise cancellation system;
FIG. 3 is a block diagram of a third prior art feedback
active noise cancellation system;
FIG. 4 is a block diagram of an exemplary embodiment of
a feedback active noise cancellation system according to the
present invention;
FIG. 5 is a block diagram of another exemplary embodiment of a feedback active noise cancellation system according to the present invention; and
FIG. 6 is a block diagram of an exemplary embodiment of
the input processor of FIGS. 4 and 5 according to the present
invention.

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DETAILED DESCRIPTION OF TilE
INVENTION
Various exemplary embodiments of the present invention
are described herein in the context of a method and an
apparatus for minimizing latency in digital signal processing
paths. Those of ordinary skill in the art will realize that the
following detailed description of the present invention is
illustrative only and is not intended to be in any way
limiting. Other embodiments of the present invention will
readily suggest themselves to such skilled persons having
the benefit of this disclosure. Reference will now be made in
detail to exemplary implementations of the present invention
as illustrated in the accompanying drawings. The same
reference indicators will be used throughout the drawings
and the following detailed descriptions to refer to the same
or like parts.
In the interest of clarity, not all of the routine features of
the exemplary implementations described herein are shown
and described. It will of course, be appreciated that in the
development of any such actual implementation, numerous
implementation-specific decisions must be made in order to
achieve the developer's specific goals, such as compliance
with application- and business-related constraints, and that
these specific goals will vary from one implementation to
another and from one developer to another. Moreover, it will
be appreciated that such a development effort might be
complex and time-consuming, but would nevertheless be a
routine undertaking of engineering for those of ordinary skill
in the art having the benefit of this disclosure.
In accordance with the present invention, the components,
process steps, and/or data structures may be implemented
using various types of operating systems, computing
platforms, computer programs, and/or general purpose
machines. In addition, those of ordinary skill in the art will
recognize that devices of a less general purpose nature, such
as hardwired devices, field programmable gate arrays
(FPGAs), application specific integrated circuits (ASICs), or
the like, may also be used without departing from the scope
and spirit of the inventive concepts disclosed herein.
Turning now to FIG. 4, a block diagram of an exemplary
embodiment of a feedback active noise cancellation system

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74 must later be up-sampled by the second input samplingrate converter 78 to the intermediate sampling rate (IFs).
Similar to above, it is also possible to combine the input
delt-asigma modulator 72 and the first input sampling-rate
converter 74 into an input ADC with an output rate of KFs.
It is worth noting that M,.N, and K are not necessarily
related to one another except that K is assumed to be less
than M. M may or may not be equal toN. Also of note is the
fact that the equalizer 76 is not in the critical delay path, that
is, it is outside of the closed loop. As a result, either Finite
Impulse Response (FIR) or Infinite Impulse Response (IIR)
filters with higher order can be used to achieve better
equalization. As an alternative to the example shown, it is
possible that the first sampling-rate converter 74, either
alone or as part of the input ADC, has an output rate equal
to the intermediate sampling rate. In such a case, the second
input sampling-rate converter 78 can be eliminated. In the
latter case, the equalizer 76 may also be eliminated leaving
only the input delta-sigma modulator 72 and the first input
sampling-rate converter 74. Recall that the input delta-sigma
modulator 72 and the first input sampling-rate converter 74
may also be replaced with the input ADC. If so, this would
leave the input ADC as the only element of the input
processor 52.
Rather than an analog signal, assume now that the INPUT
signal is a digital signal (Din). If so, then there will be no
need for the input delta-sigma modulator 72 and the first
input sampling-rate converter 74 shown. These can be
eliminated. That leaves the equalizer 76 and the second input
sampling-rate converter 78. Of course since there is now
only one, the term second could be dropped leaving only an
input sampling-rate converter 78. Depending on the
circumstances, these remaining two elements may appear in
one of four configurations, that is, the one, the other, both,
and neither. When the sampling rate of the digital signal is
already at the intermediate rate, then there will be no need
for the sampling-rate converter 78. When the sampling rate
is not equal to the intermediate rate, then there will be a need
for up-sampling or down-sampling, depending on the
circumstances, by the input sampling-rate converter 78.
Similarly, there may or may not bee a need or desire for
equalization, depending on the circumstances, and when
there is not then the equalizer 76 may be eliminated. It is
therefore possible in a digital context that the input processor 52 may merely pass the signal through to the first
summation node 66 of FIGS. 4 and 5 without transformation. Nevertheless, for the sake of uniformity, the signal is
referred to as the processed digital input signal to distinguish
it from the generalized INPUT signal which may or may not
require transformation.
Other embodiments of the present invention include but
are not limited to incorporation of programmable or adaptive
equalizers and compensation filters, FIR and IIR, and associated hardware and software capabilities for achieving the
same. It should be noted that the various features of the
foregoing exemplary embodiments were discussed separately for clarity of description only and they can be incorporated in whole or in part into a single embodiment of the
present invention having some or all of these features. It
should also be noted that the present invention is not limited
to active noise cancellation but can readily be used in
conjunction with other signal processing devices such as
communication systems having undesirable latencies.
Other embodiments, features, and advantages of the
present invention will be apparent to those skilled in the art
from a consideration of the foregoing specification as well as
through practice of the invention and alternative embodi-

ments and methods disclosed herein. Therefore, it should be
emphasized that the specification and embodiments are
exemplary only, and that .the true scope and spirit of the
invention is limited only by the claims.
What is claimed is:
1. A digital closed feedback loop having an input, an
output, a first summation node, and a second summation
node, wherein a processed digital input signal is fed to a first
input of the first summation node, the processed digital input
signal has an intermediate sampling rate, and a disturbance
signal is fed to a first input of the second summation node,
the digital closed feedback loop comprising:
a compensation filter having an input coupled to an output
of the first summation node;
a digital-to-analog converter having an input coupled to
an output of the compensation filter;
an output transducer having an input coupled to an output
of the digital-to-analog converter and having an output
coupled to a second input of the second summation
node;
an input transducer having an input coupled to an output
of the second summation node;
a delta-sigma modulator having an input coupled to an
output of the input transducer, wherein the output
signal of the delta-sigma modulator has a first sampling
rate that is higher than the intermediate sampling rate;
and
a feedback sampling-rate converter having an input
coupled to an output of the delt-asigma modulator and
having an output coupled to a second input of the first
summation node, wherein the output signal of the
delta-sigma modulator is down-sampled from the first
sampling rate to the intermediate sampling rate.
2. The digital closed feedback loop according to claim 1,
further comprising an input processor for transforming an
input signal into the processed digital input signal.
3. The digital closed feedback loop according to claim 2,
wherein the input processor further comprises:
an input delta-sigma modulator having an input that
receives the input signal, wherein the input signal is
modulated to a second sampling rate that is higher than
the intermediate sampling rate;
a first input sampling-rate converter having an input
coupled to an output of the input delta-sigma
modulator, wherein the second sampling rate is downsampled to a third sampling rate; and
an equalizer having an input coupled to an output of the
first input sampling-rate converter.
4. The digital closed feedback loop according to claim 3,
wherein the third sampling rate is equal to the intermediate
sampling rate and the output signal from an output of the
equalizer is the processed digital input signal.
5. The digital closed feedback loop according to claim 3,
wherein the third sampling rate is less than the intermediate
sampling rate and the input processor further comprises:
a second input sampling-rate converter having an input
coupled to an output of the equalizer, wherein the third
sampling rate is up-sampled to the intermediate sampling rate and the output signal from an output of the
second input sampling-rate converter is the processed
digital input signal.
6. The digital closed feedback loop according to claim 2,
wherein the input processor further comprises:
an input delta-sigma modulator having an input that
receives the input signal, wherein the input signal is

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modulated to a second sampling rate that is higher than
modulated to a second sampling rate that is higher than
the intermediate sampling rate;
the intermediate sampling rate; and
a first input sampling-rate converter having an input
an input sampling-rate converter having an input coupled
to an output of the input delta-sigma modulator,
coupled to an output of the input delta-sigma
wherein the second sampling rate is down-sampled to 5
modulator, wherein the second sampling rate is downsampled to a third sampling rate; and
the intermediate sampling rate and the output signal
from an output of the input sampling-rate converter is
an equalizer having an input coupled to an output of the
the processed digital input signal.
first input sampling-rate converter.
7. The digital closed feedback loop according to claim 2,
13. The digital closed feedback loop according to claim
10
wherein the input processor further comprises:
12, wherein the third sampling rate is equal to the intermean equalizer having an input that receives the input signal
diate sampling rate and the output signal from an output of
and having an output that is the source of the processed
the equalizer is the processed digital input signal.
14. The digital closed feedback loop according to claim
digital input signal.
8. The digital closed feedback loop according to claim 2,
12, wherein the third sampling rate is less than the interme15
wherein the input processor further comprises:
diate sampling rate and the input processor further comprises:
an equalizer having an input that receives the input signal;
a second input sampling-rate converter having an input
and
coupled to an output of the equalizer, wherein the third
an input sampling-rate converter having an input coupled
sampling rate is up-sampled to the intermediate samto an output of the equalizer, wherein the input signal 20
pling rate and the output signal from an output of the
is converted from a second sampling rate to the intersecond input sampling-rate converter is the processed
mediate sampling rate and the output signal from an
digital input signal.
output of the input sampling-rate converter is the
15. The digital closed feedback loop according to claim
processed digital input signal.
9. The digital closed feedback loop according to claim 2, 25 11, wherein the input processor further comprises:
wherein the input processor further comprises:
an input delta-sigma modulator having an input that
receives the input signal, wherein the input signal is
an input sampling-rate converter having an input that
modulated to a second sampling rate that is higher than
receives the input signal and having an output that is the
the intermediate sampling rate; and
source of the processed digital input signal, wherein the
input signal is converted from a second sampling rate 30
an input sampling-rate converter having an input coupled
to the intermediate sampling rate.
to an output of the input delt-asigma modulator,
10. A digital closed feedback loop having an input, an
wherein the second sampling rate is down-sampled to
output, a first summation node, and a second summation
the intermediate sampling rate and the output signal
from an output of the input sampling-rate converter is
node, wherein a processed digital input signal is fed to a first
the processed digital input signal.
input of the first summation node, the processed digital input 35
signal has an intermediate sampling rate, and a disturbance
16. The digital closed feedback loop according to claim
11, wherein the input processor further comprises:
signal is fed to a first input of the second summation node,
the digital closed feedback loop comprising:
an equalizer having an input that receives the input signal
a digital-to-analog converter having an input coupled to
and having an output that is the source of the processed
40
digital input signal.
an output of the first summation node;
17. The digital closed feedback loop according to claim
an output transducer having an input coupled to an output
11, wherein the input processor further comprises:
of the digital-to-analog converter and having an output
an equalizer having an input that receives the input signal;
coupled to a second input of the second summation
and
node;
an input transducer having an input coupled to an output 45
an input sampling-rate converter having an input coupled
of the second summation node;
to an output of the equalizer, wherein the input signal
is converted from a second sampling rate to the intera delta-sigma modulator having an input coupled to an
mediate sampling rate and the output signal from an
output of the input transducer, wherein the output
output of the input sampling-rate converter is the
signal of the delta-sigma modulator has a first sampling
50
processed digital input signal.
rate that is higher than the intermediate sampling rate;
18. The digital closed feedback loop according to claim
a feedback sampling-rate converter having an input
11, wherein the input processor further conprises:
coupled to an output of the delta-sigma modulator,
an input sampling-rate converter having an input that
wherein the output signal of the delta-sigma modulator
receives the input signal and having an output that is the
is down-sampled from the first sampling rate to the 55
source of the processed digital input signal, wherein the
intermediate sampling rate; and
input signal is converted from a second sampling rate
a compensation filter having an input coupled to an output
to the intermediate sampling rate.
of the feedback sampling-rate converter and having an
19. A digital closed feedback loop method comprising:
output coupled to a second input of the first summation
processing an input signal into a processed digital input
node.
60
signal having a preselected intermediate sampling rate;
11. The digital closed feedback loop according to claim
converting an analog output signal into a digital feedback
10, further comprising an input processor for transforming
signal having substantially the same preselected interan input signal into the processed digital input signal.
12. The digital closed feedback loop according to claim
mediate sampling rate;
11, wherein the input processor further comprises:
combining the processed digital input signal and the
65
an input delta-sigma modulator having an input that
digital feedback signal to form a combined digital
receives the input signal, wherein the input signal is
signal;

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generating a digital anti disturbance signal from the
combined digital signal;
converting the digital anti disturbance signal to an analog
anti disturbance signal; and

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combining the analog anti disturbance signal with a
disturbance signal to form the analog output signal.

* * * * *

UNITED STATES PATENT AND TRADEMARK OFFICE

CERTIFICATE OF CORRECTION
PATENT NO.
: 6,717,537B1
DATED
: April6, 2004
INVENTOR(S) : Xiaoling Fang, Keith L. Davis and Martin R. Johnson

Page 1 of 1

It is certified that error appears in the above-identified patent and that said Letters Patent is
hereby corrected as shown below:

Column 1,
Line 29, after "a" insert-- wide variety of electro-optical manufacturing and circuit
design configurations depending upon--.
Column4,
Line 9, replace "(Finax)" with -- (F max) --.
Line 34, replace "(Vout)" with-- (Yout) --.
ColumnS,
Line 4, replace "delt-asigma" with-- delta-sigma--.
Line 6, replace "M, .N," with-- M, N, --.
Column 6,
Line 30, replace "delt-asigma" with-- delta-sigma--.
Column 8,
Line 30, replace "delt-asigma" with-- delta-sigma--.
Line 53, replace "conprises:" with-- comprises--.

Signed and Sealed this
Twenty-second Day of February, 2005

<

· · · · · · · · ~· · ·
.

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............. .

JONW.DUDAS

Director of the United States Patent and Trademark Office

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