Bose Corporation v. Beats Electronics LLC et al

Filing 1

COMPLAINT filed with Jury Demand - against Beats Electronics International Limited, Beats Electronics LLC - Magistrate Consent Notice to Pltf. ( Filing fee $ 400, receipt number 0311-1560024.) - filed by Bose Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3, # 4 Exhibit 4, # 5 Exhibit 5, # 6 Exhibit 6, # 7 Exhibit 7, # 8 Exhibit 8, # 9 Exhibit 9, # 10 Exhibit 10, # 11 Civil Cover Sheet)(rwc)

Exhibit 6

UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
July 09, 2014
THIS IS TO CERTIFY THAT ANNEXED HERETO IS A TRUE COPY FROM
THE RECORDS OF THIS OFFICE OF:

U.S. PATENT: 8,345,888
ISSUE DATE: January 01,2013

By Authority of the
Under Secretary of Commerce for Intellectual Property
and Director of the United States Patent and Trademark Office

M. TARVER
Certifying Officer

111111

1111111111111111111111111111111111111111111111111111111111111
US008345888B2

United States Patent

(10)

Carreras et al.

c12)

(45)

(54)

DIGITAL HIGH FREQUENCY PHASE
COMPENSATION

(75)

Inventors: Ricardo F. Carreras, Southborough,
MA (US); Daniel M. Gauger, Jr.,
Cambridge, MA (US); Steven H.
Isabelle, Newton, MA (US)

(73)

Assignee: Bose Corporation, Framingham, MA
(US)

( *)

Notice:

(21)

Appl. No.: 12/750,309

(22)

Filed:

Patent No.:
US 8,345,888 B2
Date of Patent:
Jan.l,2013

5,710,819
5,815,582
5,852,667
5,937,070
6,035,050
6,041,126
6,118,878
6,160,893
6,236,731
6,240,192
6,418,228
6,445,799
6,522,753
6,532,296
6,567,524
6,717,537

Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 316 days.

A
111998 Tapholm eta!.
A
9/1998 Claybaugh eta!.
A
12/1998 Pan et a!.
A .. 811999 Todter eta! .................. 381171.6
A
3/2000 Weinfurtner et a!.
3/2000 Terai eta!.
A
A
9/2000 Jones
A
12/2000 Saunders et a!.
B1
5/2001 Brennan et a!.
B1
512001 Brennan et a!.
B1
7/2002 Terai eta!.
Bl
9/2002 Taenzer et al.
B1
2/2003 Matsuzawa et a!.
B1
3/2003 Vaudrey et a!.
B1
5/2003 Svean et a!.
B1
4/2004 Fang eta!.

(Continued)
FOREIGN PATENT DOCUMENTS
Mar. 30, 2010

(65)

EP

(51)
(52)
(58)

OTHER PUBLICATIONS

Oct. 28, 2010

Related U.S. Application Data

Invitation to Pay Additional Fees dated Aug. 3, 2010 for PCT/
US20 10/032403.

Continuation-in-part of application No. 12/431,003,
filed on Apr. 28, 2009, now Pat. No. 8,085,946.
Int. Cl.
GJOK 11116
(2006.01)
U.S. Cl•.................................... 381/71.6; 381/71.14
Field of Classification Search ................. 381/71.6,
381/71.11,71.1, 71.14, 72, 73.1, 74,97
See application file for complete search history.
References Cited

(56)

U.S. PATENT DOCUMENTS
4,947,432
4,953,217
5,202,927
5,303,306
5,410,605
5,444,788

A
A "'
A
A
A
A

8/1990
8/1990
4/1993
4/1994
4/1995
8/1995

Topholm
Twiney eta! ................ 381171.6
Topholm
Brillhart et a!.
Sawada eta!.
Orban

4/1998

(Continued)

Prior Publication Data
US 2010/0272283 AI

(63)

0836736 A1

(Continued)

Primary Examiner- Xu Mei
Assistant Examiner- David Ton
ABSTRACT

(57)

In anANR circuit of a personalANR device, a digital filter is
structured to introduce one or more zeros to add gain to
introduce positive phase in the provision of feedback-based
ANR, wherein the gain follows a frequency-dependent "skislope" gain curve with little gain added at lower audible
frequencies, with increasing gain that increases with frequency added at higher audible frequencies, and with the
increasing gain flattening at frequencies above audible frequencies.
16 Claims, 29 Drawing Sheets

.........

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US 8,345,888 B2
Page2

2010/0272278
2010/0272279
2010/0272280
2010/0272281
2010/0272282
2010/0272284
2010/0274564
2010/0310086
2011/0130176
2011/0176697
2011/0188665
2011/0243343
2011/0243344
2011/0243345

U.S. PATENT DOCUMENTS
6,741,707
6,870,940
6,996,241
7,039,195
7,103,188
7,630,504
7,853,028
7,945,065
7,983,908
2003/0053636
2005/0078845
2005/0117754
2006/0222192
2007/0253567
2007/0253568
2008/0112570
2008/0212791
2008/0310645
2009/0046867
2009/0296949
2010/0266137
2010/0272275
2010/0272276
2010/0272277

B2
B2
B2
B1
B1
B2
B2
B2
B2
A1
A1
A1
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A1 *
A1 *
A1
A1 *
A1
A1
A1
A1

5/2004
3/2005
2/2006
5/2006
9/2006
12/2009
12/2010
5/2011
7/2011
3/2003
4/2005
6/2005
10/2006
1112007
1112007
5/2008
9/2008
12/2008
2/2009
12/2009
10/2010
10/2010
10/2010
10/2010

Ray eta!.
Meyer eta!.
Rayet a!.
Svean eta!.
Jones
Poulsen
Fischer
Menzletal.
Kuboki et a!.
Goldberg et a!.
Aschoff eta!.
Sakawaki
Matthey
Sapiejewski
Sapiejewski
Asada eta! ..................
Asada eta! ..................
Itabashi et a!. .... ... ... .....
Clemow
Iwata eta! ...................
Sibbald et a!.
Carreras et a!.
Carreras et a!.
Joho eta!.

A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1

10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
12/2010
6/2011
7/2011
8/2011
10/2011
10/2011
10/2011

Joho eta!.
Joho eta!.
Joho eta!.
Carreras et a!.
Carreras
Joho eta!.
Bakalos eta!.
Magrath et a!.
Magrath et a!.
Apfel eta!.
Burge eta!.
Gauger, Jr. et a!.
Bakalos et a!.
Carreras eta!.

FOREIGN PATENT DOCUMENTS
381/71.6
381/71.6
381/71.6
381/71.6

EP
JP

wo

1970902 A2
2005257720 A
8900746 A1

9/2008
9/2005
l/1989

OTHER PUBLICATIONS
International Search Report and Written Opinion dated Dec. 1, 2010
for PCT/US20 10/032403.

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2

DIGITAL HIGH FREQUENCY PHASE
COMPENSATION

device to derive a downsampled form of the digital data;
operating an interface of the ANR circuit that couples the
ANR circuit to a bus to which the processing device is also
CROSS-REFERENCE TO RELATED
coupled to transmit the downs amp led form of the digital data
APPLICATION
5 to the processing device as side-chain data; and operating the
processing device to employ the side-chain data as an input to
The present application is a continuation-in-part of applithe ANR analysis.
cation Ser. No. 12/431,003 filed Apr. 28, 2009 by Ricardo F.
Implementations may include, and are not limited to, one
Carreras, Marcel Joho and Daniel M. Gauger, now U.S. Pat.
or more of the following features. The processing device may
No. 8,085,946, the disclosure of which is incorporated herein 10 perform the ANR analysis as part of cooperating with the
by reference.
ANR circuit to provide adaptive ANR. The method may further include routing the downsampled form of the digital data
TECHNICAL FIELD
through a bandpass filter to limit the range of frequencies of
reference sounds represented by the downsampled form of
This disclosure relates to personal active noise reduction 15
the digital data prior to operating the interface of the ANR
(ANR) devices to reduce acoustic noise in the vicinity of at
circuitto transmit the downsampled form of the digital data as
least one of a user's ears.
the side-chain data to the processing device. The method may
further include routing the downsampled form of the digital
BACKGROUND
20 data through a filter to provide weighting to frequencies of
reference sounds represented by the downsampled form of
Headphones and other physical configurations of personal
the digital data prior to operating the interface of the ANR
ANR device worn about the ears of a user for purposes of
circuit to transmit the downsampled form of the digital data as
isolating the user's ears from unwanted environmental
the side-chain data to the processing device. The method may
sounds have become commonplace. In particular, ANR headphones in which unwanted environmental noise sounds are 25 further include calculating a signal strength value of the
downsampled form of the digital data, and operating the
countered with the active generation of anti-noise sounds,
interface of the ANR circuit to transmit the signal strength
have become highly prevalent, even in comparison to headvalue, instead of the downsampled form of the digital data, as
phones or ear plugs employing only passive noise reduction
the side-chain data to the processing device, wherein the
(PNR) technology, in which a user's ears are simply physically isolated from environmental noises. Especially ofinter- 30 signal strength value may be a RMS value and an absolute
value. The method may further include operating the interface
est to users are ANR headphones that also incorporate audio
of the ANR circuit to receive ANR settings from the processlistening functionality, thereby enabling a user to listen to
ing device that are derived through the ANR analysis perelectronically provided audio (e.g., playback of recorded
formed by the processing device, possibly storing the ANR
audio or audio received from another device) without the
35 settings received from the processing device, and possibly
intrusion of unwanted environmental noise sounds.
dynamically configuring at least one filter employed by the
Unfortunately, despite various improvements made over
ANR circuit in performing the at least one offeedback-based
time, existing personal ANR devices continue to suffer from
and feedforward-based ANR with at least one coefficient
a variety of drawbacks. Foremost among those drawbacks are
taken from the ANR settings received from the processing
undesirably high rates of power consumption leading to short
battery life, undesirably narrow ranges of audible frequencies 40 device.
In one aspect, an apparatus includes a firstANR circuit, and
in which unwanted environmental noise sounds are countered
the first ANR circuit includes an ADC comprising a primary
through ANR, instances of unpleasant ANR-originated
output through which the ADC outputs a first digital data
sounds, and instances of actually creating more unwanted
representing reference sounds detected by a first microphone,
noise sounds than whatever unwanted environmental sounds
45 the first microphone being one of a feedback microphone and
may be reduced.
a feedforward microphone; and an interface coupling the first
SUMMARY
ANR circuit to a bus through which the first ANR circuit is
able to be coupled to a processing device performing ANR
An ANR circuit, possibly of a personal ANR device and
analysis, the interface being operable to transmit a first sidepossibly within an ADC of the ANR circuit, feedback refer- 50 chain data through the bus to the processing device to enable
ence data, feedforward reference data and/or pass-through
the first side-chain data to be employed by the processing
audio data is provided to a secondary downsampling (and/or
device as an input to the ANR analysis, the first side-chain
decimating) filter and/or is provided to a calculating block
data being derived from the first digital data by at least downsampling the first digital data.
(e.g., RMS or absolute calculation block) to derive side-chain
data to be output by the ANR circuit to a processing device 55
Implementations may include, and are not limited to, one
coupled to theANR circuit to employ the side-chain data in an
or more ofthe following features. The processing device may
analysis related to the provision of feedback-based ANR,
perform the ANR analysis as part of cooperating with the first
feedforward-based ANR and/or pass-through audio by the
ANR circuit to provide adaptive ANR. The ADC may further
include a downsampling block to downsample the first digital
ANR circuit.
In one aspect, a method of supporting ANR analysis per- 60 data output by the ADC as part of deriving the first side-chain
data; a secondary output through which the ADC outputs the
formed by a processing device coupled to an ANR circuit
first side-chain data to the interface; possibly a bandpass filter,
performing at least one offeedback-based and feedforwardbased ANR in at least one earpiece of a personal ANR device
an A-weighted filter or a B-weighted filter interposed
includes: downsampling digital data representing reference
between the downsampling block and the secondary output;
sounds detected by at least one of a feedback microphone 65 and/or possibly a signal strength calculating block interposed
disposed within the at least one earpiece and a feedforward
between the downsampling block and the secondary output to
calculate a signal strength value of as part of deriving the first
microphone disposed on a portion of the personal ANR

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side-chain data, wherein the signal strength calculating block
introduce a positive phase, and selecting the at least one
may be a RMS block or an absolute value block
coefficient to cause the addition of a gain that increases with
The ANR circuit may further include at least one digital
frequency within a portion of a range of audible frequencies
filter to derive anti-noise sounds from reference sounds
and that flattens in a range of frequencies above the range of
detected by one of a feedback microphone and a feedforward 5 audible frequencies.
microphone; wherein the interface is further operable to
Implementations may include, and are not limited to, one
receive ANR settings to enable the at least one digital filter to
or more of the following features. The method may further
be configured with at least one coefficient taken from the
include selecting a FIR filter as the digital filter. Further, the
ANR settings, theANR settings being derived by the processFIR filter may include at least four taps, and selecting the at
ing device through the ANR analysis. The ANR circuit may 10
least one coefficient may include selecting a coefficient for
still further include a first buffer, a second buffer, and a third
each of the at least four taps to implement the high-frequency
buffer; wherein the at least one digital filter coefficient is
phase compensation transform as at least a fourth order transstored in one of the first buffer and the second buffer; wherein
form.
the first and second buffers are alternately employed in conThe method may further include selecting at least one
figuring coefficient settings of the at least one digital filter in 15
biquad filter as the digital filter, and programming another tap
coordination with a data transfer rate of the at least one digital
of the at least one biquad filter that is structured to enable the
filter; and wherein a failsafe filter coefficient is stored in the
at least one biquad filter to introduce a pole with another
third buffer to configure the at least one digital filter in
coefficient to cause the at least one biquad filter to not employ
response to an instance of instability being detected. The
apparatus may further include a first earpiece; the first micro- 20 the another tap to introduce a pole. Selecting the at least one
coefficient may include selecting the at least one coefficient to
phone, wherein the first microphone is disposed on the first
introduce the at least one zero to cause the gain to start
earpiece; the processing device; and the bus. The apparatus
may still further include a second earpiece; a second microincreasing with gain at a higher audible frequency beneath 15
phone disposed on the second earpiece; and a second ANR
KHz. The method may further include positioning the at least
circuit, wherein the second ANR circuit includes a second 25 one digital filter along a feedback ANR pathway of an ANR
ADC comprising a primary output through which the second
circuit of the personal ANR device at a position after both a
ADC outputs a second digital data representing second refsigma-delta analog-to-digital converter and a downsampling
erence sounds detected by the second microphone, and a
block of the ANR circuit of the personal ANR device.
second interface coupling the second ANR circuit to the proIn another aspect, an ANR circuit structured to provide at
cessing device to transmit a second side-chain data to the 30 least one of feedforward-based ANR and feedback-based
processing device to enable the second side-chain data to be
ANR, the ANR circuit includes at least a first digital filter
employed by the processing device as an input to the ANR
positioned along a pathway defined in the ANR circuit and
analysis, the second side-chain data being derived from the
configured with at least a first coefficient to implement a first
second digital data by at least downsampling the second
transform to generate digital data representing an anti-noise
35
digital data.
sound, and at least a second digital filter positioned along the
In one aspect, an ADC includes a primary output through
pathway and configured with at least a second coefficient to
which the ADC outputs digital data representing reference
introduce at least one zero to implement high-frequency
sounds also represented by an analog signal received by a
phase compensation transform to introduce a positive phase
microphone, a downsampling block to downsample the digital data as part of deriving side-chain data, and a secondary 40 in the pathway to increase at least one of a magnitude and an
upper frequency ofa range offrequencies at which the at least
output through which the ADC outputs the side-chain data.
one of the feedforward-basedANR and the feedback-based
Implementations may include, and are not limited to, one
or more of the following features. The ADC may further
ANR is provided. Further, introducing the at least one zero
include one of a bandpass filter, an A-weighted filter and a
adds gain increasing with frequency at least partly within a
B-weighted filter interposed between the downsampling 45 range of audible frequencies, and the gain flattens in a range
block and the secondary output. The ADC may further
offrequencies above the range of audible frequencies.
include a signal strength calculating block interposed
Implementations may include, and are not limited to, one
between the downsampling block and the secondary output to
or more of the following features. The at least a second digital
calculate a signal strength value of as part of deriving the
filter may be a FIR filter. Further, the FIR filter may include at
side-chain data, wherein the signal strength calculating block 50 least four taps, and the at least a second coefficient may
may be a RMS block or an absolute value block
include a coefficient for each of the at least four taps to
In anANR circuit of a personal ANR device, a digital filter
implement the high-frequency phase compensation transis structured to introduce one or more zeros to add gain to
form as at least a fourth order transform. Alternatively, the at
introduce positive phase in the provision of feedback-based
least a second digital filter may be a biquad filter.
ANR, wherein the gain follows a frequency-dependent "ski- 55
TheANR circuit may further include a sigma-delta analogslope" gain curve with little gain added at lower audible
to-digital converter positioned at an end of the pathway to
frequencies, with increasing gain that increases with freconvert an analog signal received from a microphone of a
quency added at higher audible frequencies, and with the
personal ANR device into which the ANR circuit is incorpoincreasing gain flattening at frequencies above audible fre60 rated into digital data representing a reference noise sound
quencies.
sampled at a first rate, and a downsampling block positioned
In another aspect, a method of implementing a high-frein the pathway following the sigma-delta analog-to-digital
quency phase compensation transform to enable increasing at
converter to reduce a data transfer rate of the digital data from
least one of a magnitude and an upper frequency of a range of
the first rate to a second rate that is lower than the first rate.
frequencies at which ANR is provided in a personal ANR
device includes programming a digital filter having at least 65 The at least a second coefficient may be selected to introduce
the at least one zero to cause the gain to start increasing with
one tap with at least one coefficient to cause the digital filter
gain at a higher audible frequency beneath 15 KHz.
to employ the at least one tap to introduce at least one zero to

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Other features and advantages of the invention will be
apparent from the description and claims that follow.

two-way audio communications, one-way audio communications (i.e., acoustic output of audio electronically provided
by another device), or no communications, at all. It is
intended that what is disclosed and what is claimed herein is
applicable to personal ANR devices that are wirelessly connected to other devices, that are connected to other devices
through electrically and/or optically conductive cabling, or
that are not connected to any other device, at all. It is intended
that what is disclosed and what is claimed herein is applicable
to personal ANR devices having physical configurations
structured to be worn in the vicinity of either one or both ears
of a user, including and not limited to, headphones with either
one or two earpieces, over-the-head headphones, behind-theneck headphones, headsets with communications microphones (e.g., boom microphones), wireless headsets (i.e.,
earsets), single earphones or pairs of earphones, as well as
hats or helmets incorporating one or two earpieces to enable
audio communications and/or ear protection. Still other
physical configurations of personal ANR devices to which
what is disclosed and what is claimed herein are applicable
will be apparent to those skilled in the art.
Beyond personal ANR devices, what is disclosed and
claimed herein is also meant to be applicable to the provision
ofANR in relatively small spaces in which a person may sit or
stand, including and not limited to, phone booths, car passenger cabins, etc.
FIG. 1 provides a block diagram of a personalANR device
1000 structured to be worn by a user to provide active noise
reduction (ANR) in the vicinity of at least one of the user's
ears. As will also be explained in greater detail, the personal
ANR device 1000 may have any of a number of physical
configurations, some possible ones of which are depicted in
FIGS. 2a through 2j Some of these depicted physical configurations incorporate a single earpiece 100 to provideANR
to only one ofthe user's ears, and others incorporate a pair of
earpieces 100 to provide ANR to both of the user's ears.
However, it should be noted that for the sake of simplicity of
discussion, only a single earpiece 100 is depicted and
described in relation to FIG. 1. As will also be explained in
greater detail, the personal ANR device 1000 incorporates at
least one ANR circuit 2000 that may provide either or both of
feedback-based ANR and feedforward-based ANR, in addition to possibly further providing pass-through audio. FIGS.
3a and 3b depict a couple of possible internal architectures of
the ANR circuit 2000 that are at least partly dynamically
configurable. Further, FIGS. 4a through 4e depict some possible signal processing topologies and FIGS. 5a through 5e
depict some possible filter block topologies that may theANR
circuit 2000 maybe dynamically configured to adopt. Further,
the provision of either or both of :feedback-based ANR and
feedforward-basedANR is in addition to at least some degree
ofpassive noise reduction (PNR) provided by the structure of
each earpiece 100. Still further, FIGS. 6a through 6c depict
various forms of triple-buffering that may be employed in
dynamically configuring signal processing topologies, filter
block topologies and/or still other ANR settings.
Each earpiece 100 incorporates a casing 110 having a
cavity 112 at least partly defined by the casing 110 and by at
least a portion of an acoustic driver 190 disposed within the
casing to acoustically output sounds to a user's ear. This
manner of positioning the acoustic driver 190 also partly
defines another cavity 119 within the casing 110 that is separated from the cavity 112 by the acoustic driver 190. The
casing 110 carries an ear coupling 115 surrounding an opening to the cavity 112 and having a passage 117 that is formed
through the ear coupling 115 and that communicates with the
opening to the cavity 112. In some implementations, an

DESCRIPTION OF THE DRAWINGS
5

FIG.l is a blockdiagramofportions of an implementation
of a personal ANR device.
FIGS. 2a through 2/ depict possible physical configurations of the personal ANR device of FIG. 1.
FIGS. 3a and 3b depict possible internal architectures ofan
ANR circuit of the personal ANR device of FIG. 1.
FIGS. 4a through 4g depict possible signal processing
topologies that may be adopted by the ANR circuit of the
personal ANR device ofFIG.l.
FIGS. 5a through 5e depict possible filter block topologies
that may be adopted by theANR circuit of the personalANR
device of FIG. 1.
FIGS. 6a through 6c depict possible variants of triplebuffering that may be adopted by the ANR circuit of the
personal ANR device of FIG. 1.
FIG. 7a depicts a possible additional portion ofthe internal
architecture of FIG. 3a.
FIG. 7 b depicts a possible additional portion ofthe internal
architecture of FIG. 3b.
FIG. 8 is a flowchart of a possible boot loading sequence
that may be adopted by the ANR circuit of the personal ANR
device of FIG. 1.
FIG. 9a depicts a possible internal architecture ofanADC
of the ANR circuit of the personal ANR device of FIG. 1.
FIG. 9b depicts a possible additional portion of any of the
signal processing topologies of FIGS. 4a through 4g.
FIGS. lOa and lOb depict possible additional portions of
any of the signal processing topologies of FIGS. 4a through
4g.
FIG. 11 a depicts phase shifting caused by limitations and
propagation delays of acoustic and/or electronic components
that may be incorporated into the personal ANR device of
FIG.l.
FIG. 11 b depicts aspects of variants of high frequency
phase compensation transforms to counteract the phase shifting of FIG. 7a.
FIG.11 c depicts aspects of the results of employing a high
frequency phase compensation transform ofFIG. 7 b to counteract the phase shifting of FIG. 7a.
FIG. 12 depicts possible benefits of employing a high
frequency phase compensation transform of FIG. 7b.
FIGS.13a and 13b depict aspects of possible implementations of a high frequency phase compensation transform of
FIG. 7b.

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DETAILED DESCRIPTION
What is disclosed and what is claimed herein is intended to
be applicable to a wide variety of personal ANR devices, i.e.,
devices that are structured to be at least partly worn by a user 55
in the vicinity of at least one ofthe user's ears to provideANR
functionality for at least that one ear. It should be noted that
although various specific implementations of personal ANR
devices, such as headphones, two-way communications
headsets, earphones, earbuds, wireless headsets (also known 60
as "earsets") and ear protectors are presented with some
degree of detail, such presentations of specific implementations are intended to facilitate understanding through the use
of examples, and should not be taken as limiting either the
scope of disclosure or the scope of claim coverage.
65
It is intended that what is disclosed and what is claimed
herein is applicable to personal ANR devices that provide

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acoustically transparent screen, grill or other form of perforated panel (not shown) may be positioned in or near the
passage 117 in a manner that obscures the cavity and/or the
passage 117 from view for aesthetic reasons and/or to protect
components within the casing 110 from damage. At times
when the earpiece 100 is worn by a user in the vicinity of one
of the user's ears, the passage 117 acoustically couples the
cavity 112 to the ear canal of that ear, while the ear coupling
115 engages portions of the ear to form at least some degree
of acoustic seal therebetween. Tbis acoustic seal enables the
casing 110, the ear coupling 115 and portions of the user's
head surrounding the ear canal (including portions of the ear)
to cooperate to acoustically isolate the cavity 112, the passage
117 and the ear canal from the environment external to the
casing 110 and the user's head to at least some degree, thereby
providing some degree ofPNR.
In some variations, the cavity 119 may be coupled to the
environment external to the casing 110 via one or more acoustic ports (only one of which is shown), each tuned by their
dimensions to a selected range of audible frequencies to
enhance characteristics of the acoustic output of sounds by
the acoustic driver 190 in a manner readily recognizable to
those skilled in the art. Also, in some variations, one or more
tuned ports (not shown) may couple the cavities 112 and 119,
and/or may couple the cavity 112 to the environment external
to the casing 110. Although not specifically depicted, screens,
grills or other forms ofperforated or fibrous structures may be
positioned within one or more of such ports to prevent passage of debris or other contaminants therethrough and/or to
provide a selected degree of acoustic resistance therethrough.
In implementations providing feedforward-basedANR, a
feedforward microphone 130 is disposed on the exterior of
the casing 110 (or on some other portion of the personal ANR
device 1000) in a manner that is acoustically accessible to the
environment external to the casing 110. Tbis external positioning of the feedforward microphone 130 enables the feedforward microphone 130 to detect environmental noise
sounds, such as those emitted by an acoustic noise source
9900, in the environment external to the casing 110 without
the effects of any form of PNR or ANR provided by the
personal ANR device 1000. As those familiar with feedforward-based ANR will readily recognize, these sounds
detected by the feedforward microphone 130 are used as a
reference from which feedforward anti-noise sounds are
derived and then acoustically output into the cavity 112 by the
acoustic driver 190. The derivation of the feedforward antinoise sounds takes into account the characteristics of the PNR
provided by the personal ANR device 1000, characteristics
and position of the acoustic driver 190 relative to the feedforward microphone 130, and/or acoustic characteristics of the
cavity 112 and/or the passage 117. The feedforward antinoise sounds are acoustically output by the acoustic driver
190 with amplitudes and time shifts calculated to acoustically
interact with the noise sounds of the acoustic noise source
9900 that are able to enterinto the cavity 112, the passage 117
and/or an ear canal in a subtractive manner that at least attenuates them.
In implementations providing feedback-based ANR, a
feedback microphone 120 is disposed within the cavity 112.
The feedback microphone 120 is positioned in close proximity to the opening of the cavity 112 and/or the passage 117 so
as to be positioned close to the entrance of an ear canal when
the earpiece 100 is worn by a user. The sounds detected by the
feedback microphone 120 are used as a reference from which
feedback anti-noise sounds are derived and then acoustically
output into the cavity 112 by the acoustic driver 190. The
derivation of the feedback anti-noise sounds takes into

account the characteristics and position of the acoustic driver
190 relative to the feedback microphone 120, and/or the
acoustic characteristics of the cavity 112 and/or the passage
117, as well as considerations that enhance stability in the
provision offeedback-basedANR. The feedback anti-noise
sounds are acoustically output by the acoustic driver 190 with
amplitudes and time shifts calculated to acoustically interact
with noise sounds of the acoustic noise source 9900 that are
able to enter into the cavity 112, the passage 117 and/or the
ear canal (and that have not been attenuated by whatever
PNR) in a subtractive manner that at least attenuates them.
The personalANR device 1000 further incorporates one of
theANRcircuit 2000associated with each earpiece 100 of the
personal ANR device 1000 such that there is a one-to-one
correspondence ofANR circuits 2000 to earpieces 100. Either
a portionofor substantially all ofeachANR circuit 2000 may
be disposed within the casing 110 of its associated earpiece
100.Alternatively and/or additionally, a portion of or substantially all of each ANR circuit 2000 may be disposed within
another portion of the personalANR device 1000. Depending
on whether one or both of feedback-basedANR and feedforward-based ANR are provided in an earpiece 100 associated
with the ANR circuit 2000, the ANR circuit 2000 is coupled
to one or both of the feedback microphone 120 and the feedforward microphone 130, respectively. The ANR circuit 2000
is further coupled to the acoustic driver 190 to cause the
acoustic output of anti-noise sounds.
In some implementations providing pass-through audio,
theANR circuit 2000 is also coupled to an audio source 9400
to receive pass-through audio from the audio source 9400 to
be acoustically output by the acoustic driver 190. The passthrough audio, unlike the noise sounds emitted by the acoustic noise source 9900, is audio that a user of the personal ANR
device 1000 desires to hear. Indeed, the user may wear the
personal ANR device 1000 to be able to hear the pass-through
audio without the intrusion of the acoustic noise sounds. The
pass-through audio may be a playback of recorded audio,
transmitted audio, or any of a variety of other forms of audio
that the user desires to hear. In some implementations, the
audio source 9400 may be incorporated into the personal
ANR device 1000, including and not limited to, an integrated
audio playback component or an integrated audio receiver
component. In other implementations, the personal ANR
device 1000 incorporates a capability to be coupled either
wirelessly or via an electrically or optically conductive cable
to the audio source 9400 where the audio source 9400 is an
entirely separate device from the personal ANR device 1000
(e.g., a CD player, a digital audio file player, a cell phone,
etc.).
In other implementations pass-through audio is received
from a communications microphone 140 integrated into variants of the personalANR device 1000 employed in two-way
communications in which the communications microphone
140 is positioned to detect speech sounds produced by the
user of the personal ANR device 1000. In such implementations, an attenuated or otherwise modified form of the speech
sounds produced by the user may be acoustically output to
one or both ears of the user as a communications sidetone to
enable the user to hear their own voice in a manner substantially similar to how they normally would hear their own
voice when not wearing the personal ANR device 1000.
In support of the operation of at least the ANR circuit 2000,
the personal ANR device 1000 may further incorporate one or
both of a storage device 170, a power source 180 and/or a
processing device (not shown).As will be explained in greater
detail, the ANR circuit 2000 may access the storage device
170 (perhaps through a digital serial interface) to obtainANR

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settings with which to configure feedback-based and/or feedforward-based ANR. As will also be explained in greater
detail, the power source 180 may be a power storage device of
limited capacity (e.g., a battery).
FIGS. 2a through 2/depict various possible physical configurations that may be adopted by the personal ANR device
1000 ofFIG.1. As previously discussed, different implementations of the personal ANR device 1000 may have either one
or two earpieces 100, and are structured to be worn on or near
a user's head in a manner that enables each earpiece 100 to be
positioned in the vicinity of a user's ear.
FIG. 2a depicts an "over-the-head" physical configuration
1500a of the personal ANR device 1000 that incorporates a
pair of earpieces 100 that are each in the form of an earcup,
and that are connected by a headband 102. However, and
although not specifically depicted, an alternate variant of the
physical configuration 1500a may incorporate only one of the
earpieces 100 connected to the headband 102. Another alternate variant of the physical configuration 1500a may replace
the headband 102 with a different band structured to be worn
around the back of the head and/or the back of the neck of a
user.
In the physical configuration 1500a, each of the earpieces
100 may be either an "on-ear'' (also commonly called "supraaural") or an "around-ear'' (also commonly called "circumaural") form of earcup, depending on their size relative to the
pinna of a typical human ear. As previously discussed, each
earpiece 100 has the casing 110 in which the cavity 112 is
formed, and that 110 carries the ear coupling 115. In this
physical configuration, the ear coupling 115 is in the form of
a flexible cushion (possibly ring-shaped) that surrounds the
periphery of the opening into the cavity 112 and that has the
passage 117 formed therethrough that communicates with the
cavity 112.
Where the earpieces 100 are structured to be worn as overthe-ear earcups, the casing 110 and the ear coupling 115
cooperate to substantially surround the pinna of an ear of a
user. Thus, when such a variant of the personal ANR device
1000 is correctly worn, the headband 102 and the casing 110
cooperate to press the ear coupling 115 against portions of a
side of the user's head surrounding the pinna of an ear such
that the pinna is substantially hidden from view. Where the
earpieces 100 are structured to be worn as on-ear earcups, the
casing 110 and ear coupling 115 cooperate to overlie peripheral portions of a pinna that surround the entrance of an
associated ear canal. Thus, when correctly worn, the headband 102 and the casing 110 cooperate to press the ear coupling 115 against portions of the pinna in a manner that likely
leaves portions of the periphery of the pinna visible. The
pressing of the flexible material of the ear coupling 115
against either portions of a pinna or portions of a side of a head
surrounding a pinna serves both to acoustically couple the ear
canal with the cavity 112 through the passage 117, and to
form the previously discussed acoustic seal to enable the
provision ofPNR.
FIG. 2b depicts another over-the-head physical configuration 1500b that is substantially similar to the physical configuration 1500a, but in which one of the earpieces 100 additionally incorporates a communications microphone 140
connected to the casing 110 via a microphone boom 142.
When this particular one of the earpieces 100 is correctly
worn, the microphone boom 142 extends from the casing 110
and generally alongside a portion of a cheek of a user to
position the communications microphone 140 closer to the
mouth of the user to detect speech sounds acoustically output
from the user's mouth. However, and although not specifically depicted, an alternative variant of the physical configu-

ration 1500b is possible in which the communications microphone 140 is more directly disposed on the casing 110, and
the microphone boom 142 is a hollow tube that opens on one
end in the vicinity of the user's mouth and on the other end in
the vicinity of the communications microphone 140 to convey sounds from the vicinity of the user's mouth to the vicinity of the communications microphone 140.
FIG. 2b also depicts the other of the earpieces 100 with
broken lines to make clear that still another variant of the
physical configuration 1500b of the personal ANR device
1000 is possible that incorporates only the one of the earpieces 100 that incorporates the microphone boom 142 and
the communications microphone 140. In such another variant, the headband 102 would still be present and would continue to be worn over the head of the user.
FIG. 2c depicts an "in-ear" (also commonly called "intraaural") physical configuration 1500c of the personal ANR
device 1000 that incorporates a pair of earpieces 100 that are
each in the form of an in-ear earphone, and that may or may
not be connected by a cord and/or by electrically or optically
conductive cabling (not shown). However, and although not
specifically depicted, an alternate variant of the physical configuration 1500c may incorporate only one of the earpieces
100.
As previously discussed, each of the earpieces 100 has the
casing 110 in which the open cavity 112 is formed, and that
carries the ear coupling 115. In this physical configuration,
the ear coupling 115 is in the form of a substantially hollow
tube-like shape defining the passage 117 that communicates
with the cavity 112. In some implementations, the ear coupling 115 is formed of a material distinct from the casing 110
(possibly a material that is more flexible than that from which
the casing 110 is formed), and in other implementations, the
ear coupling 115 is formed integrally with the casing 110.
Portions of the casing 110 and/or of the ear coupling 115
cooperate to engage portions of the concha and/or the ear
canal of a user's ear to enable the casing 110 to rest in the
vicinity of the entrance of the ear canal in an orientation that
acoustically couples the cavity 112 with the ear canal through
the ear coupling 115. Thus, when the earpiece 100 is properly
positioned, the entrance to the ear canal is substantially
"plugged" to create the previously discussed acoustic seal to
enable the provision ofPNR.
FIG. 2d depicts another in-ear physical configuration
1500d of the personal ANR device 1000 that is substantially
similar to the physical configuration 1500c, but in which one
of the earpieces 100 is in the form of a single-ear headset
(sometimes also called an "earset") that additionally incorporates a communications microphone 140 disposed on the
casing 110. When this earpiece 100 is correctly worn, the
communications microphone 140 is generally oriented
towards the vicinity of the mouth of the user in a manner
chosen to detect speech sounds produced by the user. However, and although not specifically depicted, an alternative
variant of the physical configuration 1500d is possible in
which sounds from the vicinity of the user's mouth are con~
veyed to the communications microphone 140 through a tube
(not shown), or in which the communications microphone
140 is disposed on a boom (not shown) connected to the
casing 110 and positioning the communications microphone
140 in the vicinity of the user's mouth.
Although not specifically depicted in FIG. 2d, the depicted
earpiece 100 of the physical configuration 1500d having the
communications microphone 140 may or may not be accompanied by another earpiece having the form of an in-ear
earphone (such as one of the earpieces 100 depicted in FIG.

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2c) that may or may not be connected to the earpiece 100
FIG. 3a depicts a possible internal architecture 2200a of
theANR circuit 2000 in which digital circuits that manipulate
depicted in FIG. 2d via a cord or conductive cabling (also not
digital data representing sounds are selectively interconshown).
nected through one or more arrays of switching devices that
FIG. 2e depicts a two-way communications handset physical configuration 1500e of the personalANR device 1000 that 5 enable those interconnections to be dynamically configured
during operation of the ANR circuit 2000. Such a use of
incorporates a single earpiece 100 that is integrally formed
switching devices enables pathways for movement of digital
with the rest of the handset such that the casing 110 is the
data among various digital circuits to be defined through
casing of the handset, and that may or may not be connected
programming. More specifically, blocks of digital filters of
by conductive cabling (not shown) to a cradle base with which
10 varying quantities and/or types are able to be defined through
it may be paired. In a manner not unlike one of the earpieces
which digital data associated with feedback-based ANR,
100 of an on-the-ear variant of either of the physical configufeedforward-basedANR and pass-through audio are routed to
rations 1500a and 1500b, the earpiece 100 of the physical
perform these functions. In employing the internal architecconfiguration 1500e carries a form of the ear coupling 115
ture 2200a, the ANR circuit 2000 incorporates ADCs 210,
that is configured to be pressed against portions of the pinna 15 310 and 410; a processing device 510; a storage 520; an
of an ear to enable the passage 117 to acoustically couple the
interface (I/F) 530; a switch array 540; a filter bank 550; and
cavity 112 to an ear canal. In various possible implementaa DAC 910. Various possible variations may further incorpotions, ear coupling 115 may be formed of a material distinct
rate one or more of analog VGAs 125, 135 and 145; a VGA
from the casing 110, or may be formed integrally with the
bank 560; a clock bank 570; a compression controller 950; a
casing 110.
20 further ADC 955; and/or an audio amplifier 960.
FIG. 2/depicts another two-way communications handset
TheADC 210 receives an analog signal from the feedback
physical configuration 1500/ of the personal ANR device
microphone 120, theADC 310 receives an analog signal from
1000 that is substantially similar to the physical configuration
the feedforward microphone 130, and theADC 410 receives
1500e, but in which the casing 110 is shaped somewhat more
an analog signal from either the audio source 9400 or the
appropriately for portable wireless communications use, pos- 25 communications microphone 140. As will be explained in
sibly incorporating user interface controls and/or display(s)
greater detail, one or more oftheADCs 210, 310 and 410 may
to enable the dialing ofphone numbers and/or the selection of
receive their associated analog signals through one or more of
radio frequency channels without the use of a cradle base.
the analog VGAs 125, 135 and 145, respectively. The digital
FIGS. 3a and 3b depict possible internal architectures,
outputs of each oftheADCs 210, 310 and 410 are coupled to
either of which may be employed by theANR circuit 2000 in 30 the switcharray540. EachoftheADCs 210,310 and410 may
implementations of the personal ANR device 1000 in which
be designed to employ a variant of the widely known sigmathe ANR circuit 2000 is at least partially made up of dynarnidelta analog-to-digital conversion algorithm for reasons of
cally configurable digital circuitry. In other words, the interpower conservation and inherent ability to reduce digital data
nal architectures of FIGS. 3a and 3b are dynamically configrepresenting audible noise sounds that might otherwise be
urable to adopt any of a wide variety of signal processing 35 introduced as a result of the conversion process. However, as
those skilled in the art will readily recognize, any of a variety
topologies and filter block topologies during operation of the
ANR circuit 2000. FIGS. 4a-g depict various examples of
of other analog-to-digital conversion algorithms may be
signal processing topologies that may be adopted bytheANR
employed. Further, in some implementations, at least the
circuit 2000 in this manner, and FIGS. 5a-e depict various
ADC 410 may be bypassed and/or entirely dispensed with
examples of filter block topologies that may also be adopted 40 where at least the pass-through audio is provided to theANR
by the ANR circuit 2000 for use within an adopted signal
circuit 2000 as digital data, rather than as an analog signal.
processing topology in this manner. However, and as those
The filter bank 550 incorporates multiple digital filters,
skilled in the art will readily recognize, other implementaeach of which has its inputs and outputs coupled to the switch
tions of the personal ANR device 1000 are possible in which
array 540. In some implementations, all of the digital filters
theANR circuit 2000 is largely or entirely implemented with 45 within the filter bank 550 are of the same type, while in other
analog circuitry and/or digital circuitry lacking such dynamic
implementations, the filter bank550 incorporates a mixture of
configurability.
different types of digital filters. As depicted, the filter bank
In implementations in which the circuitry of the ANR
550 incorporates a mixture of multiple downsampling filters
circuit 2000 is at least partially digital, analog signals repre552, multiple biquadratic (biquad) filters 554, multiple intersenting sounds that are received or output by theANR circuit 50 polating filters 556, and multiple finite impulse response
2000 may require conversion into or creation from digital
(FIR) filters 558, although other varieties of filters may be
data that also represents those sounds. More specifically, in
incorporated, as those skilled in the art will readily recognize.
both of the internal architectures 2200a and 2200b, analog
Further, among each of the different types of digital filters
signals received from the feedback microphone 120 and the
may be digital filters optimized to support different data transfeedforward microphone 130, as well as whatever analog 55 fer rates. By way of example, differing ones of the biquad
signal representing pass-through audio may be received from
filters 554 may employ coefficient values of differing biteither the audio source 9400 or the communications microwidths, or differing ones of the FIR filters 558 may have
phone 140, are digitized by analog-to-digital converters
differing quantities of taps. The VGA bank 560 (if present)
(ADCs) of the ANR circuit 2000. Also, whatever analog
incorporates multiple digital VGAs, each of which has its
signal is provided to the acoustic driver 190 to cause the 60 inputs and outputs coupled to the switch array 540. Also, the
acoustic driver 190 to acoustically output anti-noise sounds
DAC 910 has its digital input coupled to the switch array 540.
and/or pass-through audio is created from digital data by a
The clock bank 570 (ifpresent) provides multiple clock signal
digital-to-analog converter (DAC) oftheANR circuit 2000.
outputs coupled to the switch array 540 that simultaneously
Further, either analog signals or digital data representing
provide multiple clock signals for clocking data between
sounds may be manipulated to alter the amplitudes of those 65 components at selected data transfer rates and/or other purrepresented sounds by either analog or digital forms, respecposes. In some implementations, at least a subset of the multively, of variable gain amplifiers (VGAs).
tiple clock signals are synchronized multiples of one another

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to simultaneously support different data transfer rates in different pathways in which the movement of data at those
different data transfer rates in those different pathways is
synchronized.
The switching devices of the switch array 540 are operable
to selectively couple different ones of the digital outputs of
the ADCs 210, 310 and 410; the inputs and outputs of the
digital filters of the filter bank 550; the inputs and outputs of
the digital VGAs of the VGA bank 560; and the digital input
of the DAC 910 to form a set of interconnections therebetween that define a topology of pathways for the movement of
digital data representing various sounds. The switching
devices of the switch array 540 may also be operable to
selectively couple different ones of the clock signal outputs of
the clock bank 570 to different ones of the digital filters of the
filter bank 550 and/or different ones of the digital VGAs of the
VGA bank 560. It is largely in this way that the digital circuitry of the internal architecture 2200a is made dynamically
configurable. In this way, varying quantities and types of
digital filters and/or digital VGAs may be positioned at various points along different pathways defined for flows of digital data associated with feedback-basedANR, feedforwardbased ANR and pass-through audio to modifY sounds
represented by the digital data and/or to derive new digital
data representing new sounds in each of those pathways.
Also, in this way, different data transfer rates may be selected
by which digital data is clocked at different rates in each of the
pathways.
In support of feedback-based ANR, feedforward-based
ANR and/or pass-through audio, the coupling of the inputs
and outputs of the digital filters within the filter bank 550 to
the switch array 540 enables inputs and outputs of multiple
digital filters to be coupled through the switch array 540 to
create blocks of filters. As those skilled in the art will readily
recognize, by combining multiple lower-order digital filters
into a block of filters, multiple lower-order digital filters may
be caused to cooperate to implement higher order functions
without the use of a higher-order filter. Further, in implementations having a variety of types of digital filters, blocks of
filters may be created that employ a mix of filters to perform
a still greater variety of functions. By way of example, with
the depicted variety of filters within the filter bank 550, a filter
block (i.e., a block of filters) may be created having at least
one of the downsampling filters 552, multiple ones of the
biquad filters 554, at least one of the interpolating filters 556,
and at least one of the FIR filters 558.
In some implementations, at least some of the switching
devices of the switch array 540 may be implemented with
binary logic devices enabling the switch array 540, itself, to
be used to implement basic binary math operations to create
summing nodes where pathways along which different pieces
of digital data flow are brought together in a manner in which
those different pieces of digital data are arithmetically
summed, averaged, and/or otherwise combined. In such
implementations, the switch array 540 may be based on a
variant of dynamically programmable array oflogic devices.
Alternatively and/or additionally, a bank of binary logic
devices orotherform of arithmetic logic circuitry (not shown)
may also be incorporated into theANR circuit 2000 with the
inputs and outputs of those binary logic devices and/or other
form of arithmetic logic circuitry also being coupled to the
switch array 540.
In the operation of switching devices of the switch array
540 to adopt a topology by creating pathways for the flow of
data representing sounds, priority may be given to creating a
pathway for the flow of digital data associated with feedbackbased ANR that has as low a latency as possible through the

switching devices. Also, priority may be given in selecting
digital filters and VGAs that have as low a latency as possible
from among those available in the filter bank 550 and the
VGA bank 560, respectively. Further, coefficients and/or
other settings provided to digital filters of the filter bank 550
that are employed in the pathway for digital data associated
with feedback-based ANR may be adjusted in response to
whatever latencies are incurred from the switching devices of
the switch array 540 employed in defining the pathway. Such
measures may be taken in recognition ofthe higher sensitivity
of feedback-based ANR to the latencies of components
employed in performing the function of deriving and/or
acoustically outputting feedback anti-noise sounds. Although
such latencies are also of concern in feedforward-basedANR,
feedforward-based ANR is generally less sensitive to such
latencies than feedback -based ANR. As a result, a degree of
priority less than that given to feedback-based ANR, but
greater than that given to pass-through audio, may be given to
selecting digital filters and VGAs, and to creating a pathway
for the flow of digital data associated with feedfurward-based
ANR.
The processing device 510 is coupled to the switch array
540, as well as to both the storage 520 and the interface 530.
The processing device 510 may be any of a variety of types of
processing device, including and not limited to, a general
purpose central processing unit (CPU), a digital signal processor (DSP), a reduced instruction set computer (RISC)
processor, a microcontroller, or a sequencer. The storage 520
may be based on any of a variety of data storage technologies,
including and not limited to, dynamic random access memory
(DRAM), static random access memory (SRAM), ferromagnetic disc storage, optical disc storage, or any of a variety of
nonvolatile solid state storage technologies. Indeed, the storage 520 may incorporate both volatile and nonvolatile portions. Further, it will be recognized by those skilled in the art
that although the storage 520 is depicted and discussed as if it
were a single component, the storage 520 may be made up of
multiple components, possibly including a combination of
volatile and nonvolatile components. The interface 530 may
support the coupling of the ANR circuit 2000 to one or more
digital communications buses, including digital serial buses
by which the storage device 170 (not to be confused with the
storage 520) and/or other devices external to theANR circuit
2000 (e.g., other processing devices, or other ANR circuits)
may be coupled. Further, the interface 530 may provide one or
more general purpose input/output (GPIO) electrical connections and/or analog electrical connections to support the coupling of manually-operable controls, indicator lights or other
devices, such as a portion of the power source 180 providing
an indication of available power.
In some implementations, the processing device 510
accesses the storage 520 to read a sequence of instructions of
a loading routine 522, that when executed by the processing
device 510, causes the processing device 510 to operate the
interface 530 to access the storage device 170 to retrieve one
or both oftheANRroutine 525 and theANR settings 527, and
to store them in the storage 520. In other implementations,
one or both of theANR routine 525 and the ANR settings 527
are stored in a nonvolatile portion of the storage 520 such that
they need not be retrieved from the storage device 170, even
if power to the ANR circuit 2000 is lost.
Regardless of whether one or both of the ANR routine 525
and the ANR settings 527 are retrieved from the storage
device 170, or not, the processing device 510 accesses the
storage 520 to read a sequence of instructions of the ANR
routine 525. The processing device 510 then executes that
sequence of instructions, causing the processing device 510

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to configure the switching devices of the switch array 540 to
adopt a topology defining pathways for flows of digital data
representing sounds and/or to provide differing clock signals
to one or more digital filters and/or VGAs, as previously
detailed. In some implementations, the processing device 510
is caused to configure the switching devices in a manner
specified by a portion of the ANR settings 527, which the
processing device 510 is also caused to read from the storage
520. Further, the processing device 510 is caused to set filter
coefficients of various digital filters of the filter bank 550,
gain settings of various VGAs of the VGA bank 560, and/or
clock frequencies of the clock signal outputs of the clock bank
570 in a manner specified by a portion of the ANR settings
527.
In some implementations, the ANR settings 527 specify
multiple sets of filter coefficients, gain settings, clock frequencies and/or configurations of the switching devices of the
switch array 540, of which different sets are used in response
to different situations. In other implementations, execution of
sequences of instructions of the ANR routine 525 causes the
processing device 510 to derive different sets of filter coefficients, gain settings, clock frequencies and/or switching
device configurations in response to different situations. By
way of example, the processing device 510 may be caused to
operate the interface 530 to monitor a signal from the power
source 180 that is indicative of the power available from the
power source 180, and to dynamically switch between different sets of filter coefficients, gain settings, clock frequencies
and/or switching device configurations in response to
changes in the amount of available power.
By way of another example, the processing device 510 may
be caused to monitor characteristics ofsounds represented by
digital data involved in feedback-based ANR, feedforwardbasedANR and/or pass-through audio to determine whether
or not it is desirable to alter the degree feedback-based and/or
feedforward-based ANR provided. As will be familiar to
those skilled in the art, while providing a high degree ofANR
can be very desirable where there is considerable environmental noise to be attenuated, there can be other situations
where the provision of a high degree of ANR can actually
create a noisier or otherwise more unpleasant acoustic environment for a user of a personal ANR device than would the
provision ofless ANR. Therefore, the processing device 510
may be caused to alter the provision of ANR to adjust the
degree of attenuation and/or the range of frequencies of environmental noise attenuated by the ANR provided in response
to observed characteristics of one or more sounds. Further, as
will also be familiar to those skilled in the art, where a reduction in the degree of attenuation and/or the range of frequencies is desired, it may be possible to simplify the quantity
and/or type of filters used in implementing feedback-based
and/or feedforward-based ANR, and the processing device
510 may be caused to dynamically switch between different
sets of filter coefficients, gain settings, clock frequencies and/
or switching device configurations to perform such simplifying, with the added benefit of a reduction in power consumption.
The DAC 910 is provided with digital data from the switch
array 540 representing sounds to be acoustically output to an
ear of a user of the personal ANR device 1000, and converts
it to an analog signal representing those sounds. The audio
amplifier 960 receives this analog signal from the DAC 910,
and amplifies it sufficiently to drive the acoustic driver 190 to
effect the acoustic output of those sounds.
The compression controller 950 (if present) monitors the
sounds to be acoustically output for an indication of their
amplitude being too high, indications of impending instances

of clipping, actual instances of clipping, and/or other impending or actual instances of other audio artifacts. The compression controller 150 may either directly monitor digital data
provided to the DAC 910 or the analog signal output by the
audio amplifier 960 (through the ADC 955, if present). In
response to such an indication, the compression controller
950 may alter gain settings ofone or more ofthe analog VGAs
125, 135and145 (ifpresent); and/oroneormoreofthe VGAs
of the VGA bank 560 placed ina pathway associated with one
or more of the feedback-based ANR, feedforward-based
ANR and pass-through audio functions to adjust amplitude,
as will be explained in greater detail. Further, in some implementations, the compression controller 950 may also make
such an adjustment in response to receiving an external control signal. Such an external signal may be provided by
another component coupled to the ANR circuit 2000 to provide such an external control signal in response to detecting a
condition such as an exceptionally loud environmental noise
sound that may cause one or both of the feedback-based and
feedforward-basedANR functions to react unpredictably.
FIG. 3b depicts another possible internal architecture
2200b of the ANR circuit 2000 in which a processing device
accesses and executes stored machine-readable sequences of
instructions that cause the processing device to manipulate
digital data representing sounds in a manner that can be
dynamically configured during operation of the ANR circuit
2000. Such a use of a processing device enables pathways for
movement of digital data of a topology to be defined through
programming. More specifically, digital filters of varying
quantities and/or types are able to be defined and instantiated
in which each type of digital filter is based on a sequence of
instructions. In employing the internal architecture 2200b,
the ANR circuit 2000 incorporates the ADCs 210, 310 and
410; the processing device 510; the storage 520; the interface
530; a direct memory access (DMA) device 540; and the DAC
910. Various possible variations may further incorporate one
or more of the analog VGAs 125, 135 and 145; the ADC 955;
and/or the audio amplifier 960. The processing device 510 is
coupled directly or indirectly via one or more buses to the
storage 520; the interface 530; the DMA device 540; the
ADCs 210, 310 and 410; and the DAC 910 to at least enable
the processing device 510 to control their operation. The
processing device 510 may also be similarly coupled to one or
more of the analog VGAs 125, 135 and 145 (if present); and
to the ADC 955 (if present).
As in the internal architecture 2200a, the processing device
510 may be any of a variety oftypes of processing device, and
once again, the storage 520 may be based on any of a variety
of data storage technologies and may be made up of multiple
components. Further, the interface 530 may support the coupling of the ANR circuit 2000 to one or more digital communications buses, and may provide one or more general purpose input/output (GPIO) electrical connections and/or
analog electrical connections. The DMA device 540 may be
based on a secondary processing device, discrete digital logic,
a bus mastering sequencer, or any of a variety of other technologies.
Stored within the storage 520 are one or more of a loading
routine 522, an ANR routine 525, ANR settings 527, ANR
data 529, a downsampling filter routine 553, a biquad filter
routine 555, an interpolating filter routine 557, a FIR filter
routine 559, and a VGA routine 561. In some implementations, the processing device 510 accesses the storage 520 to
read a sequence ofinstructions ofthe loading routine 522, that
when executed by the processing device 510, causes the processing device 510 to operate the interface 530 to access the
storage device 170 to retrieve one or more of the ANRroutine

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525, the ANR settings 527, the downsampling filter routine
553, the biquad filter routine 555, the interpolating filter routine 557, the FIR routine 559 and the VGAroutine 561, and to
store them in the storage 520. In other implementations, one
or more of these are stored in a nonvolatile portion of the
storage 520 such that they need not be retrieved from the
storage device 170.
As was the case in the internal architecture 2200a, theADC
210 receives an analog signal from the feedback microphone
120, the ADC 310 receives an analog signal from the feedforward microphone 130, and the ADC 410 receives an analog signal from either the audio source 9400 or the communications microphone 140 (unless the use of one or more of
the ADCs 210, 310 and 410 is obviated through the direct
receipt of digital data).Again, one or more oftheADCs 210,
310 and 410 may receive their associated analog signals
through one or more of the analog VGAs 125, 135 and 145,
respectively. As was also the case in the internal architecture
2200a, the DAC 910 converts digital data representing sounds
to be acoustically output to an ear of a user of the personal
ANR device 1000 into an analog signal, and the audio amplifier 960 amplifies this signal sufficiently to drive the acoustic
driver 190 to effect the acoustic output of those sounds.
However, unlike the internal architecture 2200a where
digital data representing sounds were routed via an array of
switching devices, such digital data is stored in and retrieved
from the storage 520. In some implementations, the processing device 510 repeatedly accesses the ADCs 210, 310 and
410 to retrieve digital data associated with the analog signals
they receive for storage in the storage 520, and repeatedly
retrieves the digital data associated with the analog signal
output by the DAC 910 from the storage 520 and provides that
digital data to the DAC 910 to enable the creation of that
analog signal. In otherimplementations, the DMA device 540
(if present) transfers digital data among theADCs 210,310
and 410; the storage 520 and the DAC 910 independently of
the processing device 510. In still other implementations, the
ADCs 210,310 and410 and/ortheDAC 910 incorporate"bus
mastering" capabilities enabling each to write digital data to
and/or read digital data from the storage 520 independently of
the processing device 510. The ANR data 529 is made up of
the digital data retrieved from the ADCs 210, 310 and 410,
and the digital data provided to the DAC 910 by the processing device 510, the DMA device 540 and/or bus mastering
functionality.
The downsampling filter routine 553, the biquad filter routine 555, the interpolating filter routine 557 and the FIR filter
routine 559 are each made up of a sequence of instructions
that cause the processing device 510 to perform a combination of calculations that define a downsampling filter, a
biquad filter, an interpolating filter and a FIR filter, respectively. Further, among each of the different types of digital
filters may be variants of those digital filters that are optimized for different data transfer rates, including and not limited to, differing bit widths of coefficients or differing quantities of taps. Similarly, the VGA routine 561 is made up of a
sequence of instructions that cause the processing device 510
to perform a combination of calculations that define a VGA.
Although not specifically depicted, a summing node routine
may also be stored in the storage 520 made up of a sequence
of instructions that similarly defines a summing node.
The ANR routine 525 is made up of a sequence of instructions that cause the processing device 510 to create a signal
processing topology having pathways incorporating varying
quantities of the digital filters andVGAs defined by the downsampling filter routine 553, the biquad filter routine 555, the
interpolating filter routine 557, the FIR filter routine 559 and

the VGA routine 561 to support feedback-based ANR, feedfOrward-based ANR and/or pass-through audio. The ANR
routine 525 also causes the processing device 510 to perform
the calculations defining each ofthe various filters and VGAs
incorporated into that topology. Further, theANRroutine 525
either causes the processing device 510 to perform the moving of data among ADCs 210, 310 and 410, the storage 520
and the DAC 910, or causes the processing device 510 to
coordinate the performance of such moving of data either by
the DMA device 540 (if present) or by bus mastering operations performed by the ADCs 210, 310 and 410, and/or the
DAC910.
The ANR settings 527 is made up of data defining topology
characteristics (including selections of digital filters), filter
coefficients, gain settings, clock frequencies, data transfer
rates and/or data sizes. In some implementations, the topology characteristics may also define the characteristics of any
summing nodes to be incorporated into the topology. The
processing device 510 is caused by the ANR routine 525 to
employ such data taken from theANR settings 527 in creating
a signal processing topology (including selecting digital filters), setting the filter coefficients for each digital filter incorporated into the topology, and setting the gains for each VGA
incorporated into the topology. The processing device 510
may be further caused by theANR routine 525 to employ such
data from the ANR settings 527 in setting clock frequencies
and/or data transfer rates for theADCs 210, 310 and 410; for
the digital filters incorporated into the topology; for the VGAs
incorporated into the topology; and for the DAC 910.
In some implementations, the ANR settings 527 specify
multiple sets of topology characteristics, filter coefficients,
gain settings, clock frequencies and/or data transfer rates, of
which different sets are used in response to different situations. In other implementations, execution of sequences of
instructions of the ANR routine 525 causes the processing
device 510 to derive different sets of filter coefficients, gain
settings, clock frequencies and/or data transfer rates for a
given signal processing topology in different situations. By
way of example, the processing device 510 may be caused to
operate the interface 530 to monitor a signal from the power
source 180 that is indicative of the power available from the
power source 180, and to employ different sets of filter coefficients, gain settings, clock frequencies and/or data transfer
rates in response to changes in the amount of available power.
By way of another example, the processing device 510 may
be caused to alter the provision ofANR to adjust the degree of
ANR required in response to observed characteristics of one
or more sounds. Where a reduction in the degree of attenuation and/or the range of frequencies of noise sounds attenuated is possible and/or desired, it may be possible to simplify
the quantity and/or type of filters used in implementing feedback-based and/or feedforward-basedANR, and the processing device 510 may be caused to dynamically switch between
different sets of filter coefficients, gain settings, clock frequencies and/or data transfer rates to perform such simplifying, with the added benefit of a reduction in power consumption.
Therefore, in executing sequences of instructions of the
ANR routine 525, the processing device 510 is caused to
retrieve data from the ANR settings 527 in preparation for
adopting a signal processing topology defining the pathways
to be employed by the processing device 510 in providing
feedback-based ANR, feedforward-based ANR and passthrough audio. The processing device 510 is caused to instantiate multiple instances of digital filters, VGAs .and/or summing nodes, employing filter coefficients, gain settings and/or
other data from theANR settings 527. The processing device

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510 is then further caused to perform the calculations defining
each of those instances of digital filters, VGAs and summing
nodes; to move digital data among those instances of digital
filters, VGAs and summing nodes; and to at least coordinate
the moving of digital data among theADCs 210, 310 and 410,
the storage 520 and the DAC 910 in a manner that conforms
to the data retrieved from the ANR settings 527. At a subsequent time, the ANR routine 525 may cause the processing
device 510 to change the signal processing topology, a digital
filter, filter coefficients, gain settings, clock frequencies and/
or data transfer rates during operation of the personal ANR
device 1000. It is largely in this way that the digital circuitry
of the internal architecture 2200b is made dynamically configurable. Also, in this way, varying quantities and types of
digital filters and/or digital VGAs may be positioned at various points along a pathway of a topology defined for a flow of
digital data to modifY sounds represented by that digital data
and/or to derive new digital data representing new sounds, as
will be explained in greater detail.
In some implementations, the ANR routine 525 may cause
the processing device 510 to give priority to operating the
ADC 210 and performing the calculations of the digital filters, VGAs and/or summing nodes positioned along the pathway defined for the flow of digital data associated with feedback-based ANR. Such a measure may be taken in
recognition of the higher sensitivity offeedback-basedANR
to the latency between the detection of feedback reference
sounds and the acoustic output of feedback anti-noise sounds.
The processing device 510 may be further caused by the
ANR routine 525 to monitor the sounds to be acoustically
output for indications of the amplitude being too high, clipping, indications of clipping about to occur, and/or other
audio artifacts actually occurring or indications of being
about to occur. The processing device 510 may be caused to
either directly monitor digital data provided to the DAC 910
or the analog signal output by the audio amplifier 960
(through the ADC 955) for such indications. In response to
such an indication, the processing device 510 may be caused
to operate one or more of the analog VGAs 125, 135 and 145
to adjust at least one amplitude of an analog signal, and/or
may be caused to operate one or more of the VGAs based on
the VGA routine 561 and positioned within a pathway of a
topology to adjust the amplitude of at least one sound represented by digital data, as will be explained in greater detail.
FIGS. 4a through 4g depict some possible signal processing topologies that may be adopted by the ANR circuit 2000
of the personal ANR device 1000 of FIG. 1. As previously
discussed, some implementations of the personalANRdevice
1000 may employ a variant of the ANR circuit 2000 that is at
least partially programmable such that the ANR circuit 2000
is able to be dynamically configured to adopt different signal
processing topologies during operation of the ANR circuit
2000. Alternatively, other implementations of the personal
ANR device 1000 may incorporate a variant of the ANR
circuit 2000 that is substantially inalterably structured to
adopt one unchanging signal processing topology.
As previously discussed, separate ones of the ANR circuit
2000 are associated with each earpiece 100, and therefore,
implementations of the personal ANR device 1000 having a
pair of the earpieces 100 also incorporate a pair of the ANR
circuits 2000. However, as those skilled in the art will readily
recognize, other electronic components incorporated into the
personal ANR device 1000 in support of a pair of the ANR
circuits 2000, such as the power source 180, may not be
duplicated. For the sake of simplicity of discussion and under-

standing, signal processing topologies for only a single ANR
circuit 2000 are presented and discussed in relation to FIGS.
4a-g.
As also previously discussed, different implementations of
the personalANR device 1000 may provide only one of either
feedback-based ANR or feedforward-based ANR, or may
provide both. Further, different implementations may or may
not additionally provide pass-through audio. Therefore,
although signal processing topologies implementing all three
offeedback-basedANR, feedforward-basedANR and passthrough audio are depicted in FIGS. 4a-g, it is to be understood that variants of each of these signal processing topologies are possible in which only one or the other of these two
forms of ANR is provided, and/or in which pass-through
audio is not provided. In implementations in which the ANR
circuit 2000 is at least partially programmable, which of these
two forms of ANR are provided and/or whether or not both
forms of ANR are provided may be dynamically selectable
during operation oftheANR circuit 2000.
FIG. 4a depicts a possible signal processing topology
2500a for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500a, the ANR circuit 2000
incorporates at least the DAC 910, the compression controller
950, and the audio amplifier 960. Depending, in part on
whether one or both of feedback-based and feedforwardbased ANR are supported, the ANR circuit 2000 further
incorporates one or more of the ADCs 210, 310, 410 and/or
955; filter blocks 250, 350 and/or 450; and/or summing nodes
270 and/or 290.
Where the provision offeedback-basedANR is supported,
the ADC 210 receives an analog signal from the feedback
microphone 120 representing feedback reference sounds
detected by the feedback microphone 120. The ADC 210
digitizes the analog signal from the feedback microphone
120, and provides feedback reference data corresponding to
the analog signal output by the feedback microphone 120 to
the filter block 250. One or more digital filters within the filter
block 250 are employed to modifY the data from theADC 210
to derive feedback anti-noise data representing feedback antinoise sounds. The filter block 250 provides the feedback
anti-noise data to the VGA 280, possibly through the summing node 270 where feedforward-basedANR is also supported.
Where the provision of feedforward-based ANR is also
supported, the ADC 310 receives an analog signal from the
feedforwardmicrophone 130, digitizes it, and provides feedforward reference data corresponding to the analog signal
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
employed to modifY the feedforward reference data received
from the ADC 310 to derive feedforward anti-noise data
representing feedforward anti-noise sounds. The filter block
350 provides the feedforward anti-noise data to the VGA 280,
possibly through the summing node 270 where feedbackbased ANR is also supported.
At the VGA 280, the amplitude of one or both of the.
feedback and feedforward anti-noise sounds represented by
the data received by the VGA 280 (either through the summing node 270, or not) may be altered under the control ofthe
compression controller 950. The VGA 280 outputs its data
(with or without amplitude alteration) to the DAC 910, possibly through the summing nodes 290 where talk-through
audio is also supported.
In some implementations where pass-through audio is supported, the ADC 410 digitizes an analog signal representing
pass-through audio received from the audio source 9400, the

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communications microphone 140 or another source and provides the digitized result to the filter block 450. In other
implementations where pass-through audio is supported, the
audio source 9400, the communications microphone 140 or
another source provides digital data representing passthrough audio to the filter block 450 without need of analogto-digital conversion. One or more digital filters within the
filter block 450 are employed to modify the digital data representing the pass-through audio to derive a modified variant
of the pass-through audio data in which the pass-through
audio may be re-equalized and/or enhanced in other ways.
The filter block 450 provides the pass-through audio data to
the summing node 290 where the pass-through audio data is
combined with the data being provided by the VGA 280 to the
DAC910.
The analog signal output by the DAC 910 is provided to the
audio amplifier 960 to be amplified sufficiently to drive the
acoustic driver 190 to acoustically output one or more of
feedback anti-noise sounds, feedforward anti-noise sounds
and pass-through audio. The compression controller950 controls the gain ofthe VGA 280 to enable the amplitude of sound
represented by data output by one or both of the filter blocks
250 and 350 to be reduced in response to indications of
impending instances of clipping, actual occurrences of clipping and/or other undesirable audio artifacts being detected
by the compression controller 950. The compression controller 950 may either monitor the data being provided to the
DAC 910 by the summing node 290, or may monitor the
analog signal output of the audio amplifier 960 through the
ADC955.
As further depicted in FIG. 4a, the signal processing topology 2500a defines multiple pathways along which digital
data associated with feedback-based ANR, feedforwardbased ANR and pass-through audio flow. Where feedbackbased ANR is supported, the flow of feedback reference data
and feedback anti-noise data among at least theADC 210, the
filter block 250, the VGA 280 and the DAC 910 defines a
feedback-basedANR pathway 200. Similarly, where feedforward-based ANR is supported, the flow of feedforward reference data and feedforward anti-noise data among at least
theADC 310, the filter block350, the VGA 280 and the DAC
910 defines a feedforward-basedANR pathway 300. Further,
where pass-through audio is supported, the flow of passthrough audio data and modified pass-through audio data
among at least theADC 410, the filter block450, the summing
node 290 and the DAC 910 defines a pass-through audio
pathway 400. Where both feedback-based and feedforwardbased ANR are supported, the pathways 200 and 300 both
further incorporate the summing node 270. Further, where
pass-through audio is also supported, the pathways 200 and/
or 300 incorporate the summing node 290.
In some implementations, digital data representing sounds
may be clocked through all of the pathways 200, 300 and 400
that are present at the same data transfer rate. Thus, where the
pathways 200 and 300 are combined at the summing node
270, and/or where the pathway 400 is combined with one or
both of the pathways 200 and 300 at the summing node 400,
all digital data is clocked through at a common data transfer
rate, and that common data transfer rate may be set by a
common synchronous data transfer clock. However, as is
known to those skilled in the art and as previously discussed,
the feedforward-based ANR and pass-through audio functions are less sensitive to latencies than the feedback-based
ANR function. Further, the feedforward-based ANR and
pass-through audio functions are more easily implemented
with sufficiently high quality of sound with lower data sampling rates than the feedback-basedANRfunction. Therefore,

in other implementations, portions of the pathways 300 and/
or 400 may be operated at slower data transfer rates than the
pathway 200. Preferably, the data transfer rates of each of the
pathways 200, 300 and400 are selected such that the pathway
200 operates with a data transfer rate that is an integer multiple of the data transfer rates selected for the portions of the
pathways 300 and/or 400 that are operated at slower data
transfer rates.
By way of example in an implementation in which all three
of the pathways 200, 300 and 400 are present, the pathway
200 is operated at a data transfer rate selected to provide
sufficiently low latency to enable sufficiently high quality of
feedback-basedANR that the provision ofANR is not unduly
compromised (e.g., by having anti-noise sounds out-of-phase
with the noise sounds they are meant to attenuate, or instances
of negative noise reduction such that more noise is actually
being generated than attenuated, etc.), and/or sufficiently
high quality of sound in the provision of at least the feedback
anti-noise sounds. Meanwhile, the portion ofthe pathway 300
from the ADC 310 to the summing node 270 and the portion
of the pathway 400 from theADC 410 to the summing node
290 are both operated at lower data transfer rates (either the
same lower data transfer rates or different ones) that still also
enable sufficiently high quality of feedforward-basedANR in
the pathway 300, and sufficiently high quality of sound in the
provision of the feedforward anti-noise through the pathway
300 and/or pass-through audio through the pathway 400.
In recognition of the likelihood that the pass-through audio
function may be even more tolerant of a greater latency and a
lower sampling rate than the feedforward-based ANR function, the data transfer rate employed in that portion of the
pathway 400 may be still lower than the data transfer rate of
that portion of the pathway 300. To support such differences
in transfer rates in one variation, one or both of the summing
nodes 270 and 290 may incorporate sample-and-hold, buffering or other appropriate functionality to enable the combining of digital data received by the summing nodes 270 and
290 at different data transfer rates. This may entail the provision of two different data transfer clocks to each of the summing nodes 270 and 290. Alternatively, to support such differences in transfer rates in another variation, one or both of
the filter blocks 350 and 450 may incorporate an upsampling
capability (perhaps through the inclusion of an interpolating
filter or other variety of filter incorporating an upsampling
capability) to increase the data transfer rate at which the filter
blocks 350 and 450 provide digital data to the summing nodes
270 and 290, respectively, to match the data transfer rate at
which the filter block 250 provides digital data to the summing node 270, and subsequently, to the summing node 290.
It may be that in some implementations, multiple power
modes may be supported in which the data transfer rates ofthe
pathways 300 and 400 are dynamically altered in response to
the availability of power from the power source 180 and/or in
response to changing ANR requirements. More specifically,
the data transfer rates of one or both of the pathway 300 and
400 up to the points where they are combined with the pathway 200 may be reduced in response to an indication of
diminishing power being available from the power supply
180 and/orin response to the processing device510 detecting
characteristics in sounds represented by digital data indicating that the degree of attenuation and/or range of frequencies
of noise sounds attenuated by the ANR provided can be
reduced In making determinations of whether or not such
reductions in data transfer rates are possible, the processing
device 510 may be caused to evaluate the effects of such
reductions in data transfer rates on quality of sound through

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one or more of the pathways 200, 300 and 400, and/or the
quality of feedback-based and/or feed-forward based ANR
provided.
FIG. 4b depicts a possible signal processing topology
2500b for which the ANR circuit 2000 may be structured
and/ or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500b, the ANR circuit 2000
incorporates at least the DAC 910, the audio amplifier 960,
theADC 210, a pairofsummingnodes 230 and270, and a pair
of filter blocks 250 and 450. The ANR circuit 2000 may
further incorporate one or more of the ADC 410, the ADC
310, a filter block 350 and a summing node 370.
The ADC 210 receives and digitizes an analog signal from
the feedback microphone 120 representing feedback reference sounds detected by the feedback microphone 120, and
provides corresponding feedback reference data to the summing node 230. In some implementations, theADC 410 digitizes an analog signal representing pass-through audio
received from the audio source 9400, the communications
microphone 140 or another source and provides the digitized
result to the filter block 450. In other implementations, the
audio source 9400, the communications microphone 140 or
another source provides digital data representing passthrough audio to the filter block 450 without need of analogto-digital conversion. One or more digital filters within the
filter block 450 are employed to modify the digital data representing the pass-through audio to derive a modified variant
of the pass-through audio data in which the pass-through
audio may be re-equalized and/or enhanced in other ways.
One or more digital filters within the filter block 450 also
function as a crossover that divides the modified pass-through
audio data into higher and lower frequency sounds, with data
representing the higher frequency sounds being output to the
summing node 270, and data representing the lower frequency sounds being output to the summing node 230. In
various implementations, the crossover frequency employed
in the filter block 450 is dynamically selectable during operation of the ANR circuit 2000, and may be selected to effectively disable the crossover function to cause data representing all frequencies of the modified pass-through audio to be
output to either of the summing nodes 230 or270. In this way,
the point at which the modified pass-through audio data is
combined with data for the feedbackANR function within the
signal processing topology 2500a can be made selectable.
As just discussed, feedback reference data from the ADC
210 may be combined with data from the filterblock450 for
the pass-through audio function (either the lower frequency
sounds, or all of the modified pass-through audio) at the
summing node 230. The summing node 230 outputs the possibly combined data to the filter block 250. One or more
digital filters within the filter block 250 are employed to
modify the data from summing node 230 to derive modified
data representing at least feedback anti-noise sounds and
possibly further-modified pass-through audio sounds. The
filter block 250 provides the modified data to the summing
node 270. The summing node 270 combines the data from the
filter block 450 that possibly represents higher frequency
sounds of the modified pass-through audio with the modified
data from the filter block 250, and provides the result to the
DAC 910 to create an analog signal. The provision of data by
the filter block 450 to the summing node 270 may be through
the summing node 370 where the provision of feedforwardbasedANR is also supported.
Where the crossover frequency employed in the filter block
450 is dynamically selectable, various characteristics of the
filters making up the filter block 450 may also be dynamically
configurable. By way of example, the number and/or type of

digital filters making up the filter block 450 may be dynamically alterable, as well as the coefficients for each of those
digital filters. Such dynamic configurability may be deemed
desirable to correctly accommodate changes among having
no data from the filter block 450 being combined with feedback reference data from the ADC 210, having data from the
filter block 450 representing lower frequency sounds being
combined with feedback reference data from the ADC 210,
and having data representing all of the modified pass-through
audio from the filter block 450 being combined with feedback
reference data from theADC 210.
Where the provision of feedforward-based ANR is also
supported, the ADC 310 receives an analog signal from the
feedforward microphone 130, digitizes it, and provides feedforward reference data corresponding to the analog signal
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
employed to modify the feedforward reference data received
from the ADC 310 to derive feedforward anti-noise data
representing feedforward anti-noise sounds. The filter block
350 provides the feedforward anti-noise data to the summing
node 370 where the feedforward anti-noise data is possibly
combined with data that may be provided by the filter block
450 (either the higher frequency sounds, or all of the modified
pass-through audio).
The analog signal output by the DAC 910 is provided to the
audio amplifier 960 to be amplified sufficiently to drive the
acoustic driver 190 to acoustically output one or more of
feedback anti-noise sounds, feedforward anti-noise sounds
and pass-through audio.
As further depicted in FIG. 4b, the signal processing topology 2500b defines its own variations of the pathways 200, 300
and 400 along which digital data associated with feedbackbased ANR, feedforward-based ANR and pass-through
audio, respectively, flow. In a manner not unlike the pathway
200 of the signal processing topology 2500a, the flow of
feedback reference data and feedback anti-noise data among
theADC210, thesummingnodes230 and270, the filter block
250 and the DAC 910 defines the feedback-basedANR pathway 200 of the signal processing topology 2500b. Where
feedforward-based ANR is supported, in a manner not unlike
the pathway 300 of the signal processing topology 2500a, the
flow of feedforward reference data and feedforward antinoise data among the ADC 310, the filter block 350, the
summing nodes 270 and 370, and the DAC 910 defines the
feedforward-basedANR pathway 300 of the signal processing topology 2500b. However, in a manner very much unlike
the pathway 400 of the signal processing topology 2500a, the
ability ofthe filter block450 ofthe signal processing topology
2500b to split the modified pass-through audio data into
higher frequency and lower frequency sounds results in the
pathway 400 of the signal processing topology 2500b being
partially split. More specifically, the flow of digital data from
the ADC 410 to the filter block 450 is split at the filter block
450. One split portion of the pathway 400 continues to the
summing node 230, where it is combined with the pathway
200, before continuing through the filter block 250 and the
summing node 270, and ending at the DAC 910. The other
split portion of the pathway 400 continues to the summing
node 370 (if present), where it is combined with the pathway
300 (ifpresent), before continuing through the summing node
270 and ending at the DAC 910.
Also not unlike the pathways 200, 300 and400 ofthe signal
processing topology 2500a, the pathways 200, 300 and400 of
the signal processing topology 2500b may be operated with
different data transfer rates. However, differences in data
transfer rates between the pathway 400 and both of the path-

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ways 200 and 300 would have to be addressed. Sample-andhold, buffering or other functionality may be incorporated
into each of the summing nodes 230, 270 and/or 370. Alternatively and/or additionally, the filter block 350 may incorporate interpolation or otherupsampling capability in providing digital data to the summing node 370, and/or the filter
block 450 may incorporate a similar capability in providing
digital data to each of the summing nodes 230 and 370 (or
270, if the pathway 300 is not present).
FIG. 4c depicts another possible signal processing topology 2500c for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500c, the ANR circuit 2000
incorporates at least the DAC 910, the audio amplifier 960,
theADC210, thesummingnode230, thefilterblocks250and
450, the VGA 280, another summing node 290, and the compressor 950. The ANR circuit 2000 may further incorporate
one or more of the ADC 410, the ADC 310, the filter block
350, the summing node 270, and the ADC 955. The signal
processing topologies 2500b and 2500c are similar in numerous ways. However, a substantial difference between the signal processing topologies 2500b and 2500c is the addition of
the compressor 950 in the signal processing topology 2500c
to enable the amplitudes of the sounds represented by data
output by both of the filter blocks 250 and 350 to be reduced
in response to the compressor 950 detecting actual instances
or indications of impending instances of clipping and/or other
undesirable audio artifacts.
The filter block 250 provides its modified data to the VGA
280 where the amplitude ofthe sounds represented by the data
provided to the VGA 280 may be altered under the control of
the compressioncontroller950. The VGA280 outputs its data
(with or without amplitude alteration) to the summing node
290, where it may be combined with data that may be output
by the filter block 450 (perhaps the higher frequency sounds
of the modified pass-through audio, or perhaps the entirety of
the modified pass-through audio). In turn, the summing node
290 provides its output data to the DAC 910. Where the
provision of feedforward-based ANR is also supported, the
data output by the filter block 250 to the VGA 280 is routed
through the summing node 270, where it is combined with the
data output by the filter block 350 representing feedforward
anti-noise sounds, and this combined data is provided to the
VGA280.
FIG. 4d depicts another possible signal processing topology 2500d for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500d, the ANR circuit 2000
incorporates at least the DAC 910, the compression controller
950, the audio amplifier 960, the ADC 210, the summing
nodes 230 and 290, the filter blocks 250 and 450, the VGA
280, and still other VGAs 445, 455 and 460. The ANR circuit
2000 may further incorporate one or more of the ADCs 310
and/or 410, the filter block 350, the summing node 270, the
ADC 955, and still another VGA 3 60. The signal processing
topologies 2500c and 2500d are similar in numerous ways.
However, a substantial difference between the signal processing topologies 2500c and 2500d is the addition of the ability
to direct the provision of the higher frequency sounds of the
modified pass-through audio to be combined with other audio
at either or both of two different locations within the signal
processing topology 2500d
One or more digital filters within the filter block 450 are
employed to modify the digital data representing the passthrough audio to derive a modified variant of the pass-through
audio data and to function as a crossover that divides the
modified pass-through audio data into higher and lower fre-

quency sounds. Data representing the lower frequency
sounds are output to the summing node 230 through the VGA
445. Data representing the higher frequency sounds are output both to the summing node 230 through the VGA 455 and
to the DAC 910 through the VGA 460. The VGAs 445, 455
and 460 are operable both to control the amplitudes of the
lower frequency and higher frequency sounds represented by
the data output by the filter block 450, and to selectively direct
the flow of the data representing the higher frequency sounds.
However, as has been previously discussed, the crossover
functionality of the filter block 450 may be employed to
selectively route the entirety of the modified pass-through
audio to one or the other of the summing node 230 and the
DAC910.
Where the provision of feedforward-based ANR is also
supported, the possible provision of higher frequency sounds
(or perhaps the entirety of the modified pass-through audio)
by the filter block 450 through the VGA 460 and to the DAC
910 may be through the summing node 290. The filter block
350 provides the feedforward anti-noise data to the summing
node 270 through the VGA 360.
FIG. 4e depicts another possible signal processing topology 2500e for which theANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500e, the ANR circuit 2000
incorporates at least the DAC 910; the audio amplifier 960;
theADCs 210 and310; the summing nodes 230,270 and370;
the filter blocks 250, 350 and 450; the compressor 950; and a
pair ofVGAs 240 and 340. TheANR circuit 2000 may further
incorporate one or both of the ADCs 410 and 955. The signal
processing topologies 2500b, 2500c and 2500e are similar in
numerous ways. The manner in which the data output by each
of the filter blocks 250, 350 and 450 are combined in the
signal processing topology 2500e is substantially similar to
that of the signal processing topology 2500b. Also, like the
signal processing topology 2500c, the signal processing
topology 2500e incorporates the compression controller 950.
However, a substantial difference between the signal processing topologies 2500c and 2500e is the replacement of the
single VGA 280 in the signal processing topology 2500c for
the separately controllable VGAs 240 and 340 in the signal
processing topology 2500e.
The summing node 230 provides data representing feedback reference sounds possibly combined with data that may
be output by the filter block 450 (perhaps the lower frequency
sounds of the modified pass-through audio, or perhaps the
entirety of the modified pass-through audio) to the filter block
250 through the VGA 240, and the ADC 310 provides data
representing feedforward reference sounds to the filter block
350 through the VGA 340. The data output by the filter block
350 is combined with data that may be output by the filter
block 450 (perhaps the higher frequency sounds of the modified pass-through audio, or perhaps the entirety of the modified pass-through audio) at the summing node370. In turn, the
sUlllmingnode 370 provides its data to the sUlllming node 270
to be combined with data output by the filter block 250. The
summing node 270, in turn, provides its combined data to the
DAC910.
The compression controller 950 controls the gains of the
VGAs 240 and 340, to enable the amplitude of the sounds
represented by data output by the summing node 230 and the
ADC 310, respectively, to be reduced in response to actual
instances or indications of upcoming instances of clipping
and/or other undesirable audio artifacts being detected by the
compression controller 950. The gains of the VGAs 240 and
340 may be controlled in a coordinated manner, or may be
controlled entirely independently of each other.

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and 270. Thus, where the feedforward anti-noise data is comFIG. 4fdepicts another possible signal processing topolbined with data related to feedback ANR within the signal
ogy 2500/for which theANR circuit 2000 may be structured
processing topology 2500g is made selectable.
and/or programmed Where theANR circuit 2000 adopts the
Therefore, depending on the gains selected for the VGAs
signal processing topology 2500/, the ANR circuit 2000
incorporates at least the DAC 910; the audio amplifier 960; 5 355 and 360, the feedforward anti-noise data from the filter
theADCs 210 and310; the summing nodes 230,270 and370;
block 350 may be combined with the feedback reference data
the filter blocks 250, 350 and 450; the compressor 950; and
from the ADC 210 at the summing node 230, or may be
the VGAs 125 and 135. The ANR circuit 2000 may further
combined with feedback anti-noise data derived by the filter
block 250 from the feedback reference data at the summing
incorporate one or both of the ADCs 410 and 955. The signal
processing topologies 2500e and 2500/are similar in numer- 1o node 270. Ifthe feedforward anti-noise data is combined with
ous ways. However, a substantial difference between the sigthe feedback reference data at the summing node 230, then
the filter block 250 derives data representing a combination of
nal processing topologies 2500e and 2500/is the replacement
feedback anti -noise sounds and further-modified feedforward
of the pair of VGAs 240 and 340 in the signal processing
anti-noise sounds, and this data is provided to the VGA 280
topology 2500e for the VGAs 125 and 135 in the signal
15 throughthesummingnode270atwhichnocombiningofdata
processing topology 2500/
occurs. Alternatively, if the feedforward anti-noise data is
The VGAs 125 and 135 positioned at the analog inputs to
combined with the feedback anti-noise data at the summing
the ADCs 210 and 310, respectively, are analog VGAs, unlike
node 270, then the feedback anti-noise data will have been
the VGAs 240 and 340 of the signal processing topology
derived by the filter block 250 from the feedback reference
2500e. This enables the compression controller 950 to
respond to actual occurrences and/or indications of soon-to- 20 data received through the summing node 230 at which no
combining of data occurs, and the data resulting from the
occur instances of clipping and/or other audio artifacts in
driving the acoustic driver 190 by reducing the amplitude of
combining at the summing node 270 is provided to the VGA
one or both of the analog signals representing feedback and
280. With or without an alteration in amplitude, the VGA 280
feedforwardreference sounds. This may be deemed desirable
provides whichever form of combined data is received from
where it is possible for the analog signals provided to the 25 the summing node 270 to the DAC 910 to create an analog
signal. This provision of this combined data by the VGA 280
ADCs 210 and 310 to be at too great an amplitude such that
may be through the summing node 290 where the provision of
clipping at the point of driving the acoustic driver 190 might
pass-through audio is also supported.
be more readily caused to occur. The provision of the ability
Where the provision of pass-through audio is supported,
to reduce the amplitude of these analog signals (and perhaps
also including the analog signal provided to the ADC 410 via 30 the audio source 9400 may provide an analog signal representing pass-through audio to be acoustically output to a user,
the VGA 145 depicted elsewhere) may be deemed desirable
and the ADC 410 digitizes the analog signal and provides
to enable balancing of amplitudes between these analog sigpass-through audio data corresponding to the analog signal to
nals, and/or to limit the numeric values of the digital data
the filter block 450. Alternatively, where the audio source
produced by one or more of the ADCs 210, 310 and 410 to
lesser magnitudes to reduce storage and/or transmission 35 9400 provides digital data representing pass-through audio,
such digital data may be provided directly to the filter block
bandwidth requirements.
450. One or more digital filters within the filter block 450 may
FIG. 4g depicts another possible signal processing topolbe employed to modify the digital data representing the passogy 2500g for which the ANR circuit 2000 may be prothrough audio to derive a modified variant ofthe pass-through
grammed or otherwise structured. Where the ANR circuit
2000 adopts the signal processing topology 2500g, the ANR 40 audio data that may be re-equalized and/or enhanced in other
ways. The filter block 450 provides the modified passcircuit 2000 incorporates at least the compression controller
throughaudio data to the VGA 460, andeitherwithorwithout
950, the DAC 910, the audio amplifier960, theADCs 210 and
altering the amplitude of the pass-through audio sounds rep310, a pairofVGAs 220 and320, the summing nodes 230and
resented by the modified pass-through audio data, the VGA
270, the filter blocks 250 and 350, another pair ofVGAs 355
and 3 60, and the VGA 280. TheANR circuit 2000 may further 45 460 provides the modified pass-through audio data to the
DAC 910 through the summing node 290.
incorporate one or more of the ADC 410, the filter block 450,
The compression controller 950 controls the gain of the
still another VGA 460, the summing node 290, and the ADC
VGA280toenabletheamplitudeofwhatevercombinedform
955.
of feedback and feedforward anti-noise sounds are received
TheADC 210 receives an analog signal from the feedback
microphone 120 and digitizes it, before providing corre- 50 by the VGA 280 to be reduced under the control of the
compression controller 950 in response to actual occurrences
sponding feedback reference data to the VGA 220. The VGA
and/or indications of impending instances of clipping and/or
220 outputs the feedback reference data, possibly after modiother audio artifacts.
fying its amplitude, to the summing node 230. Similarly, the
FIGS. 5a through 5e depict some possible filter block
ADC 310 receives an analog signal from the feedforward
microphone 130 and digitizes it, before providing corre- 55 topologies that may be employed in creating one or more
blocks of filters (such as filter blocks 250, 350 and 450) within
sponding feedforward reference data to the VGA 320. The
signal processing topologies adopted by the ANR circuit
VGA 320 outputs the feedforward reference data, possibly
2000 (such as the signal processing topologies 2500a-g). It
after modifying its amplitude, to the filter block 350. One or
should be noted that the designation of a multitude of digital
more digital filters within the filter block 350 are employed to
modify the feedforward reference data to derive feedforward 60 filters as a "filter block" is an arbitrary construct meant to
simplify the earlier presentation of signal processing topoloanti-noise data representing feedforward anti-noise sounds,
gies. In truth, the selection and positioning of one or more
and the filter block 350 provides the feedforward anti-noise
digital filters at any point along any of the pathways (such as
data to both of the VGAs 355 and 360. In various implementhe pathways 200, 300 and 400) of any signal processing
tations, the gains of the VGAs 355 and 360 are dynamically
selectable and can be operated in a coordinated manner like a 65 topology may be accomplished in a manner identical to the
selection and positioning of VGAs and summing nodes.
three-way switch to enable the feedforward anti-noise data to
Therefore, it is entirely possible for various digital filters to be
be selectively provided to either of the summing nodes 230

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positioned along a pathway for the movement of data in a
manner in which those digital filters are interspersed among
VGAs and/or summing nodes such that no distinguishable
block of filters is created. Or, as will be illustrated, it is
entirely possible for a filter block to incorporate a summing
node or other component as part of the manner in which the
filters of a filter block are coupled as part of the filter block
topology of a filter block.
However, as previously discussed, multiple lower-order
digital filters may be combined in various ways to perform the
equivalent function of one or more higher-order digital filters.
Thus, although the creation of distinct filter blocks is not
necessary in defining a pathway having multiple digital fi1ters, it can be desirable in numerous situations. Further, the
creation of a block of filters at a single point along a pathway
can more easily enable alterations in the characteristics of
filtering performed in that pathway. By way of example,
multiple lower-order digital filters connected with no other
components interposed between them can be dynamically
configured to cooperate to perform any of a variety ofhigherorder filter functions by simply changing their coefficients
and/or changing the manner in which they are interconnected.
Also, in some implementations, such close interconnection of
digital filters may ease the task of dynamically configuring a
pathway to add or remove digital filters with a minimum of
changes to the interconnections that define that pathway.
It should be noted that the selections of types of fi1ters,
quantities offi1ters, interconnections of filters and fi1ter block
topologies depictedineachofFIGS. SathroughSearemeant
to serve as examples to facilitate understanding, and should
not be taken as limiting the scope of what is described or the
scope of what is claimed herein.
FIG. Sa depicts a possible filter block topology 3SOOa for
which the ANR circuit 2000 may be structured and/or programmed to define a filter block, such as one of the filter
blocks 2SO, 3SO and 4SO. The filter block topology 3SOOa is
made up of a serial chain of digital filters with a downsampling fi1ter 6S2 at its input; biquad filters 6S4, 6SS and 6S6;
and a FIR filter 6S8 at its output.
As more explicitly depicted in FIG. Sa, in some implementations, the ANR circuit 2000 employs the internal architecture 2200a such that the ANR circuit 2000 incorporates the
filter bank SSO incorporating multitudes of the downsampling
filters SS2, the biquad filters SS4, and the FIR fi1ters SS8. One
or more of each of the downsampling fi1ters SS2, biquad filters
SS4 and FIR filters SS8 may be interconnected in any of a
number of ways via the switch array S40, including in a way
that defines the filter block topology 3SOOa. More specifically, the downs amp ling filter 6S2 is one ofthe downsampling
filters SS2; the biquad filters 6S4, 6SS and 6S6 are each one of
the biquad filters SS4; and the FIR filter 6S8 is one of the FIR
filters SS8.
Alternatively, and as also more explicitly depicted in FIG.
Sa, in other implementations, the ANR circuit 2000 employs
the internal architecture 2200b such that the ANR circuit
2000 incorporates a storage S20 in which is stored the downsampling fi1ter routine SS3, the biquad filter routine SSS and
the FIR filter routine SS9. Varying quantities of downsampling, biquad and/or FIR fi1ters may be instantiated within
available storage locations of the storage S20 with any of a
variety of interconnections defined between them, including
quantities of fi1ters and interconnections that define the fi1ter
block topology 3SOOa. More specifically, the downsampling
filter 6S2 is an instance of the downsampling filter routine
SS3; the biquad filters 6S4, 6SS and 6S6 are each instances of
the biquad filter routine SSS; and the FIR filter 6S8 is an
instance of the FIR filter routine SS9.

As previously discussed, power conservation and/or other
benefits may be realized by employing different data transfer
rates along different pathways of digital data representing
sounds in a signal processing topology. In support of converting between different data transfer rates, including where one
pathway operating at one data transfer rate is coupled to
another pathway operating at another data transfer rate, different data transfer clocks may be provided to different ones
of the digital filters within a filter block, and/or one or more
digital filters within a filter block may be provided with multiple data transfer clocks.
By way of example, FIG. Sa depicts a possible combination of different data transfer rates that may be employed
within the filter block topology 3SOOa to support digital data
being received at one data transfer rate, digital data being
transferred among these digital filters at another data transfer
rate, and digital data being output at still another data transfer
rate. More specifically, the downsampling filter 6S2 receives
digital data representing a sound at a data transfer rate 672,
and at least downsamples that digital data to a lower data
transfer rate 67S. The lower data transfer rate 67S is employed
in transferring digital data among the downsampling fi1ter
6S2, the biquad filters 6S4-6S6, and the FIR fi1ter 6S8. The
FIR filter 6S8 at least upsamples the digital data that it
receives from the lower data transfer rate 67S to a higher data
transfer rate 678 as that digital data is output by the fi1ter block
to which the digital filters in the filter block topology 3SOOa
belong. Many other possible examples of the use of more than
one data transfer rate within a fi1ter block and the possible
corresponding need to employ multiple data transfer clocks
within a filter block will be clear to those slG!led in the art.
FIG. Sb depicts a possible fi1ter block topology 3SOOb that
is substantially similar to the filter block topology 3SOOa, but
in which the FIR filter 6S8 of the filter block topology 3SOOa
has been replaced with an interpolating filter 6S7. Where the
internal architecture 2200a is employed, such a change from
the filter block topology 3SOOa to the filter block topology
3SOOb entails at least altering the configuration of the switch
array S40 to exchange one of the FIR filters SS8 with one of
the interpolating filters SS6. Where the internal architecture
2200b is employed, such a change entails at least replacing
the instantiation of the FIR fi1ter routine SS9 that provides the
FIR filter 6S8 with an instantiation of the interpolating filter
routine SS7 to provide the interpolating filter 6S7
FIG. Sc depicts a possible filter block topology 3SOOc that
is made up of the same digital fi1ters as the filter block topology 3SOOb, but in which the interconnections between these
digital filters have been reconfigured into a branching topology to provide two outputs, whereas the filter block topology
3SOOb had only one. Where the intemal architecture 2200a is
employed, such a change from the fi1ter block topology 3SOOb
to the filter block topology 3SOOc entails at least altering the
configuration of the switch array S40 to disconnect the input
to the biquad filter 6S6 from the output of the biquad fi1ter
6SS, and to connect that input to the output of the downsampling filter 6S2, instead. Where the internal architecture
2200b is employed, such a change entails at least altering the.
instantiation of biquad filter routine SSS that provides the
biquad filter 6S6 to receive its input from the instantiation of
the downsampling filter routine SS3 that provides the downsampling filter 6S2. The filter block topology 3SOOc may be
employed where it is desired that a filter block be capable of
providing two different outputs in which data representing
audio provided at the input is altered in different ways to
create two different modified versions of that data, such as in
the case of the filter block 4SO in each of the signal processing
topologies 2SOObj.

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FIG. Sd depicts another possible filter block topology
3500d that is substantially similar to the filter block topology
3500a, but in which the biquad filters 655 and 656 have been
removed to shorten the chain of digital filters from the quantity of five in the filter block topology 3500a to a quantity of
three.
FIG. Se depicts another possible filter block topology
3500e that is made up of the same digital filters as the filter
block topology 3500b, but in which the interconnections
between these digital filters have been reconfigured to put the
biquad filters 654, 655 and 656 in a parallel configuration,
whereas these same filters were ina serial chain configuration
in the filter block topology 3500b. As depicted, the output of
the downsampling filter 652 is coupled to the inputs of all
three of the biquadfilters 654,655 and656, and the outputs of
all three of these biquad filters are coupled to the input of the
interpolating filter 657 through an additionally incorporated
summing node 659.
Taken together, the FIGS. Sa through 5e depict the manner
in which a given filter block topology of a filter block is
dynamically configurableto so as to allow the types of filters,
quantities of filters and/or interconnections of digital filters to
be altered during the operation of a filter block. However, as
those skilled in the art will readily recognize, such changes in
types, quantities and interconnections of digital filters are
likely to require corresponding changes in filter coefficients
and/or other settings to be made to achieve the higher-order
filter function sought to be achieved with such changes. As
will be discussed in greater detail, to avoid or at least mitigate
the creation of audible distortions or other undesired audio
artifacts arising from making such changes during the operation of the personal ANR device, such changes in interconnections, quantities of components (including digital filters),
types of components, filter coefficients and/or VGA gain
values are ideally buffered so as to enable their being made in
a manner coordinated in time with one or more data transfer
rates.
The dynamic configurability of both of the internal architectures 2200a and 2200b, as exemplified throughout the
preceding discussion of dynamically configurable signal processing topologies and dynamically configurable filter block
topologies, enables numerous approaches to conserving
power and to reducing audible artifacts caused by the introduction of microphone self noise, quantization errors and
other influences arising from components employed in the
personal ANR device 1000. Indeed, there can be a synergy
between achieving both goals, since at least some measures
taken to reduce audible artifacts generated by the components
of the personal ANR device 1000 can also result in reductions
in power consumption. Reductions in power consumption
can be of considerable importance given that the personal
ANR device 1000 is preferably powered from a battery or
other portable source of electric power that is likely to be
somewhat limited in ability to provide electric power.
In either of the internal architectures 2200a and 2200b, the
processing device 510 may be caused by execution of a
sequence of instructions of the ANR routine 525 to monitor
the availability of power from the power source 180. Alternatively and/or additionally, the processing device 510 may
be caused to monitor characteristics of one or more sounds
(e.g., feedback reference and/or anti-noise sounds, feedforward reference and/or anti-noise sounds, and/or pass-through
audio sounds) and alter the degree of ANR provided in
response to the characteristics observed. As those familiar
with ANR will readily recognize, it is often the case that
providing an increased degree of ANR often requires the
implementation of a more complex transfer function, which

often requires a greater number of filters and/or more complex types of filters to implement, and this in turn, often leads
to greater power consumption. Analogously, a lesser degree
ofANR often requires the implementation of a simpler transferfunction, which often requires fewer and/or simpler filters,
which in turn, often leads to less power consumption.
Further, there can arise situations, such as an environment
with relatively low environmental noise levels or with environmental noise sounds occurring within a relatively narrow
range of frequencies, where the provision of a greater degree
ofANR can actually result in the components used in providing the ANR generating noise sounds greater than the attenuated environmental noise sounds. Still further, and as will be
familiar to those skilled in the art of feedback-based ANR,
under some circumstances, providing a considerable degree
offeedback-basedANR can lead to instability as undesirable
audible feedback noises are produced.
In response to either an indication of diminishing availability of electric power or an indication that a lesser degree of
ANR is needed (oris possibly more desirable), the processing
device 510 may disable one or more functions (including one
or both of feedback-based and feedforward-based ANR),
lower data transfer rates of one or more pathways, disable
branches within pathways, lower data transfer rates between
digital filters within a filter block, replace digital filters that
consume more power with digital filters that consume less
power, reduce the complexity of a transfer function employed
in providingANR, reduce the overall quantity of digital filters
within a filter block, and/or reduce the gain to which one or
more sounds are subjected by reducing VGA gain settings
and/or altering filter coefficients. However, in taking one or
more of these or other similar actions, the processing device
510 may be further caused by the ANRroutine 525 to estimate
a degree of reduction in the provision of ANR that balances
one or both of the goals of reducing power consumption and
avoiding the provision of too great a degree ofANR with one
or both of the goals of maintaining a predetermined desired
degree of quality of sound and quality of ANR provided to a
user of the personal ANR device 1000. A minimum data
transfer rate, a maximum signal-to-noise ratio or other measure may be used as the predetermined degree of quality or
ANR and/or sound.
As an example, and referring back to the signal processing
topology 2500a of FIG. 4a in which the pathways 200, 300
and 400 are explicitly depicted, a reduction in the degree of
ANR provided and/or in the consumption of power may be
realized through turning off one or more of the feedbackbasedANR, feedforward-basedANR and pass-through audio
functions. This would result in at least some of the components along one or more of the pathways 200, 300 and 400
either being operated to enter a low power state in which
operations involving digital data would cease within those
components, or being substantially disconnected from the
power source 180. A reduction in power consumption and/or
degree of ANR provided may also be realized through lowering the data transfer rate(s) of at least portions of one or
more of the pathways 200, 300 and 400, as previously discussed in relation to FIG. 4a.
As another example, and referring back to the signal processing topology 2500b of FIG. 4b in which the pathways
200, 300 and 400 are also explicitly depicted, a reduction in
power consumption and/or in the complexity oftransfer functions employed may be realized through turning ·off the flow
of data through one of the branches of the split in the pathway
400. More specifically, and as previously discussed in relation
to FIG. 4b, the crossover frequency employed by the digital
filters within the filter block 450 to separate the modified

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pass-through audio into higher frequency and lower frequency sounds may be selected to cause the entirety of the
modified pass-through audio to be directed towards only one
of the branches of the pathway 400. This would result in
discontinuing of the transfer of modified pass-through audio
data through one or the other of the summing nodes 230 and
370, thereby enabling a reduction in power consumption and!
or in the introduction of noise sounds from components by
allowing the combining function of one or the other of these
summing nodes to be disabled or at least to not be utilized.
Similarly, and referring back to the signal processing topology 2500d of FIG. 4d (despite the lack of explicit marking of
its pathways), either the crossover frequency employed by the
filterblock450 or the gain settings of the VGAs 445, 455 and
460 may be selected to direct the entirety of the modified
pass-through audio data down a single one of the three possible pathway branches into which each of these VGAs lead.
Thus, a reduction in power consumption and/or in the introduction of noise sounds would be enabled by allowing the
combining function of one or the other of the summing nodes
230 and 290 to be disabled or at least not be utilized. Still
further, one or more of the VGAs 445, 455 and 460 through
which modified pass-through audio data is not being transferred may be disabled.
As still another example, and referring back to the filter
block topology 3500a of FIG. 5a in which the allocation of
three data transfer rates 672, 675 and 678 are explicitly
depicted, a reduction in the degree ofANR provided and/or in
power consumption may be realized through lowering one or
more of these data transfer rates. More specifically, within a
filter block adopting the filter block topology 3500a, the data
transfer rate 675 at which digital data is transferred among the
digital filters 652, 654-656 and 658 may be reduced. Such a
change in a data transfer rate may also be accompanied by
exchanging one or more of the digital filters for variations of
the same type of digital filter that are better optimized for
lower bandwidth calculations. As will be familiar to those
skilled in the art of digital signal processing, the level of
calculation precision required to maintain a desired predetermined degree of quality of sound and/or quality of ANR in
digital processing changes as sampling rate changes. Therefore, as the data transfer rate 675 is reduced, one or more of
the biquad filters 654-656 which may have been optimized to
maintain a desired degree of quality of sound and/or desired
degree of quality ofANR at the original data transfer rate may
be replaced with other variants ofbiquad filter that are optimized to maintain substantially the same quality of sound
and/ or ANR at the new lower data transfer rate with a reduced
level of calculation precision that also reduces power consumption. This may entail the provision of different variants
of one or more of the different types of digital filter that
employ coefficient values of differing bit widths and/or incorporate differing quantities of taps.
As still other examples, and referring back to the filter
block topologies 3500c and 3500d of FIGS. 5c and 5d,
respectively, as well as to the filter block topology 3500a, a
reduction in the degree of ANR provided and/or in power
consumption may be realized through reducing the overall
quantity of digital filters employed in a filter block. More
specifically, the overall quantity of five digital filters in the
serial chain of the filter block topology 3500a may be reduced
to the overall quantity of three digital filters in the shorter
serial chain of the filter block topology 3500d. As those
skilled in the artwouldreadilyrecognize, such a change in the
overall quantity of digital filters would likely need to be
accompanied by a change in the coefficients provided to the
one or more of the digital filters that remain, since it is likely

that the transfer function(s) performed by the original five
digital filters would have to be altered or replaced by transfer
function(s) that are able to be performed with the three digital
filters that remain. Also more specifically, the overall quantity
of five digital filters in the branching topology of the filter
block topology 3500c may be reduced to an overall quantity
of three digital filters by removing or otherwise deactivating
the filters of one of the branches (e.g., the biquadfilter 656 and
the interpolating filter 657 of one branch that provides one of
the two outputs). This may be done in concert with selecting
a crossover frequency for a filter block providing a crossover
function to effectively direct all frequencies of a sound represented by digital data to only one of the two outputs, and/or
in concert with operating one or more VGAs external to a
filter block to remove or otherwise cease the transfer of digital
data through a branch of a signal processing topology.
Reductions in data transfer rates may be carried out in
various ways in either of the internal architectures 2200a and
2200b. By way of example in the internal architecture 2200a,
various ones of the data transfer clocks provided by the clock
bank 570 may be directed through the switch array 540 to
differing ones of the digital filters, VGAs and summing nodes
of a signal processing topology and/or filter block topology to
enable the use of multiple data transfer rates and/or conversions between different data transfer rates by one or more of
those components. By way of example in the internal architecture 2200b, the processing device 510 may be caused to
execute the sequences of instructions of the various instantiations of digital filters, VGAs and summing nodes of a
signal processing topology and/or filter block topology at
intervals of differing lengths of time. Thus, the sequences of
instructions for one instantiation of a given component are
executed at more frequent intervals to support a higher data
transfer rate than the sequences of instructions for another
instantiation of the same component where a lower data transfer rate is supported.
As yet another example, and referring back to any of the
earlier-depicted signal processing topologies and/or filter
block topologies, a reduction in the degree of ANR provided
and/or in power consumption may be realized through the
reduction of the gain to which one or more sounds associated
with the provision of ANR (e.g., feedback reference and/or
anti-noise sounds, or feedforward reference and/or anti-noise
sounds). Where a VGA is incorporated into at least one of a
feedback-basedANR pathway and a feedforward-basedANR
pathway, the gain setting of that VGA may be reduced. Alternatively and/or additionally, and depending on the transfer
function implemented by a given digital filter, one or more
coefficients of that digital filter may be altered to reduce the
gain imparted to whatever sounds are represented by the
digital data output by that digital filter. As will be familiar to
those skilled in the art, reducing a gain in a pathway can
reduce the perceptibility of noise sounds generated by components. In a situation where there is relatively little in the
way of environmental noise sounds, noise sounds generated
by components can become more prevalent, and thus, reducing the noise sounds generated by the components can
become more important than generating anti -noise sounds to
attenuate what little in the way of environmental noise sounds
may be present. In some implementations, such reduction(s)
in gain in response to relatively low environmental noise
sound levels may enable the use oflower cost microphones.
·In some implementations, performing such a reduction in
gain at some point along a feedback-basedANR pathway may
prove more useful than along a feedforward-basedANR pathway, since environmental noise sounds tend to be more
attenuated by the PNR provided by the personal ANR device

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before ever reaching the feedback microphone 120. As a
result of the feedback microphone 120 tending to be provided
with weaker variants of environmental noise sounds than the
feedforwardmicrophone 130, the feedback-basedANR function may be more easily susceptible to a situation in which
noise sounds introduced by components become more prevalent than environmental noise sounds at times when there is
relatively little in the way of environmental noise sounds. A
VGA may be incorporated into a feedback-basedANR pathway to perform this function by normally employing a gain
valueofl which would then be reduced to lhorto some other
preselected lower value in response to the processing device
510 and/or another processing device external to the ANR
circuit 2000 and to which the ANR circuit 2000 is coupled
determining that environmental noise levels are low enough
that noise sounds generated by components in the feedbackbased ANR pathway are likely to be significant enough that
such a gain reduction is more advantageous than the production of feedback anti-noise sounds.
The monitoring of characteristics of environmental noise
sounds as part of determining whether or not changes inANR
settings are to be made may entail any of a number of
approaches to measuring the strength, frequencies and/or
other characteristics of the environmental noise sounds. In
some implementations, a simple sound pressure level (SPL)
or other signal energy measurement without weighting may
be taken of environmental noise sounds as detected by the
feedback microphone 120 and/or the feedforward microphone 130 within a preselected range of frequencies. Alternatively, the :frequencies within the preselected range of frequencies of a SPL or other signal energy measurement may
subjected to the widely known and used "A-weighted" frequency weighting curve developed to reflect the relative sensitivities of the average human ear to different audible frequencies.
FIGS. 6a through 6c depict aspects and possible implementations of triple-buffering both to enable synchronized
ANR setting changes and to enable a failsafe response to an
occurrence and/or to indications of a likely upcoming occurrence of an out-of-bound condition, including and not limited
to, clipping and/or excessive amplitude of acoustically output
sounds, production of a sound within a specific range of
frequencies that is associated with a malfunction, instability
of at least feedback-basedANR, or other condition that may
generate undesired or uncomfortable acoustic output. Each of
these variations of triple-buffering incorporate at least a trio
ofbuffers 620a, 620b and 620c. In each depicted variation of
triple-buffering, two of the buffers 620a and 620b are alternately employed during normal operation oftheANR circuit
2000 to synchronously update desiredANR settings "on the
fly," including and not limited to, topology interconnections,
data clock settings, data width settings, VGA gain settings,
and filter coefficient settings. Also, in each depicted variation
of triple-buffering, the third buffer 620c maintains a set of
ANR settings deemed to be "conservative" or "failsafe" settings that may be resorted to bring theANR circuit 2000 back
into stable operation and/or back to safe acoustic output levels
in response to an out-of-bound condition being detected.
As will be familiar to those skilled in the art of controlling
digital signal processing for audio signals, it is often necessary to coordinate the updating of various audio processing
settings to occur during intervals between the processing of
pieces of audio data, and it is often necessary to cause the
updating of at least some of those settings to be made during
the same interval. Failing to do so can result in the incomplete
programming of filter coefficients, an incomplete or malformed definition of a transfer function, or other mismatched

configuration issue that can result in undesirable sounds
being created and ultimately acoustically output, including
and not limited to, sudden popping or booming noises that can
surprise or frighten a listener, sudden increases in volume that
are unpleasant and can be harmful to a listener, or howling
feedback sounds in the case ofupdating feedback-basedANR
settings that can also be harmful.
In some implementations, the buffers 620a-c of any of
FIGS. 6a-c are dedicated hardware-implemented registers,
the contents of which are able to be clocked into registers
within the VGAs, the digital filters, the summing nodes, the
clocks of the clock bank 570 (if present), switch array 540 (if
present), the DMA device 541 (if present) and/or other components. In other implementations, the buffers 620a-c of
FIGS. 6a-c are assigned locations within the storage 520, the
contents of which are able to be retrieved by the processing
device 510 and written by the processing device 510 into
other locations within the storage 520 associated with instantiations of the VGAs, digital filters, and summing nodes,
and/or written by the processing device 510 into registers
within the clocks oftheclockbank570 (if present), the switch
array 540 (if present), the DMA device 541 (if present) and/or
other components.
FIG. 6a depicts the triple-buffering of VGA settings,
including gain values, employing variants of the buffers
620a-c that each store differing ones ofVGA settings 626. An
example of a use of such triple-buffering ofVGA gain values
may be the compression controller 950 operating one or more
VGAs to reduce the amplitude of sounds represented by
digital data in response to detecting occurrences and/or indications of impending occurrences of clipping and/or other
audible artifacts in the acoustic output of the acoustic driver
190. In some implementations, the compression controller
950 stores new VGA settings into a selected one of the buffers
620a and 620b. At a subsequent time that is synchronized to
the flow of pieces of digital data through one or more of the
VGAs, the settings stored in the selected one of the buffers
620a and 620b are provided to those VGAs, thereby avoiding
the generation of audible artifacts. As those skilled in the art
will readily recognize, the compression controller 950 may
repeatedly update the gain settings ofVGAs over a period of
time to "ramp down'' the amplitude of one or more sounds to
a desired level of amplitude, rather than to immediately
reduce the amplitude to that desired level. In such a situation,
the compression controller 950 would alternate between storing updated gain settings to the buffer 620a and storing
updated gain settings to the buffer 620b, thereby enabling the
decoupling of the times at which each of the buffers 620a and
620b are each written to by the compression controller 950
and the times at which each of the buffers provide their stored
VGA settings to the VGAs. However, a set of more conservatively selected VGA settings is stored in the buffer 620c,
and these failsafe settings may be provided to the VGAs in
response to an out-of-bound condition being detected. Such
provision of the VGA settings stored in the buffer 620c overrides the provision of any VGA settings stored in either ofthe
buffers 620a and 620b.
FIG. 6b depicts the triple-buffering of filter settings·,
including filter coefficients, employing variants of the buffers
620a-c that each store differing ones of filter settings 625. An
example of a use of such triple-buffering of filter coefficients
may be adjusting the range of frequencies and/or the degree of
attenuation of noise sounds that are reduced in the feedbackbased ANR provided by the personal ANR device 1000. In
some implementations, processing device 510 is caused by
the ANR routine 525 to store new filter coefficients into a
selected one of the buffers 620a and 620b. At a subsequent

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time that is synchronized to the flow of pieces of digital data
coupling the ANR circuit 2000 to other devices via at least
one bus 535. Others ofthese possible additions rely on the use
through one or more ofthe digital filters, the settings stored in
the selected one of the buffers 620a and 620b are provided to
of the interface 530 to receive a signal from at least one
manually-operable control.
those digital filters, thereby avoiding the generation of
More particularly, in executing a sequence of instructions
audible artifacts. Another example of a use of such triple- 5
buffering of filter coefficients may be adjusting the crossover
of the loading routine 522 to possibly retrieve at least some of
frequency employed by the digital filters within the filter
the contents oftheANR settings 527 from an external storage
device (e.g., the storage device 170), the processing device
block 450 in some of the above signal processing topologies
to divide the sounds of the modified pass-through audio into
510 may be caused to configure the ANR circuit 2000 to
lower and higher frequency sounds. At a time synchronized to 1o accept those contents from an external processing device
9100, instead. Also, to better enable the use of adaptive algoat least the flow of pieces of digital data associated with
pass-through audio through the digital filters of the filter
rithms in providing feedback-based and/or feedforwardbased ANR functions, the external processing device 9100
block 450, filter settings stored in one or the other of the
buffers 620a and 620b are provided to at least some of the
may be coupled to the ANR circuit 2000 to augment the
digital filters.
15 functionality of the ANR circuit 2000 with analysis of statistical information concerning feedback reference sounds,
FIG. 6c depicts the triple-buffering of either all or a selectable subset of clock, VGA, filter and topology settings,
feedforward reference sounds and/or pass-through audio,
where side-chain information is provided from downsamemploying variants of the buffers 620a-c that each store difpling and/or other filters either built into or otherwise confering ones of topology settings 622, filter settings 625, VGA
settings 626 and clock settings 627. An example of a use of 20 nected to one or more oftheADCs 210,310 and410. Further,
to enable cooperation between two of the ANR circuits 2000
triple-buffering of all of these settings may be changing from
one signal processing topology to another in response to a
to achieve a form of binaural feedforward-basedANR, each
one of the ANR circuits 2000 may transmit copies of feeduser of the personal ANR device 1000 operating a control to
forward reference data to the other. Still further, one or more
activate a "talk-through" feature in which the ANR provided
by the personalANR device 1000 is altered to enable the user 25 oftheANR circuit 2000 and/or the external processing device
9100 may monitor a manually-operable talk-through control
to more easily hear the voice of another person without hav9300 for instances of being manually operated by a user to
ing to remove the personal ANR device 1000 or completely
make use of a talk-through function.
turn offtheANR function. The processing device 510 may be
caused to store the settings required to specify a new signal
The ANR circuit 2000 may accept an input from the talkprocessing topology in which voice sounds are more readily 30 through control 9300 coupled to the ANR circuit 2000
able to pass to the acoustic driver 190 from the feedforward
directly, through another ANR circuit 2000 (if present), or
microphone 130, and the various settings of the VGAs, digital
through the external processing device 9100 (if present).
Where the personalANR device 1000 incorporates two of the
filters, data clocks and/ or other components of the new signal
ANR circuit 2000, the talk-through control 9300 may be
processing topology within one or the other of the buffers
620a and 620b. Then, at a time synchronized to the flow of at 35 directly coupled to the interface 530 of each one of the ANR
least some pieces of digital data representing sounds through
circuit 20 00, or may be coupled to a single one of the external
at least one component (e.g., anADC, a VGA, a digital filter,
processing device 9100 (if present) that is coupled to both of
a sUlllming node, or a DAC), the settings are used to create the
the ANR circuits 2000, or may be coupled to a pair of the
interconnections for the new signal processing topology (by
external processing devices 9100 (if present) where each one
being provided to the switch array 540, if present) and are 40 of the processing devices 9100 is separately coupled to a
separate one of each oftheANR circuits 2000.
provided to the components that are to be used in the new
signal processing topology.
Regardless of the exact manner in which the talk-through
However, some variants of the triple-buffering depicted in
control 9300 is coupled to other component(s), upon the
talk-through control 9300 being detected as having been
FIG. 6c may further incorporate a mask 640 providing the
ability to determine which settings are actually updated as 45 manually operated, the provision of at least feedforwardeither of the buffers 620a and 620b provide their stored conbased ANR is altered such that attenuation of sounds in the
human speech band detected by the feedforwardmicrophone
tents to one or more components. In some embodiments, bit
130 is reduced. In this way, sounds in the human speech band
locations within the mask are selectively set to either 1 or 0 to
selectively enable the contents of different ones of the settings
detected by the feedforward microphone 130 are actually
corresponding to each of the bit locations to be provided to 50 conveyed through at least a pathway for digital data associated with feedforward-based ANR to be acoustically output
one or more components when the contents of one or the other
of the buffers 620a and 620b are to provide updated settings
by the acoustic driver 190, while other sounds detected by the
feedforward microphone 130 continue to be attenuated
to the components. The granularity of the mask 640 may be
such that each individual setting may be selectively enabled
through feedforward-based ANR. In this way, a user of the
for updating, or may be such that the entirety of each of the 55 personal ANR device 1000 is still able to have the benefits of
topology settings 622, the filter settings 625, the VGA setting
at least some degree of feedforward-based ANR to counter
626 and the clock setting 627 are able to be selected for
environmental noise sounds, while also being able to hear the
updating through the topology settings mask 642, the filter
voice of someone talking nearby.
settings mask 645, the VGA settings mask 646 and the clock
As will be familiar to those skilled in the art, there is some
settings mask 647, respectively.
60 variation in what range of frequencies is generally accepted as
defining the human speech band from ranges as wide as 300
FIGS. 7a and 7b each depict variations of a number of
possible additions to the internal architectures 2200a and
Hz to 4 KHz to ranges as narrow as 1 KHz to 3 KHz. In some
2200b, respectively, of the ANR circuit 2000. Therefore, it
implementations, the processing device 510 and/or the external processing device 9100 (ifpresent) is caused to respond to
should be noted that for sake of simplicity of discussion, only
portions of the internal architectures 2200a and 2200b asso- 65 the user operating the talk-through control9300 by altering
ANR settings for at least the filters in the pathway for feedciated with these possible additions are depicted. Some of
forward-based ANR to reduce the range of frequencies of
these possible additions rely on the use of the interface 530

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environmental noise sounds attenuated through feedfmwardbasedANR such that the feedfmward-basedANR function is
substantially restricted to attenuating frequencies below
whatever range of frequencies is selected to define the human
speech band forthepersonalANRdevice 1000.Alternatively,
the ANR settings for at least those filters are altered to create
a "notch" for a form of the human speech band amidst the
range of frequencies of environmental noise sounds attenuated by feedforward-based ANR, such that feedforwardbasedANR attenuates environmental noise sounds occurring
in frequencies below that human speech band and above that
hmnan speech band to a considerably greater degree than
sounds detected by the feedforward microphone 130 that are
within that human speech band. Either way, at least one or
more filter coefficients are altered to reduce attenuation of
sounds in the human speech band. Further, the quantity and/or
types of filters employed in the pathway for feedforwardbased ANR may be altered, and/or the pathway for feedforward-basedANR itself may be altered.
Although not specifically depicted, an alternative approach
to providing a form of talk-through function that is more
amenable to the use of analog filters would be to implement a
pair of parallel sets of analog filters that are each able to
support the provision offeedforward-basedANR functionality, and to provide a form of manually-operable talk-through
control that causes one or more analog signals representing
feedforward-based ANR to be routed to and/or from one or
the other of the parallel sets of analog filters. One of the
parallel sets of analog filters is configured to provide feedforward-basedANR without accommodating talk-throughfunctionality, while the other of the parallel sets of filters is configured to provide feedforward-based ANR in which sounds
within a form of the human speech band are attenuated to a
lesser degree. Something of a similar approach could be
implemented within the internal architecture 2200a as yet
another alternative, in which a form of manually-operable
talk-through control directly operates at least some of the
switching devices within the switch array 540 to switch the
flow of digital data between two parallel sets of digital filters.
FIG. 8 is a flowchart of an implementation of a possible
loading sequence by which at least some ofthe contents of the
ANR settings 527 to be stored in the storage 520 may be
provided across the bus 535 from either the external storage
device 170 or the processing device 9100. 1bis loading
sequence is intended to allow the ANR circuit 2000 to be
flexible enough to accommodate any of a variety of scenarios
without alteration, including and not limited to, only one of
the storage device 170 and the processing device 9100 being
present on the bus 535, and one or the other of the storage
device 170 and the processing device 9100 not providing such
contents despite both of them being present on the bus. The
bus 535 may be either a serial or parallel digital electronic
bus, and different devices coupled to the bus 535 may serve as
a bus master at least coordinating data transfers.
Upon being powered up and/or reset, the processing device
510 accesses the storage 520 to retrieve and execute a
sequence of instructions of the loading routine 522. Upon
executing the sequence ofinstructions, at 632, the processing
device 510 is caused to operate the interface 530 to cause the
ANR circuit 2000 to enter master mode in which the ANR
circuit 2000 becomes a bus master on the bus 535, and then
the processing device 510 further operates the interface 530 to
attempt to retrieve data (such as part of the contents of the
ANR settings 527) from a storage device also coupled to the
bus 535, such as the storage device 170. If, at 633, the attempt
to retrieve data from a storage device succeeds, then the
processing device 510 is caused to operate the interface 530 to

cause the ANR circuit 2000 to enter a slave mode on the bus
535 to enable another processing device on the bus 535 (such
as the processing device 9100) to transmit data to the ANR
circuit 2000 (including at least part ofthe contents of theANR
settings 527) at 634.
However, if at 633, the attempt to retrieve data from a
storage device fails, then the processing device 510 is caused
to operate the interface 530 to cause theANR circuit 2000 to
enter a slave mode on the bus 535 to enable receipt of data
from an external processing device (such as the external processing device 9100) at 635. At 636, the processing device
510 is further caused to await the receipt of such data from
another processing device for a selected period oftime. If, at
637, such data is received from another processing device,
then the processing device 510 is caused to operate the interface 530 to cause the ANR circuit 2000 to remain in a slave
mode on the bus 535 to enable the other processing device on
the bus 535 to transmit further data to theANRcircuit 2000 at
638. However, if at 637, no such data is received from another
processing device, then the processing device 510 is caused to
operate the interface 530 to cause the ANR circuit 2000 to
return to being a bus master on the bus 535 and to again
attempt to retrieve such data from a storage device at 632.
FIGS. 9a and 9b each depict a mannerin which either ofthe
internal architectures 2200a and 2200b 1nay support the provision of side-chain data to the external processing device
9100, possibly to enable the processing device 9100 to add
adaptive features to feedback-based and/or feedforwardbasedANR functions performed by theANR circuit 2000. In
essence, while the ANR circuit 2000 performs the filtering
and other aspects of deriving feedback and feedforward antinoise sounds, as well as combining those anti-noise sounds
with pass-through audio, the processing device 9100 performs analyses of various characteristics offeedback and/or
feedforward reference sounds detected by the microphones
120 and/or 130. Where the processing device 9100 determines that there is a need to alter the signal processing topology of the ANR circuit 2000 (including altering a filter block
topology of one of the filter blocks 250, 350 and 450), alter
VGA gain values, alter filter coefficients, alter clock timings
by which data is transferred, etc., the processing device 9100
provides new ANR settings to the ANR circuit 2000 via the
bus 535. As previously discussed, those new ANR settings
may be stored in one or the other of the buffers 620a and 620b
in preparation for those new ANR settings to be provided to
components within the ANR circuit 2000 with a timing synchronized to one or more data transfer rates at which pieces of
digital data representing sounds are conveyed between components within theANR circuit 2000. Indeed, in this way, the
provision ofANR by the ANR circuit 2000 can also be made
adaptive.
In supporting such cooperation between the ANR circuit
2000 and the external processing device 9100, it may be
deemed desirable to provide copies of the feedback reference
data, the feedforward reference data and/or the pass-through
audio data to the processing device 9100 without modification. However, it is contemplated that such data may b~
sampled at high clock frequencies, possibly on the order of 1
MHz for each of the feedback reference data, the feedforward
reference data and the pass-through audio data. Thus, providing copies of all of such data at such high sampling rates
through the bus 535 to the processing device 9100 may place
undesirably high burdens on theANR circuit 2000, as well as
undesirably increase the power consumption requirements of
theANR circuit 2000. Further, at least some of the processing
that 1nay be performed by the processing device 9100 as part
of such cooperation with the ANR circuit 2000 may not

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require access to such complete copies of such data. Therefore, implementations of the ANR circuit 2000 employing
either of the internal architectures 2200a and 2200b may
support the provision oflower speed side-chain data made up
of such data at lower sampling rates and/or various metrics
concerning such data to the processing device 9100.
FIG. 9a depicts an example variant oftheADC 310 having
the ability to output both feedforward reference data representative of the feedforward reference analog signal received
by the ADC 310 from the feedforward microphone 130 and
corresponding side-chain data. This variant of the ADC 310
incorporates a sigma-delta block 322, a primary downsampling block 323, a secondary downsampling block 325, a
bandpass filter 326 and a RMS block 327. The sigma-delta
block 322 performs at least a portion of a typical sigma-delta
analog-to-digital conversion of the analog signal received by
the ADC 310, and provides the feedforward reference data at
a relatively high sampling rate to the primary downsampling
block 323. The primary downsampling block 323 employs
any of a variety of possible downsampling (and/or decimation) algorithms to derive a variant of the feedfurward reference data at a more desirable sampling rate to whatever combination of VGAs, digital filters and/or summing nodes is
employed in deriving feedforward anti-noise data representing anti-noise sounds to be acoustically output by the acoustic
driver 190. However, the primary downsampling block 323
also provides a copy of the feedforward reference data to the
secondary downsampling block325 to derive a further downsampled (and/or decimated) variant of the feedforward reference data. The secondary downsampling block 325 then provides the further downsampled variant of the feedforward
reference data to the bandpass filter 326 where a subset of the
sounds represented by the further downsampled feedforward
reference data that are within a selected range of frequencies
are allowed to be passed on to the RMS block 327. The RMS
block 327 calculates RMS values of the further downsampled
feedforward reference data within the selected range of frequencies of the bandpass filter 326, and then provides those
RMS values to the interfuce 530 for transmission via the bus
535 to the processing device 9100.
It should be noted that although the above example
involved the ADC 310 and digital data associated with the
provision of feedforward-based ANR, similar variations of
either oftheADCs 210 and 410 involving either of the feedback-based ANR and pass-through audio, respectively, are
possible. Also possible are alternate variations of the ADC
310 (or of either of the ADCs 210 and 410) that do not
incorporate the secondary downsampling block325 such that
further downsampling (and/or decimating) is not performed
before data is provided to the bandpass filter 326, alternate
variations that employ anA-weighted orB-weighted filter in
place of or in addition to the bandpass filter 326, alternate
variations that replace the RMS block 327 with another block
performing a different form of signal strength calculation
(e.g., an absolute value calculation), and alternate variations
not incorporating the bandpass filter 326 and/or the RMS
block 327 such that the downsampled (and/or decimated)
output of the secondary downsampling block 325 is more
conveyed to the interfuce with less or substantially no modification.
FIG. 9b depicts an example variant of the filter block 350
having the ability to output both feedforward anti-noise data
and side-chain data corresponding to the feedforward reference data received by the filter block 350. As has been previously discussed at length, the quantity, type and interconnections of filters within the filter blocks 250, 350 and 450 (i.e.,
their filter block topologies) are each able to be dynamically

selected as part of the dynamic configuration capabilities of
either of the internal architectures 2200a and 2200b. Therefore, this variant of the filter block 350 may be configured
with any of a variety of possible filter block topologies in
which both of the functions of deriving feedforward antinoise data and side-chain data are performed.
FIGS. lOa and lOb each depict a manner in which either of
the internal architectures 2200a and 2200b may support binaural feedforward-based ANR in which feedforward reference data is shared between a pair oftheANR circuits 2000
(with each incarnation of the ANR circuit 2000 providing
feedforward-based ANR to a separate one of a pair of the
earpieces 100). In some implementations of the personal
ANR device 1000 having a pair of the earpieces 100, feedforward reference data representing sounds detected by separate feedforward microphones 130 associated with each of
the earpieces 100 is provided to both of the separate ANR
circuits 2000 associated with each of the earpieces. This is
accomplished through an exchange of feedforward reference
data across a bus connecting the pair of ANR circuits 2000.
FIG. lOa depicts an example addition to a signal processing topology (perhaps, any one of the signal processing
topologies previously presented in detail) that includes a variant of the filter block 350 having the ability to accept the input
offeedforward reference data from two different feedforward
microphones 130. More specifically, the filter block 350 is
coupled to theADC 310 to more directly receive feedforward
reference data from the feedforward microphone 130 that is
associated with the same one ofthe earpieces to which the one
oftheANR circuits 2000 in which the filter block 350 resides
is also associated. This coupling between the ADC 310 and
the filter block 350 is made in one of the ways previously
discussed with regard to the internal architectures 2200a and
2200b. However, the filter block 350 is also coupled to the
interface 530 to receive other feedforward reference data
from the feedforward microphone 130 that is associated with
the other of the earpieces 100 through the interfuce 530 from
theANR circuit 2000 that is also associated with the other of
the earpieces 100. Correspondingly, the output of the ADC
310 by which feedforward reference data is provided to the
filter block 350 is also coupled to the interfuce 530 to transmit
its feedforward reference data to the ANR circuit 2000 associated with the other one of the earpieces 100 through the
interface 530. TheANR circuit 2000 associated with the other
one of the earpieces 100 employs this same addition to its
signal processing topology with the same variant of its filter
block 350, and these two incarnations of the ANR circuit
2000 exchange feedforward reference data through their
respective ones of the interfuce 530 across the bus 535 to
which both incarnations oftheANR circuit 2000 are coupled.
FIG. lOb depicts another example addition to a signal
processing topology that includes a variant of the filter block
350. However, this variant of the filter block 350 is involved
in the transmission of feedfurward reference data to the ANR
circuit 2000 associated with the other one of the earpieces
100, in addition to being involved in the reception offeedforward reference data from that other incarnation of the ANR
circuit 2000. Such additional functionality may be incorporated into the filter block 350 in implementations in which it
is desired to in some way filter or otherwise process feedforward reference data before it is transmitted to the other incarnation of the ANR circuit 2000.
FIGS. lla, 11b and llc depict various effects of components (both acoustic components and electronic components)
of the personal ANR device 1000 on the provision ofANR at
higher frequencies as a result of those components introducing phase shifts, including both minimum-phase and non-

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minimum-phase shifts, that are particularly pronounced at
higher frequencies. Also depicted are aspects of the use of
high frequency phase compensation to at least partly alleviate
such effects. As has been illustrated and explained earlier at
length, the generation of anti-noise sounds entails propagating signals representative of sounds through potentially
lengthy chains of components, each of which imposes a
propagation delay, and each of which has various frequency
limitations. As those skilled in the art will readily recognize,
such component characteristics inevitably impose at least
some degree of phase shift, especially at higher frequencies.
FIG.lla depicts an example offrequency limitations typical of many components employed in audio devices, such as
devices providing ANR. In this depicted example, the components impose a relatively flat level of gain on audio propagating through them at frequencies up to about 15KHz with
gain decreasing at higher frequencies. Indeed, it could be said
that components having such frequency limitations behave as
low pass filters having a cutoff frequency of about 15 KHz
(i.e., what might be referred to as a "cliff' at 15 KHz). In
normal audio applications, such behavior is not an issue, as a
result of human hearing being only capable of detecting
sounds in the range of20 Hz to 20KHz, at best, with voice and
music generally occurring at frequencies below 15 KHz. This
is not the case for personal ANR devices, as will be explained.
As will be familiar to those skilled in the art, minimum-phase
shifts result from a component or combination ofcomponents
exhibiting a frequency-dependent change in gain, such as is
the case with components exhibiting low-pass, high-pass and
band-pass filter behavior. The minimum-phase shift imposed
on audio propagating through components exhibiting this
example 15 KHz low-pass filter behavior is also depicted.
There is a substantial negative phase shift centered at about 15
KHz, with negative phase beginning to accumulate typically
a decade lower in frequency (e.g., 1.5 KHz).
Also depicted is the frequency-dependent phase shift
caused by propagation delays of audio through components.
As will be familiar to those skilled in the art, having some
amount of propagation delay (i.e., some passage of time)
from the detection of a noise sound by a microphone, to the
derivation of an anti-noise sound by one or more filters, and
then to the acoustic output of the anti-noise sound by an
acoustic driver is inevitable. In the case of feedback-based
ANR, the propagation delay resulting from the time it takes a
sound to travel from an acoustic driver acoustically outputting anti-noise sounds (e.g., the acoustic driver 190) to a
microphone employed in sensing noise sounds (e.g., the inner
microphone 120) is also a factor in the operation oftre feedback loop. For the sake of ease of discussion, it is presumed in
the depicted example that the propagation delay is the same
across all audible frequencies (i.e., it is presumed to be independent of frequency). Such a consistent propagation delay
across a range of frequencies can also result from the handling
of audio in digital form due to sampling and processing
delays. For a given amount of propagation delay that is independent of frequency, the degree of phase shift increases
linearly with frequency such that the degree of phase shift
arising at lower frequencies is considerably less than the
degree of phase shift arising at higher frequencies. The longer
wavelengths of audio at lower frequencies results in a relatively minor phase shift, while the increasingly shorter wavelengths at higher frequencies results in increasingly greater
phase shift.
Were it possible to construct a form of the personal ANR
device 1000 that was subject to only the effects of minimumphase shift, it would theoretically be possible to provide antinoise sounds at frequencies up to the frequency limitations of

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the components (i.e., 15KHz in the depicted example). However, audio propagating through the components of any personalANR device 1000, no matter how implemented, is subject to both minimum-phase shift and non-minimum-phase
shift due to propagation delay (a linear phase shift, in this
case, given the presumption of the propagation delay being
independent of frequency). Thus, the combined effects of
both the minimum-phase shift and the non-minimum-phase
shift are also depicted as a combined phase shift caused by
components.
This depiction of the combined phase shift makes clear
why feedback-basedANR is typically provided only at relatively low audio frequencies. The relatively minor phase
shifts occurring at lower frequencies makes possible the
deriving and acoustically outputting oflower frequency antinoise sounds with an inverted phase that is relatively closely
aligned to the phase of the lower frequency noise sounds that
they attenuate. This is possible because the longer wavelengths of lower frequency noise sounds results in the misalignment in phase between noise and anti-noise sounds at
lower frequencies being but a small portion of the overall
wavelengths. As a result, it is relatively easy to achieve an
alignment between lower frequency noise and anti-noise
sounds that is close enough to bring about substantial attenuation of lower frequency noise sounds. In contrast, the relatively large phase shifts at higher frequencies makes difficult
the derivation and acoustic output of higher frequency antinoise sounds with an inverted phase that is aligned to the
phase of the higher frequency noise sounds in a manner that
causes attenuation. Indeed, due to these much shorter wavelengths, there is high likelihood of sufficient undesired alignments of higher frequency noise and anti-noise sounds that
actually brings about a positive feedback characteristic in the
feedback loop of an implementation offeedback-basedANR
that causes an amplification of higher frequency noise,
instead of attenuation. As those skilled in the art offeedbackbased ANR will readily recognize, amplification of noise
sounds in this manner often leads to oscillation in the feedback loop (also referred to as "going unstable") with unpleasant acoustic results. As a result of these difficulties, attempts
to provide feedback-based ANR at higher frequencies are
rare.
These same differences in phase shift between lower and
higher frequencies also apply in the provision offeedforwardbased ANR. Again, propagation delays through components
and frequency limitations in components impose frequencydependent phase shifts. And again, the greater phase shifts at
higher frequencies make the derivation and output of higher
frequency anti-noise sounds that align with higher frequency
noise sounds in a manner that causes attenuation more difficult. However, the provision of feedforward-based ANR is
additionally affected by the direction from which noise
sounds emanate. As those skilled in the provision offeedforward-based ANR will readily recognize, the direction from
which a noise sound emanates has an effect on the relative
times at which that noise sound reaches the location of a
feedforward microphone and at which that noise sound
reaches the location at which attennation is desired to occur ·
(e.g., at anearin the case of the personalANR device 1000).
FIG. llb depicts aspects of providing phase shift compensation at higher frequencies to at least partially counter occurrences of higher frequency phase shifting of one or more of
the varieties discussed in reference to FIG. 11. Ideally, in
order to at least partially counteract the combined phase shift
arising from propagation delays and the use of components
having the 15KHz low-pass filter behavior depicted in FIG.
11a, an ideal high-frequency (HF) phase compensation trans-

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form having the behavior of an unbounded variant of highshelf filter (sometimes also called an "up-shelf' filter) may be
implemented with additional components. This behavior of
such an ideal HF phase compensation transform that substantially counteracts at least the behavior of the aforementioned
low-pass filter is depicted in FIG. 11b. This ideal HF phase
compensation transform provides relatively little or no gain at
frequencies up to 15 KHz, but provides increasing gain at 15
KHz and higher frequencies. In being unbounded, the
increasing gain above 15 KHz increases to an infinite amount.
However, as those skilled in the art of audio filters will readily
recognize, such an ideal unbounded form of high-pass filter
cannot actually be implemented with real world components.
Therefore, the behavior of a variant of HF phase compensation transform implemented with real world analog circuitry (e.g., analog filter components) that comes as close as
realistically possible to matching the behavior of the ideal HF
phase compensation transform is also depicted At frequencies up to 15KHz, the behavior of this more realizable variant
is substantially similar to that of the theoretical variant, provi ding little or no additional gain at frequencies up to 15KHz,
and providing an increasing gain that begins at 15KHz and
increases further at higher frequencies. However, due to the
inability of real world components to provide unbounded
gain, the increasing gain necessarily stops increasing at a
frequency higher than 15KHz. Further, limitations inherent
in the use of analog circuitry to create filters (i.e., performance limitations of operational amplifiers, which are subject to a finite gain-bandwidth product) require that the gain
return to zero at a still higher frequency, thus resulting in the
depicted "hill" in which gain rolls back down. As those skilled
in the art will understand, this return of the gain to zero arises
from the introduction of poles into such a compensation
transform by any operational amplifier that may be used as a
filter to implement such a compensation transform. Although
this realizable variant of HF phase compensation transform
goes some distance to providing an approach to reversing
some ofthe phase shifting seen in FIG. 11a at higher frequencies, the limitations of analog circuitry requiring the return of
gain to zero results in this realizable variant being less than
preferred.
Therefore, the behavior of another variant of HF phase
compensation transform implemented with real world digital
circuitry (e.g., digital filter components) that comes as close
as realistically possible to matching the behavior of the ideal
HF phase compensation transform is also depicted. Again, at
frequencies up to 15KHz, the behavior of this other more
realizable variant is substantially similar to that of the theoretical variant, providing little or no additional gain at frequencies up to 15 KHz, and providing an increasing gain that
begins at 15 KHz and increases further at higher frequencies.
However, again, due to the inability of real world components
to provide unbounded gain (due to limitations imposed by the
Nyquist frequency), the increasing gain necessarily stops
increasing at a frequency higher than 15 KHz. However,
unlike the earlier analog circuitry variant, this variant implemented with digital circuitry can employ one or more digital
filters in a manner that is able to maintain the increased gain
at still higher frequencies, though the gain does eventually
return to a lesser degree towards zero starting at far higher
frequencies that are well above audible frequencies. In other
words, in the implementation with digital circuitry, the gain
flattens at still higher frequencies prior to reaching the
Nyquist frequency. In essence, a ''high-shelf' filter behavior
is realized in which there is a "ski-slope" variety of behavior
in gain between two substantially flat levels of gain. One or
more digital filters may be employed to introduce zeros that

create this "ski-slope" behavior without also introducing
poles that would force the return of the gain to zero, as was the
case with the above implementation using analog circuitry.
Although this behavior of the variant implemented with digital circuitry is not identical to that of the ideal HF phase
compensation transform, this behavior is much closer than
that of the variant implemented with analog circuitry. FIG.
11b further depicts the frequency-dependent positive phase
shift arising from the behavior of this variant of the HF phase
compensation transform implemented with digital circuitry.
FIG. 11c depicts the results of employing the frequencydependent positive phase shift provided by the digitallyimplemented variant of the HF phase compensation transform of FIG. 11b to counteract much of the negative
combined phase shift of FIG. 11a. As shown, much of the
negative phase shift at frequencies up to and somewhat
beyond 15 KHz is counteracted, with a relatively small
amount of negative phase shift remaining at frequencies further above 15 KHz.
FIG.12 depicts an example ofpossible benefits that may be
realized in the provision ofANR as a result of the introduction
of such a positive frequency-dependent phase shift as a result
of the provision of the digital circuitry variant of HF phase
compensation transform of FIG. 11b. Again, the aforedescribed difficulties caused by phase shift at higher frequencies usually limits the provision of both feedforward-based
and feedback-basedANR to only lower frequencies. Further,
as those skilled in the art will readily recognize, the provision
of PNR through the use of structures worn by a user in the
vicinity of an ear (e.g., the casing 110, the ear coupling 115
and/or other components of the personal ANR device 1 000)
tends to be more effective at higher frequencies. For these
reasons, the upper limits of the range of frequencies for which
one or both of the feedforward-based and feedback-based
ANR are provided may be selected to accommodate the lower
limit of the range of frequencies for which PNR is provided.
FIG.12 depicts anexampleofsuchcoordinationoftheranges
of frequencies at which each of these forms of noise reduction
is most effective.
Through such coordination between the lower limit of the
range of frequencies for which PNR is provided with the
upper limits of the ranges of frequencies for which feedforward-based and feedback-based ANR are provided, a relatively constant magnitude of attenuation of noise sounds can
be provided across a very wide range of frequencies. In particular, it is usually desired to avoid the creation of a "notch"
in the provision of noise reduction in the range of frequencies
in which there is a transition between the provision of ANR
and PNR. It should be noted that the upper limit of the range
of frequencies for which feedback-based ANR is provided
may be set lower than the upper limit of the range offrequencies for which feedforward-basedANR is provided. This may
be deemed desirable, despite the possible loss of a relatively
constant magnitude of attenuation of noise sounds across a
wide range offrequencies, to further decrease the likelihood
of instability developing in the provision offeedback-based
ANR such that the development of a feedback loop oscillation
is avoided under most conditions, if not all conditions.
However, with the provision of the HF phase compensation
transform (especially the variant implemented with digital
circuitry), at least the upper limit of the range of frequencies
for which feedback-based and feedforward-based ANR is
provided may be increased, if not also the magnitude. FIG. 12
depicts the possibility of increasing one or both of the upper
limit of the range of frequencies for which feedback-based
ANR is provided and the magnitude of attenuation achieved
with feedback-based ANR. This is in recognition of the

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greater potential that exists to improve the provision of feedback-based ANR through the introduction of the HF phase
compensation transform than to improve the provision of
feedforward-based ANR, although potential does exist to
make improvements in the provision of feedforward-based
ANR through the introduction of such a transform. As those
skilled in the art will readily recognize, this is due to feedback-based ANR not being subject to the same earlier-discussed directionality issues to which feedforward-based
ANR is subject.
FIGS.13a and 13b depict possible approaches to providing
high frequency phase compensation (i.e., adding an implementation ofhigh frequency phase compensation transform)
to a filter block topology (such as one of the filter topologies
3500a-e) that may be employed in creating one or more
blocks of filters (such as the filter blocks 250, 350 and 450)
within signal processing topologies adopted by the ANR circuit 2000 (such as one of the signal processing topologies
2500a-g). However, given the earlier discussion of the comparatively greater benefits that can be realized through the
addition of a high frequency phase compensation transform
to the provision offeedback-based ANR, it is more likely that
the filter topologies depicted in FIGS. 13a-b would be
employed in creating the filter block 250. As was the case in
FIGS. 5a-e, the selections of types of filters, quantities of
filters, interconnections of filters and filter block topologies
depicted in each of FIGS. 13a and 13b are meant to serve as
examples to facilitate understanding, and should not be taken
as limiting the scope of what is described or the scope of what
is claimed herein.
FIG. 13a depicts a possible filter block topology 3500/
incorporating high frequency phase compensation for which
the ANR circuit 2000 may be structured and/or programmed
to define a filter block, such as one of the filter blocks 250, 350
and 450. As depicted, the filter topology 3500/adds three of
biquad filters 659 coupled in series and to an output of other
filters 650. The other filters 650 is a block of one or more
filters implementing at least a transform to derive anti-noise
sounds from reference sounds detected by one or both of the
feedback microphone 120 and the feedforward microphone
130. Indeed, the other filters 650 may represent one of the
filter topologies 3500a-e to which the biquad filters 659 are
added. The biquad filters 659 cooperate to implement a high
frequency phase compensation transform to introduce a positive phase shift affecting at least higher frequency sounds to
enable the provision of one or both offeedforward-based and
feedback-basedANR across a range of frequencies having a
higher upper limit than might otherwise be possible. In implementing such a high frequency phase compensation transform, each of the biquad filters 659 is programmed with filter
coefficients that include zero value multipliers for the poles to
effectively turn the biquad filters 659 into dual-tap FIR filters
that introduce only zeros to create the "ski-slope" behavior
depicted in FIG. 11b.
It should be noted that although there are three of the
biquad filters 659 capable of implementing a 6th order form
ofthe high frequency phase compensation transform depicted
in FIG. 13a, greater or lesser quantities of the biquad filters
659 may be employed, depending on the characteristics of the
each of the biquad filters 659 and on the characteristics of the
particular high frequency phase compensation transform to
be implemented. Use of a greater quantity ofthe biquad filters
659 more easily enables the implementation of a higher order
form of the high frequency phase compensation transform.
Ideally, a 6th order variant ofthe high frequency phase compensation transform may be deemed desirable to reduce noise
and/or to provide considerable gain such that the height of the

ski slope curve depicted in FIG. 11b for the digitally implemented variant of the high frequency phase compensation
transform best compensates for the frequency response limitations of the acoustical components of a personal ANR
device. However, constraints on the quantity ofbiquad filters
554 in the filter bank 550 available to be assigned and/or
resources available to instantiate hi quads based on the biquad
filter routine 555 (e.g., power, memory, etc.) may necessitate
the use of a lesser number of the biquad filters 659 such that
only a lower order variant of the high frequency phase compensation transform may be implemented. Thus, using only a
pair of the biquad filters 659 and thereby implementing a 4th
order form of the high frequency phase compensation transform may be deemed more desirable as a better balance of
providing gain, maintaining gain margin, reducing noise and
conserving power.
FIG. 13b depicts another possible filter block topology
3500g incorporating high frequency phase compensation for
which the ANR circuit 2000 may be structured and/or programmed to define a filter block, such as one of the filter
blocks 250, 350 and 450. As depicted, the filter topology
3500g adds one of a FIR filter 658 coupled to an output of
other filters 650. The FIR filter 658 implements a high frequency phase compensation transform to introduce a positive
phase shift affecting at least higher frequency sounds to
enable the provision of one or both offeedforward-based and
feedback-basedANR across a range offrequencies having a
higher upper limit than might otherwise be possible. Of
course, with the use of the FIR filter 658, the ability to introduce zeros without introducing poles is provided to create the
"ski-slope" behavior depicted in FIG. 11b.
It should be noted that although there is only one of the FIR
filter 658 depicted in FIG. 13b, additional ones of the FIR
filter 658 may be employed if the one of the FIR filter 658
depicted in FIG.13b does not have a sufficient quantity oftaps
or is in some other way unable to implement a particular high
frequency phase compensation transform. Again, although it
may be deemed desirable to implement a higher order variant
of high frequency phase compensation transform to increase
gain with increasing frequency, various constraints may
necessitate the implementation of a lower order variant (e.g.,
power consumption per tap of a FIR filter). In an effort to
balance gain with other factors, a 4th, 5th or 6th order form of
the high frequency phase compensation transform may be
deemed desirable.
As explicitly depicted in FIGS. 13a-b, in some implementations, the ANR circuit 2000 employs the internal architecture 2200a such that the ANR circuit 2000 incorporates the
filter bank 550 incorporating multitudes of the biquad filters
554 and/or the FIR filters 558. One or more of each of the
biquad filters 554 and FIR filters 558 may be interconnected
in any of a number ofways via the switch array 540, including
in a way that defines either of the filter topologies 3500/and
3500g. Alternatively, in other implementations, the ANR circuit 2000 employs the internal architecture 2200b such that
the ANR circuit 2000 incorporates a storage 520 ir1 which is
stored the biquad filter routine 555 and/or the FIR filter routine 559. Varying quantities ofbiquad and/or FIR filters may
be instantiated within available storage locations of the storage 520 with any of a variety of interconnections defined
between them, including quantities of filters and interconnections that define either of the filter topologies 3500/ and
3500g.
As previously discussed, power conservation and/or other
benefits may be realized by employing different data transfer
rates along different pathways of digital data representing
sounds in a signal processing topology. In support of convert-

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ing between different data transfer rates, including where one
pathway operating at one data transfer rate is coupled to
another pathway operating at another data transfer rate, different data transfer clocks may be provided to different ones
of the digital filters within a filter block, and/or one or more
digital filters within a filter block may be provided with multiple data transfer clocks. Noise shaping and other benefits
may also be realized through conversions between transfer
rates. Indeed, as previously discussed, one or more of the
ADCs 210, 310 and 410 may employ a sigma-delta analogto-digital converter (also sometimes referred to as a "deltasigma" analog-to-digital converter) sampling at a high rate
followed by a downsampling block to greatly lower the rate of
transfer of data before the digital data is provided to a VGA or
filter block. As those skilled in the art will readily recognize,
such a combination of a sigma-delta analog-to-digital converter and downsampling block is an approach to providing
noise-shaping that improves audio performance. In implementing the high frequency phase compensation transform
with digital filters (e.g., with the biquadfilters 659 and/or the
FIR filter 658), the desired order of the transform may partially depend on the effects of the use of such a combination
of sigma-delta converter and downsampling block on feedback and/or feedforward reference sounds.
Other implementations are within the scope of the following claims and other claims to which the applicant may be
entitled

both a sigma-delta analog-to-digital converter and a downsampling block of the ANR circuit of the personal ANR
device.
7. An active noise reduction (ANR) circuit structured to
provide at least one of feedforward-basedANR and feedbackbased ANR in a first range of frequencies, the ANR circuit
comprising:
at least a first digital filter positioned along a pathway
defined in the ANR circuit and configured with at least a
first coefficient to implement a first transform to generate digital data representing an anti-noise sound;
at least a second digital filter positioned along the pathway
and configured with at least a second coefficient to introduce at least one zero to implement a high-frequency
phase compensation transform to introduce a positive
phase in the pathway in at least the first range of frequencies, wherein:
introducing the at least one zero adds gain increasing with
frequency at least partly within a secondrangeofaudible
frequencies outside of the first range of frequencies; and
the gain flattens in a range of frequencies above the second
range of audible frequencies.
8. The ANR circuit of claim 7, further comprising:
a sigma-delta analog-to-digital converter positioned at an
end of the pathway to convert an analog signal received
from a microphone of a personal ANR device into which
the ANR circuit is incorporated into digital data representing a reference noise sound sampled at a first rate;
and
a downsampling block positioned in the pathway following
the sigma-delta analog-to-digital converter to reduce a
data transfer rate of the digital data from the first rate to
a second rate that is lower than the first rate.
9. The ANR circuit of claim 7, wherein the at least a second
digital filter is a FIR filter.
10. TheANR circuit of claim 9, wherein:
the FIR filter comprises at least four taps; and
the at least a second coefficient comprises a coefficient for
each of the at least four taps to implement the highfrequency phase compensation transform as at least a
fourth order transfurm.
11. The ANR circuit of claim 7, wherein the at least a
second digital filter is a biquad filter.
12. The ANR circuit of claim 7, wherein the at least a
second coefficient is selected to introduce the at least one zero
to cause the gain to start increasing with gain at a higher
audible frequency beneath 15KHz.
13. A personal active noise reduction (ANR) device to
provide at least one offeedforward-basedANR and feedbackbased ANR to an ear of a user in a
first range of frequencies, the personal ANR device comprising:
a casing defining a cavity to be acoustically coupled to
an ear canal of an ear of the user at a time when the
casing is in position adjacent the ear;
an acoustic driver disposed within the casing to acoustically output anti-noise sounds into the cavity as part
ofthe provision ofthe at least one of the feedforwardbasedANR and the feedback-basedANR;
anANR circuit coupled to the acoustic driver to generate
the anti-noise sounds from noise reference sounds to
drive the acoustic driver with an analog signal to cause
the acoustic driver to acoustically output the antinoise sounds;
at least one digital filter incorporated into the ANR circuit; and

The invention claimed is:
1. A method of implementing a high-frequency phase compensation transform in a signal processing pathway of a circuit providing active noise reduction (ANR) circuit in a first
range of frequencies in a personal ANR device, the method
comprising:
programming a digital filter having at least one tap with at
least one coefficient to cause the digital filter to employ
the at least one tap to introduce at least one zero to
introduce a positive phase in the pathway in at least the
first range of frequencies; and
selecting the at least one coefficient to cause the addition of
a gain that increases with frequency within a second
range of audible frequencies outside of the first range of
frequencies and that flattens in a range of frequencies
above the second range of audible frequencies.
2. The method of claim 1, further comprising selecting a
FIR filter as the digital filter.
3. The method of claim 2, wherein:
the FIR filter comprises at least four taps; and
selecting the at least one coefficient comprises selecting a
coefficient for each of the at least four taps to implement
the high-frequency phase compensation transform as at
least a fourth order transform.
4. The method of claim 1, further comprising:
selecting at least one biquad filter as the digital filter; and
programming another tap of the at least one biquad filter
that is structured to enable the at least one biquadfilterto
introduce a pole with another coefficient to cause the at
least one biquad filter to not employ the another tap to
introduce a pole.
5. The method of claim 1, wherein selecting the at least one
coefficient comprises selecting the at least one coefficient to
introduce the at least one zero to cause the gain to start
increasing with gain at a higher audible frequency beneath
15KHz.
6. The method of claim 1, further comprising positioning
the at least one digital filter along a feedbackANR pathway of
anANR circuit ofthe personal ANR device at a position after

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at least one tap incorporated into the digital filter and
14. The personal ANR device of claim 13, wherein the at
least one digital filter is a FIR filter.
configured with at least one coefficient to introduce at
15. The perSonal ANR device of claim 14, wherein:
least one zero to implement a high-frequency phase
the FIR filter comprises at least four taps; and
compensation transform to introduce a positive phase
the at lease one coefficient comprises a coefficient for each
in the generation of the anti-noise sounds in at least 5
ofthe at least four taps to implement the high-frequency
the first range of frequencies, wherein:
phase compensation transform as at least a fourth order
introducing the at least one zero adds gain increasing with
transform.
frequency at least partly within a second range of audible
16. The personal ANR device of claim 13, wherein the at
frequencies outside of the first range of frequencies; and
1o least a one digital filter is a biquad filter.
the gain flattens in a range of frequencies above the second
range of audible frequencies.

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