Bose Corporation v. Beats Electronics LLC et al

Filing 1

COMPLAINT filed with Jury Demand - against Beats Electronics International Limited, Beats Electronics LLC - Magistrate Consent Notice to Pltf. ( Filing fee $ 400, receipt number 0311-1560024.) - filed by Bose Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3, # 4 Exhibit 4, # 5 Exhibit 5, # 6 Exhibit 6, # 7 Exhibit 7, # 8 Exhibit 8, # 9 Exhibit 9, # 10 Exhibit 10, # 11 Civil Cover Sheet)(rwc)

Exhibit 4

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United States Patent

(10)

Joho et al.

(12)

(45)

(54)

(75)

Inventors: Marcel Joho , Framingh阻， MA(US);
Ricardo F. Carreras , Southborough,
MA(US)

(73)

Assignee: Bose Corporation , Framingham, MA
(US)

( *)

Notice:

Subject to any disclaimer, the term ofthis
patent is extended or adjusted under 35
U.S.C. 154(b) by 420 days.

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Patent No.:
US 8,073 ,151 B2
Date of Patent:
Dec. 6, 2011

5,815 ,582
5,825 ,897
5,841 ,856
6,035 ,050
6,041 ,126
6,061 ,4 56
6,094 ,4 89

DYNAMICALLY CONFIGURABLE ANR
FILTER BLOCK TOPOLOGY

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9/1998 Claybaugh et al.
10/1998 An drea et al
1111998 Ide
3/2000 Weinfurtner et al
3/2000 Terai et al.
5/2000 An drea et al.
7/2000 Ishige et al.
(Continued)

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FOREIGN PATENT DOCUMENTS
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(21)

App l. No.: 12/430,994

(22)

Filed:

E
A

O N口 3

Invitation to Pay Additional Fees dated Ju l. 26 , 2010 for PCT/2010/
032486.

Apr. 28, 2009

(Co凶inued)

Prior Publication Data

(65)

US 201 0/0272278 Al
(51)
(52)
(58)

Primary Examiner - Elvin G Enad
Assistant Examiner - Robert W Horn

Oc t. 28 , 201 0

Int. C l.
G10K 11/16
(2006.01)
U.S. C l. ...................................................... 381171.6
Field of Classification Search .................. 381 /71. 6
See application file for complete search history.

(56)

References Cited

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(57)

ABSTRACT

In anANR circuit, possibly of a personal ANR device , each of
a feedback ANR pathway in which feedback anti-noise
sounds are generated from feedback reference sounds , a feedforward ANR pathway in which feedforward anti-noise
sounds are generated from feedforward reference sounds , and
a pass-through audio pathway in which modified passtl宜。ugh audio sounds are generated 企om received passthrough audio sounds incorporate at least a block offilters to
perform those functions; and may each incorporate one or
more VGAs and/or summing nodes. For each ofthese pathways , ANR settings for selections of quantities and types of
filters for each filter block, bit sizes of coefficients and/or
coe且cient values of each of the filters , along with still other
ANR settings , are dynamically configurable wherein
dynamic configuration is performed in syncl宜。nization with
the transfer of one or more pieces of digi的 1 data along one or
more of the pathways , at least within one or more of the filter
blocks.
30 Claims , 18 Drawing Sheets

da旭
Ou1p叫

672

678

250, 350, 450

、-3500a

US 8,073 ,151 B2
Page 2

U.S. PATENT DOCUMENTS
6 ,118 ,878
6 ,160 ,893
6 ,236 ,731
6 ,418 ,228
6 ,522 ,753
6 ,567 ,524
6 ,717 ,537
6 ,741 ,707
6 ,744 ,882
6 ,829 ,365
6 ,870 ,940
6 ,937 ,738
6 ,993 ,140
6 ,996 ,241
7 ,039 ,195
7 ,215 ,766
7 ,216 ,139
7 ,248 ,705
7 ,251 ,335
7 ,260 ,209
7 ,277 ,722
7 ,292 ,973
7 ,317 ,802
7 ,433 ,481
7 ,627 ,127
7 ,706 ,550
7 ,813 ,515
7 ,822 ,210
7 ,853 ,028
7 ,885 ,422
7 ,945 ,065
7 ,983 ,908
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2006/0088171
2007/0003078
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2007/0223715
2007/0250314
2007/0253569
2008/0025530

A
A *
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Bl *
Bl
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Al
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Al
Al *
Al
Al

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Jones
Saunders et al. ............. 381 /71. 6
Brennan et al.
Terai et al
Matsuzawa et al. ......... 381 /71. 1
Svean et al
Fang et al
Ray et a l.
Gupta et al.
Kim
Meyer et al
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Mishan
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Johnston et al. ........... 704/200.1
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Bo位i et al
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Fischer ......................... 3811312
Sinai
Menzl et al. .................. 3811314
Kuboki et al. ................ 704/228
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Ratcliff et al.
Goldberg et al. .......... 381 /71.1 1
Eichler et al.
Akiho
Onishi et al
Bo仕i et al
Bum
Aschoff et al. ............... 3811322
Sakawaki
Yeh
Escott et al
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Bose
Romesburg

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Al
Al
Al
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Al
Al
Al
Al
Al
Al
Al
Al
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乳TurtZ

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Peissig et al
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Joho etal. .................... 381 /71. 6
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Johoetal.
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JP
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for PCT/20 10/032486.
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US2010/032557
International Search Report and Written Opinion dated Sep. 16 , 2010
forPCT在JSI0/032557.

* cited by examiner

US 8,073 ,151 B2
1

2

DYNAMICALLY CONFIGURABLE ANR
FILTER BLOCK TOPOLOGY

the first set 'O f ANR settings within the filter bl 'O ck by c 'Onfiguring interc 'O nnecti 'Ons am'Ong each 'O fthe digital filters; c'O nfiguring each 'O fthe digital filters with filter c 'O efficients specified by the first set 'O fANR settings; setting a data transfer rate
at which digital data f1'Ows thr'O ugh at least 'O ne 'O fthe digital
filters as specified by the first ANR settings; 'O perating the
filter bl 'O ck t'O enable the ANR circuit t 'O provide ANR in the
earpiece; and changing an ANR setting specified by the first
set 'O f ANR settings t'O an ANR setting specified by a sec 'O nd
set 'O f ANR settings in syncl宜。n日前i'On with a transfer 'O f
digital data thr'O ugh at least a p'O rti 'O n 'O fthe pathway.
Implementati 'O ns may include, and are n 'O t limited t'O, 'O ne
'O r m 'O re 'O f the f'O ll 'Owing features. The meth'O d may further
include m 'O nit'O ring an am'O unt 'O f p 'Ower available fr 'Om a
p 'Ower s'O urce , wherein changing anANR setting specified by
the first set 'O f ANR settings t 'O anANR setting specified by the
sec 'Ond set 'O f ANR settings 'O ccurs in resp 'O nse t'O a reducti 'On
in the am'O unt 'O f p'Ower available from the p 'Ower s'O urce. The
meth'O d may further include m 'O nit 'Oring a characteristic 'O f a
s'Ound represented by digital data , wherein changing anANR
setting specified by the first set 'O f ANR settings t 'O an ANR
setting specified by the sec 'Ond set 'O f ANR settings 'O ccurs in
resp 'O nse t'O a change in the characteristi吼叫ld wherein changing an ANR setting specified by the first set 'O f ANR settings
t'O anANRsettingspecifiedbythesec 'O ndset 'O fANRsettings
may reduce a degree 'O f ANR pr'Ovided by the c 'Onfigurable
ANR circuit and may reduce c 'Onsumpti 'O n 'O f p 'Ower by the
c 'Onfigurable ANR circuit fr 'Om a p 'Ower supply c'O upled t 'O the
c 'Onfigurable ANR circui t. The meth'O d may fì叮ther include
awaiting receipt 'O f the sec 'Ond set 'O f ANR settings fr 'Om an
extemal processing device c 'O upled t'O the ANR circuit ,
wherein changing anANR setting specified by the first set 'O f
ANR settings t 'O anANR setting specified by the sec 'O nd set 'O f
ANR settings 'O ccurs inresp 'O nse t'O receiving the sec 'O nd set 'O f
ANR settings fr 'Om the external processing device. The ANR
provided by the ANR circuit may include feedback-based
ANR; and changing an ANR setting specified by the first set
'O f ANR settings t 'O anANR setting specified by the sec 'Ond set
'O f ANR settings may 'O ccur in resp 'O nse t 'O an instance 'O f
instability in at least the feedback-basedANR being detected ,
and c'O mprises changing a filter c'O e且cient specified by the
first ANR settings t 'O a filter c 'O efficient specified by the sec'O nd ANR settings t 'O rest 'O re stability
Changing an ANR setting specified by the first set 'O f ANR
settings t 'O anANR setting specified bythe sec 'O nd set 'O fANR
settings may include changing at least 'One 'O f: an interc 'O nnecti 'On 'O f the filter bl 'O ck t 'Op 'O l'O gy speci自己d by the first ANR
settings; a selecti 'On 'O f a type 'O f digital filter specified by the
自rst set 'O f ANR settings f'O r 'One 'O f the digital filters; the
quantity 'O f digital filters specified by the 且rstANR settings 'O f
the plurality 'O f digital filters; a filter c 'O e且cient specified by
the first ANR settings; and the data transfer rate specified by
the firstANR settings. Changing anANR setting specified by
the first set 'O f ANR settings t 'O anANR setting specified by the
sec 'Ond set 'O f ANR settings may include replacing 'O ne 'O f the
digital filters that is 'O f a selected type with an'Other digital
filter 'O fthe same selected type , wherein the 'O ne 'O fthe digi的l
filters supp 'O rts a filter c'O e且cient at a first bit width and
c 'Onsumes p 'Ower at a first rate during 'Operati 'On , and wherein
the 'Other digital filter supp 'O rts the same filter c 'O efficient at a
sec 'Ond bit width that is na叮'Ower than the first bit width and
c 'Onsumes p 'Ower at a sec 'O nd rate during 'O perati 'O n that is
l'Ower than the first rate.
Ad'O pting a filter bl 'O ck t'O p'O l 'O gy specified by the first set 'O f
ANR settings may include inc 'Orp 'Orating a summing n 'O de
int'O the filter bl 'O ck, and c'O nfiguring interc 'O nnecti 'O ns am'O ng
the digital filters and the summing n 'O de as specified by the

TECHNICAL FIELD
5

This discl 'O sure relates t'O pers 'O nal active n 'O ise reducti 'O n

(ANR) devices t 'O reduce ac~ustic n 'O ise in the vicinity 'O f at
least 'O ne 'O f a user' s ears.
BACKGROUND
Headph'O nes and 'Other physical c 'Onfigurati 'O ns 'O f pers 'O nal
ANR device w 'Orn ab 'Out the ears 'O f a user f 'Or purp 'O ses 'O f
is 'O lating the user's ears fr 'Om unwanted environmental
s'Ounds have bec 'Ome c'O mm'O nplace. In particular, ANR headph'Ones in which unwanted envir'Onmental n 'O ise s'O unds are
c 'Ountered with the active generati 'On 'O f anti-n'O ise s'Ounds ,
have bec 'O me highly prevalent , even in c 'O mparis 'O n t 'O headph'Ones 'O r ear plugs empl 'O ying 'O nly passive n 'O ise reducti 'O n
(PNR) techn'O l'O gy, in which a user' s ears are simply physi cally is 'O lated fr 'O m environmental n 'O ises. Especially 'O f interest t'O users are ANR headph'Ones that als 'O inc 'O rp 'O rate audi 'O
listening functi 'O nality, thereby enabling a user t'O listen t 'O
electronically pr'Ovided audi 'O (e.g. , playback 'O f rec 'O rded
audi 'O 'O r audi 'O received from an'Other device) with'Out the
intrusi 'On 'O funwanted envir'O nmental n'O ise s'O unds.
Unf'Ortunately, despite vari 'O us impr'Ovements made 'Over
time , existing pers 'O nal ANR devices c 'Ontinue t'O suffer fr 'Om
a variety 'O f drawbacks. F'O rem'O st am 'Ong th'O se drawbacks are
undesirably high rates 'O f p'Ower c 'Onsumpti 'O n leading t 'O sh'Ort
battery life , undesirably narr'Ow ranges 'O f audible frequencies
in which unwanted environm凹的1 n 'O ise s'Ounds are c'O untered
thr'Ough ANR , instances 'O f unpleasant ANR -'Originated
s'Ounds , and instances 'O f actually creating m 'O re unwanted
n 'O ise s'O unds than whatever unwanted environmental s'O unds
may be reduced.

10

15

20

25

30

35

SUMMARY
In anANR circuit, p'O ssibly 'O f a pers 'O nalANR device , each
f a feedback ANR pathway in which feedback anti-n'O ise
s'Ounds are generated fr 'Om feedback reference s'Ounds , a feed f 'Orward ANR pathway in which feedf'Orward 訕訕 -n'O ise
s'Ounds are generated fr 'O m feedf'O rward reference s'Ounds , and
a pass-thr'O ugh audi 'O pathway in which m 'O dified passthr'Ough audi 'O s'O unds are generated fr 'Om received passthr'Ough audi 'O s'O unds inc 'O rp 'O rate at least a bl 'O ck 'O ffilters t 'O
perf'O rm th'O se functi 'O ns; and may each inc 'O rp 'Orate 'One 'O r
m 'O re VGAs and/'O r summing n 'O des. F'O r each 'O fthese pathways , ANR settings f'O r selecti 'O ns 'O f quantities and types 'O f
filters f 'O r each filter bl 'O ck, bit sizes 'O f c 'O efficients and/'O r
c 'O efficient values 'O f each 'O f the filters , al 'Ong with still 'O ther
ANR settings , are dynamically c 'O nfigurable wherein
dynamic c 'Onfigurati 'O n is perf'O rmed in synchr'O nizati 'O n with
the transfer 'O f 'One 'Or m 'Ore pieces 'O f digital data al 'O ng 'O ne 'O r
m 'O re 'O f the pathways , at least within 'O ne 'Or m 'Ore 'O f the filter
bl 'O cks.
In 'O ne aspect , a meth'O d 'O f 'Op位ating a dynamically c'O nfigurable ANR circuit t 'O provide ANR in an earpiece 'O f a
pers 'O nal ANR device includes: inc 'Orp 'Orating a plurality 'O f
digital filters 'O f a quantity specified by a first set 'O f ANR
settings int 'O a filter bl 'O ck l 'O cated al 'O ng a pathway thr'O ugh
which digital data ass 'O ciated with the provisi 'On 'O f the ANR
f1'O ws within the ANR circuit; selecting a type 'O f digital filter
specified by a first set 'O f ANR settings f'O r each digital filter
企'Om 紅n'Ong a plurality 'O f types 'O f digital filter supp 'O rted by
the ANR circuit; ad'Opting a filter bl 'O ck t 'O p'O l'O gy specified by

40

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50

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60

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US 8,073 ,151 B2

3

4

first set of ANR settings to combine outputs of at least two of
routine of the plurality of filter routines comprises a sequence
of instructions that when executed by the processing device
the digital filters at the summing node; and changing anANR
setting specified by the first set of ANR settings to an ANR
causes the processing device to perform filter calculations of
setting specified by the second set ofANR settings comprises
a type of digital filter; and the processing device is further
changing an interconnection of the filter block topology 5 caused to: incorporate the plurality of digital filters and select
spe.cifie~ by th~ .first ~NR sett~ngs t?~~emove .the s~!ng
a type of digital filter for each digital filter by at least instannodeando田 ofthe at least 阿o digital filters. Adopti也 a filter
tiati~g each-digital filter based on~ filter routine selected from
blocktopology speciaed by thearst set ofANR settmgs may
the plurality ofalter routines in accordance with the type of
include con且guring interconnectIons among aarst digtal
digital alter Speziaed for each digital alter by thearst set of
filter, a second digital filter and a third digital filter of the 10
ANR settings; and adopt the filter block topology and cause
plurality of digital filters such that an output of the first digital
the ADC , the filter block and the DAC to be operated by at
filter is coupled to inputs ofthe second and third digital filters
least causing digital data to be transferred among the ADC ,
to form a branch in a f1 0w of digital data through the fir哎，
second and third digital filters; and changing anANR setti月
the digital filters and the DAC. The processing device may
specified by the fir~t set of ANR setting~ t; an ANR setting 15 dir~c~ly t~an~er di?ital ~ata among.theADC , the digital filters
specified bÝ the second set ofANR setti~gs comprises chang'::
~nd_ th~ DAC , and/Ol: th~ pro.c~ssing device may operate a
irig an interconnection of the filter block topol~gy specified
D他屯 device to transfer digital data 紅nong at least a subset of
by the first ANR settings to uncouple the third digital filter
the ADC , the digital filters and the DAC. The ANR circuit
from the first and second digital filters. Adopting a filter block
may further include an interface to enable an 紅nount of power
topology specified by the first set of ANR settings may 20 available from a power source coupled to the ANR circuit to
be monitored, and the processing device may be further
include configuring interconnections among a first digital
caused to: monitor the amount of power available from the
filter, a second digital filter and a third digital filter of the
plurality of digital filters such that an output of the first digital
power source; and change an ANR setting specified by the
first set of ANR settings to an ANR setting specified by the
filter is coupled to inputs ofthe second and third digital filters
to form a branch in a f1 0w of digital data through the fir哎， 25 second set of ANR settings in response to a reduction in the
second _and third digital filters; and configuring each of the
amount of power available from the power source. The appadigitalalterswithaltercoefHcimts spedaedbythearst setof
rams may aIrtherinclude anexternal processing device exterANR settings comprises configuring the second and third
nal to th~ ANR circui t: wherein the ÂNR circuit further comprises an interface ∞1ψ l m 也
c O 糾時 theANRc凹mt tωo theeX te岫na
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迪 侃叫叮r
刻 叩
記
digital filters with coeffic時帥 that cause at least the seco吋
andthirddi gital 且釗記郎
也廿 氾扯址 lter stωocoopeTat etωofiorm a crossover hav~~J 30 process ing device; 剖1dwherein the process ing device is fur叮 紀 品
叫
吋
吋
叮
吋叩
a selected crossover tkequency;wherein changing an ANR
ther causedto:await receipt ofthe second set ofANR settings
setting specified by the first set of ANR settings to an ANR
from the external processing device , and change an ANR
setting specified by the second set ofANR settings comprises
setting specified by the first set of ANR settings to an ANR
configuring filter coefficients of the second and third digital
alters to change the crossover frequency.35setting speciaed by the second set of ANR settings in
In one aspect, mapparams includes an ANR circuit,
response to receiving the second set ofANR settings tkomthe
wherein theÂNR circuit includes: aADC; a DAC; a processex~:nal processi月 device through the interface.
ing device; and a storage in which is stored a seq~ence of
The processing device may be further caused to monitor a
characteristic of a sound represented by digital data , and
instructions. \\司len the ;equence of instructions in-executed
by the processing device , the processing device is caused to: 的 change an ANR setting specified by the first set of ANR
incorporate a plurality of digital filters of a quantity specified
settings to anANR setting specified by the second set ofANR
by a first set of ANR settings into a filter block located along
settings in response to a change in the characteristic. The
a pathway extending from the ADC to the DAC through
processing device may be further caused to change an ANR
which digital data associated with providing ANR f1 0ws
setting specified by the first set of ANR settings to an ANR
within the ANR circuit; select a type of digital filter specified 45 setting specified by the second set of ANR settings by at least
bya first set ofANR settings for each digital filter from among
replacing one of the digital filters that is of a selected type
a plurality of ty_p es of digital filter suppo_rted by th~ ANR
with another digital filter ofthe same selected type , wherein
theo凹 ofthe digital filters supports a filter coefficient at a first
circuit; adopt a filter block topology spωiaedbytlpar-st 記t
of ANR settings within the filter block by con且g~nng mte:bit width and consumes power at a first rate during operation,
connections among each ofthe digital alters , conasure each5Oand wherein the other dgital alter supports the same alter
ofthe digitalalterswithaltercoefHdents speciaedbythearst
coefHcimt at a secondbit width that is naITowerthanthearst
set ofANR settmgs;set a data transfer rate at wl11ch digital
bit width and comumes power at a second rate during operadata f10ws through at least one ofthe digital filters as specified
tion that is lowerthan the first rate. The processing device may
by the first ANR settings; cause the ADC , the filter block and
be further caused to set a data transfer rate at which digital
the DAC to be operated to enable the ANR circuit to provide 55
ANR using reference sounds represe凶edbymmalog signal
datanowsthroud1atleastoneofthedgitaltIItemas speciaed
recewedbyANR circuit throughtheADC to derIve ant1-noise
by thearstANR settings by at least setting ahst data transfer
~~te at w?i~h ~ig~tal da:a is clocked into ~n in~u_~ ofthe digital
sounds represented by an an~og signal output by the ANR
circuit thr'augh the DÃ.C; and chang~ anANR setting specifilterandc!ockedoutofanoutputofthedigitalfilteratthefirst
fied by the fi~st set of ANR settings -to an ANR setting speci - 60 data transfer rate; and change anANR setting specified by the
fied by a second set of ANR settings in synchronization with
first set of ANR settings to an ANR setting specified by the
second set of ANR settings by at least setting a second data
a transfer of digital data through at least a portion of the
pathway.
transfer rate at which digital data is clocked out of the output
Implementations may include, and are not limited to , one
of the digital filter, wherein the second data transfer rate
or more ofthe following features. In the apparatus , it may be 65 differs from the first data transfer rate , and setting a coefficient of the digital filter to convert between the first and
that a plurality of filter routines is stored within the storage
second data transfer rates
that defines the plurality of types of digital filter; each filter

US 8,073 ,151 B2
5

6

ears. As will als 'O be explained in greater deta泣， the pers 'Onal
ANR device 1000 may have any 'O f a number 'O f physical
c 'Onfigurati'O郎， s'O me p 'O ssible 'O nes 'O f which are depicted in
DESCRIPTION OF THE DRAWINGS
FIGS. 2a thr'Ough 2f S'O me 'O fthese depicted physical c'O n5 figurati 'O ns inc 'O rp 'O rate a single earpiece 100 t 'O pr'OvideANR
FIG.1 is a bl 'O ck diagram 'O fp 'O rti 'O ns 'O fanimplementati 'O n
t 'O 'Only 'One 'O fthe user's ears , and 'O thers inc 'O rp 'Orate a pair 'O f
'O f a pers 'O nal ANR device.
earpieces 100 t 'O provide ANR t 'O b 'O th 'O f the user' s ears
FIGS-hthroughzfdepict possible physical conagum-However, it should be noted that forthe sake ofsimplicity of
tions ofthe personal ANR device o f F I G . 1 . d i s c u s s i o n, only a single earpiece 100is depicted and
FIGS-hand3bdepictPOSSIble Internal architectures ofan lodescribed in relation to FIG.1.As will also be explained in
ANR circuit ofthe personal ANR device of F I G 1 . g r e a t e r deta泣， the pers 'O nal ANR device 1000 inc 'O rp 'O rates at
FIGS.4Gthrough4g depict possible signal processmg
least oneANR circuit 2000that may prOVIde mther or both of
t'Op'Ol'Og~e~ ，t~t .m~y be ~~cpt:d by the ANR circuit 'O f the
f~~db:;~k~b~';~dÄNR ~~d~f;~di~~:rd~b~~~dAÑR~"i~~;ddi:
pers 'O nal ANR device 'O f FI G. 1.
ti 'On t 'O p 'O ssibly further providing pass-thr'O ugh audi 'O. FIGS.
FIGS.5αthr'Ough 5e depict p 'O ssible filter bl 'O ck t 'Op 'O l'O gies 15
that may be adopted by theANR circuit ofthe personal ANR3Gand3b depict a couple ofpossible internal architectures of
device ~fFIG. Î.
~
the ANR circuit 2000 that are at least partly dynamically
FIGS.6Gthrough6c depict possible variants of triple-contIgurable Further, FIGS4Gthrough 4E depict some POSE
buffering that may be ad'O pted by the ANR circuit 'O{ the
sible signal processing t 'Op 'O l'O gies and FIGS. 5αthr'Ough 5e
pers 'O nal ANR device 'O f FIG. 1.
20 depict s'Omep 'O ssible filter bl 'O ck t 'O p 'O l 'O gies thatmay theANR
circuit 2000 maybe dynamically c'O nfigured t 'O ad'Opt. Further,
DETAILED DESCRIPTION
the provisi 'O n 'O f either 'Or b 'O th 'O f feedback-based ANR and
feedf'O rward-basedANR is in additi 'On t 'O at least s'Ome degree
What is discl 'O sed and what is claimed herein is intended t 'O
'O f passive n 'O ise reducti 'On (PNR) pr'Ovided by the structure 'O f
be applicable t 'O a wide variety 'O f pers 'O nal ANR devices ，泊， 25 each earpiece 100. Still furtl間， FIGS 如 thr'Ough 6c depict
devices that are structured t 'O be at least partly w 'O m by a user
vari 'O us f'O rms 'O f triple-buffering that may be empl 'Oyed in
m 也e vicinity 'O f at least 'O ne 'O fthe user's ears t 'O pr'OvideANR
dynamically c 'Onfiguring signal processing t 'Op 'O l'O gies , filter
functi 'O nality f 'Or at least that 'O ne ear. It sh'O uld be n 'O ted that
bl 'O ck t 'O p 'O l'O gies and/'O r still 'O ther ANR settings
alth'O ugh vari 'O us specific implementati 'Ons 'O f pers 'O nal ANR
Each earpiece 100 inc 'O中'Orates a casing 11 0 havi月 a
devices , such as headph'O nes , tw 'O -way c 'Ommunicati 'O ns 30 cavity 112 at least partly defined by the casing 110 and by at
headsets , earph'O nes , earbuds , wireless headsets (als 'O kn'Own
least a p 'Orti 'On 'O f an ac 'Oustic driver 190 disp 'O sed within the
casing t 'O ac 'O ustically 'O utput s'O unds t 'O a user's ear. This
as “ earsets") and ear protect'O rs are presented with s'O me
mauner 'O f p 'O siti 'O ning the ac 'O ustic driver 190 als 'O partly
degree 'O f deta泣， such presentati 'Ons 'O f specific implementati 'O ns are intended t 'O facilitate understanding thr'O ugh the use
defines an'O ther cavity 119 within the casing 110 that is sepa'O f examples , and sh'O uld n 'O t be taken as limiting either the 35 rated fr 'O m the cavity 112 by the ac 'O ustic driver 190. The
sc 'O pe 'O f discl 'O sure 'O r the sc 'O pe 'O f claim c 'Overage.
casing 110 carries an ear c 'O upling 115 surr'Ounding an 'O penIt is intended that what is discl 'O sed and what is claimed
ing t 'O the cavity 112 and having a passage 117 that is f'O rmed
herein is applicable t 'O pers 'Onal ANR devices that pr'Ovide
tl宜。ugh the ear c 'O upling 115 and that c 'O mmunicates with the
tw 'O -way audi 'O c'O mmunicati 'O ns , 'One-way audi 'O c 'O mmuni'O pening t 'O the cavity 112. In s 'O me implementati 'Ons , an
cati 'O ns (i.e. , ac 'O ustic 'O utput 'O f audi 'O electronically provided 40 ac 'O ustically transparent screen, grill 'Or 'O ther f 'Orm 'O f perf'Oby an'O ther device) , 'O r n 'O c'O mmunicati 'O ns , at all. It is
rated panel (n'O t sh'Own) may be p 'O siti 'O ned in 'Or near the
passage 117 in a manner that 'O bscures the cavity and/'O r the
intended that what is discl 'O sed and what is claimed herein is
applicable t 'O pers 'O nal ANR devices that are wirelessly c'O npassage 117 企'Om view f 'Or aesthetic reas 'Ons and/'O r t 'O protect
c 'Omp 'O nents within the casing 110 from damage. At times
nected t 'O 'Other devices , that are c 'Onnected t 'O 'Other devices
thr'Ough electrically and/'O r 'O ptically c'O nductive cabling, 'O r 45 when the earpiece 100 is w 'O m by a user in the vicinity 'O f 'O ne
that are n 'O t c 'Onnected t 'O any 'O ther device , at al l. It is intended
'O f the user' s ears , the passage 117 ac 'O ustically c 'O uples the
cavity 112 t 'O the ear canal 'O f that ear, while the ear c 'O upling
that what is discl 'O sed and what is claimed herein is applicable
t 'O pers 'Onal ANR devices having physical c 'Onfigurati 'O ns
115 engages p 'O rti 'O ns 'O fthe ear t 'O f'O rm at least s'O me degree
structured t 'O be w 'O rn in the vicinity 'O f either 'O ne 'O r b 'Oth ears
'O f ac 'O ustic seal therebetween. This ac 'O ustic seal enables the
'O f a user, including and n 'O t limited t 'O, headph'O nes with either 50 casing 11 0, the ear c'O upling 115 and p 'O rti 'O ns 'O f the user' s
'O ne 'Or tw 'O earpieces , 'Over-the-head headph'O nes , behind-thehead surrounding the ear canal (including p 'Orti 'Ons 'O f the ear)
neck headph'O nes , headsets with c 'Ommunicati 'O ns microt 'O c 'O'O perate t 'O ac 'O ustically is 'O late the cavity 112 , the passage
ph'Ones (e 皂， b 'O'O m microph'O nes) , wireless headsets (泊
117 and th已開r canal 企'Om the environment extemal t 'O the
earsets) , single earph'O nes 'Or pairs 'O f earph'Ones , as well as
casing 11 0 and the user' s head t 'O at least s'Ome degree , thereby
hats 'O r helmets inc 'O rp 'O rating 'O ne 'O r tw'O earpieces t 'O enable 55 providing s'O me degr伐。 fPNR.
audi 'O c 'O mmunicati 'Ons and/'O r ear protecti 'O n. Still 'O ther
In s'O me variati 'O ns , the cavity 119 may be c 'Oupled t 'O the
physical c 'Onfigurati 'O ns 'O f pers 'O nal ANR devices t 'O which
environment external t 'O the casing 11 0 via 'O ne 'Or m 'O re ac 'Oustic p 'O rts ('O nly 'O ne 'O f which is sh'Own) , each tuned by their
what is discl 'O sed and what is claimed herein are applicable
will be apparent t 'O th'O se skilled in the art.
dimensi 'O ns t 'O a selected range 'O f audible frequencies t 'O
Bey'O nd pers 'O nal ANR devices , what is discl 'O sed and 60 enhance characteristics 'O f the ac 'Oustic 'Output 'O f s'Ounds by
the ac'Ou的c driver 190 in a manner readily rec 'O gnizable t 'O
claimed herein is als 'O meant t 'O be applicable t 'O the pr'Ovisi 'O n
'O fANR inrelatively small spaces in whicha pers 'O nmay sit 'O r
th'O se skilled in the art. AIs 'O, in s'O me variati 'Ons , 'O ne 'Or m 'O re
stand, including and n 'Ot limited t 'O, ph'O ne b 'O'O ths , car passentuned p 'O rts (n'O t sh'Own) may c'O uple the cavities 112 and 119 ,
ger cabins , etc.
and/'O r may c 'Ouple the cavity 112 t 'O the envir'O nment extemal
FIG. 1 pr'Ovides a bl 'O ck diagram 'O f a pers 'O nal ANR device 的 t'O the casing 110. Alth'O ugh n 'Ot specifically depicted , screens ,
1000 structured t 'O be w 'O rn by a user t 'O provide active n 'O ise
grills 'O r 'O ther f 'Orms 'O f perf'O rated 'Or fibr 'Ous structures may be
reducti 'O n (ANR) in the vicir世ty 'O f at least 'O ne 'O f the user' s
p 'O siti 'O ned within 'O ne 'O r m 'O re 'O f such p 'O rts t 'O prevent pasOther features and advantages 'O f the inventi 'O n will be
apparent from the descripti 'O n and claims that f'O ll 'Ow.

e

US 8,073 ,151 B2
7

8

sage of debris or other contaminants therethrough and/or to
In some implementations providing pass-through audio ,
provide a selected degree of acoustic resistance therethrough.
the ANR circuit 2000 is also coupled to an audio source 9400
In implementations providing feedforward-based ANR, a
to receive pass-through audio from the audio source 9400 to
feedforward microphone 130 is disposed on the exterior of
be acoustically output by the acoustic driver 190. The passthe casing 110 (oron some otherportionofthe personalANR 5 tl宜。ugh audio , unlike the noise sounds emitted by the acousdevice 1000) in a manner that is acoustically accessible to the
t~c noise sourc.e 9900 , is .audio that a user ofthe personal ANR
EIWironment external to the casing 110.This external pOBi-device 1000desires to hear.Indeed , the user may wear the
tiomng ofthe feedforward microphone 130enables the feed-personalANRdevice1000to be ableto hearthepass-throud1
audio without the intrusion of the acoustic noise sonnds. The
forward microphone 130 to detect environmental noise
10 pass-through audio may be a playback of recorded audio ,
sounds , such as those emitted by an acoustic noise source
transmitted audio , or any of a variety of other forms of audio
9900 , 111the mnroIment external to the caSIng110without
that the user desires to hear.In some implementations, the
the e芷ects of any form of PNR or ANR provided by the
audio source 9400 may be incorporated into the personal
personal ANR deVICE1000.As those familIar w1th feedfor-ANR deVICE1000 , iIUhlangmd not linnted t0 , anmtegrated
ward-b~s~d ANR ~ill readily recogni~e~ ~ these sonnds 15 audio playback c~mponent or an integrated audio re~eiver
detected by the fe~df?rward micro~hone 130 are use~ as a
component. In othe; implementation;' the personal ANR
reference from which feedforward anti-noise sonnds are
devi~e 1000 incorporate~ a capability to be -coupled either
derived and then acoustically output into the cavity 112 by the
wirelessly or via mi electrically-or optically condlictive cable
to the audio source 9400 where the audio source 9400 is an
acoustic driver 190. The derivation ofthe feedforward antinoise sounds takes into acconnt the characteristics ofthe PNR 20 entirely separate device from the personal ANR device 1000
(e.g. , a CD player, a digital audio file player, a cell phone ,
provided by the personal ANR device 1000 , characteristics
and position ofthe acoustic driver 190 relative to the feedforetc.).
In other implementations pass-through audio is received
ward microphone 130 , and/or acoustic characteristics ofthe
from a communications microphone 140 integrated into varicavity 112 and/or the passage 117. The feedforward antinoise sounds are acoustically output by the acoustic driver 25 ants of the personal ANR device 1000 employed in two-way
190 with amplitudes and time shifts calculated to acoustically
communications in which the communications microphone
140 is positioned to detect speech sounds produced by the
interact with the noise sonnds of the acoustic noise source
user ofthe personal ANR device 1000. In such implementa9900 that are able to enterinto the cavity 112, the passage 117
and/or an ear canal in a subtractivemannerthat at least attenutions , an attenuated or otherwise modified form ofthe speech
30 sounds produced by the user may be acoustically output to
ates them.
one or both ears ofthe user as a commnnications sidetone to
In implementations providing feedback-based ANR, a
feedback microphone 120 is disposed within the cavity 112.
enable the user to hear their own voice in a marmer substanThe feedback microphone 120 is positioned in close proximtially similar to how they normally would hear their own
voice when not wearing the personal ANR device 1000
ity to the opening ofthe cavity 112 and/or the passage 117 so
的 to be positioned close to the entrance of an ear canal when 35
In support ofthe operation of at least theANR circuit 2000 ,
the earpiece 100 is worn by a user. The sounds detected by the
thepersonalANRdevice 1000 may furtherincorporate one or
feedback microphone 120 are used as a reference from which
both of a storage device 170 , a power source 180 and/or a
feedback anti-noise sonnds are derived and then acoustically
processing device (not shown).As will be explainedingreater
output into the cavity 112 by the acoustic driver 190. The
detail , the ANR circuit 2000 may access the storage device
derivation of the feedback anti -noise sounds takes into 40 170 (p erhaps through a digital serial interface) to obtainANR
settings with which to configure feedback-based and/or feedacconnt the characteristics and position ofthe acoustic driver
forward-based ANR. As will also be explained in greater
190 relative to the feedback microphone 120 , and/or the
acoustic characteristics of the cavity 112 and/or the passage
detail , the power source 180 may be a power storage device of
117, as well as considerations that enhance stability in the
limited capacity (e. 皂， a ba前ery)
provision of feedback-based ANR. The feedback anti-noise 的
FIGS. 2a through 2fdepict various possible physical configurations that may be adopted by the personal ANR device
sounds are acoustically output by the acoustic driver 190 with
amplitudes and time shifts calculated to acoustically interact
1000 ofFIG. 1. As previously discussed, different implementations of the personal ANR device 1000 may have either one
with noise sounds of the acoustic noise source 9900 that are
ortwo earpieces 100 , andare structured to be wornon or near
able to enter into the cavity 112, the passage 117 and/or the
ear canal (and that have not been attenuated by whatever 50 a user' s head in a manner that enables each earpiece 100 to be
PNR) in a subtractive manner that at least attenuates them.
positioned in the vicinity of a user's ear.
The personal ANR device 1000 臼rther incorporates one of
FIG. 2a depicts an “ over-the-head" physical configuration
theANRcircuit 2000 associated with each earpiece 100 ofthe
1500a of the personal ANR device 1000 that incorporates a
personal ANR device 1000 such that there is a one-to-one
pair of earpieces 100 that are each in the form of an earCl巾，
correspondence ofANR circuits 2000 to earpieces 100. Either 55 and that are connected by a headband 102. However, and
although not specifically depicted, an alternate variant of the
a portion of or substantially all of eachANR circuit 2000 may
be disposed within the casing 11 0 of its associated earpiece
physical configuration 1500a may incorporate only one ofthe
100. Alternatively and/or additionally, a portion of or substanearpieces 100 connected to the headband 102. Another alternate variant of the physical configuration 1500a may replace
tially all of each ANR circuit 2000 may be disposed within
another portion ofthe personal ANR device 1000. Depending 60 the headband 102 with a different band structured to be worn
on whether one or both offeedback-basedANR and feedforaronnd the back ofthe head and/or the back ofthe neck of a
ward-basedANR are provided in an earpiece 100 associated
user.
with the ANR circuit 2000 , the ANR circuit 2000 is coupled
In the physical configuration 1500a , each of the earpieces
to one or both ofthe feedback microphone 120 and the feed100 maybe either an “ on-ear" (also commonly called “ supraforward microphone 130 , respectively. TheANR circuit 2000 的 aural") or an “ around-ear" (also commonly called “ clrcumis further coupled to the acoustic driver 190 to cause the
aural") form of earCl中， depending on their size relative to the
pinna of a typical human ear. As previously discussed, each
acoustic output of anti -noise sonnds.

US 8,073 ,151 B2

9

10

earpiece 100 has the casing 110 in which the cavity 112 is
the ear c'O upling 115 is in the f 'O rm 'O f a substantially h 'O ll 'Ow
f 'Ormed, and that 11 0 carries the ear c 'Oupling 115. In this
tube-like shape defining the passage 117 that c 'Ommunicates
with the cavity 112. In s'O me implementati 'Ons , the ear c'O uphysical c'O nfigurati 'O n , the ear c 'Oupling 115 is in the f 'Orm 'O f
a f1 exible cushi 'On (p 'O ssibly ring-shaped) that surrounds the
pling 115 is f 'Ormed 'O f a material distinct fr 'Om the casing 110
periphery 'O f the 'O pening int'O the cavity 112 and that has the 5 (p'O ssibly a material that is m 'O re f1 exible than that from which
the casing 11 0 is f 'O rmed) , and in 'Other implementati 'O ns , the
passage 117 f'O rmed th的加'Ough that c 'Ommunicates with the
ca:~~ 112;
.~~
ear c 'OupÜng 115 is f 'Ormed integrally with the casing 11 0
where the earpieces100are structuredto be wom as over-Portions ofthe casing 110and/or ofthe ear coupling 115
the-ear earcups , the caSIng110and the ear coupling115cooperate to engage portions of the concha andor the ear
c 'O'O perate t 'O substantially surr'O und the pinna 'O f an ear 'O f a 10
canal 'O f a user's ear t 'O enable the casing 110 t 'O rest in the
user Thus , when such a varmIHof the personal ANR device
VICiIUty ofthe eIHra1ce ofthe ear canal m an orientat1on that
1000 is c 'O rrectly w 'O rn, the headband 102 and the casing 110
ac 'O ustically c 'O uples the cavity 112 with the ear canal thr'O ugh
c 'O'O perate t 'O press the ear c 'Oupling 115 against p 'O rti 'O ns 'O f a
the ear c'O叩li月 115. Th恥 when the earpiece 100 is pr'Operly
side 'Oftl叭肘r's h臼d surr'Oundi時 the pi~~ 'O f ~ ear s~~h
that the pinna is substantially hidden fr~m view. Where the 15 p'Ositi'On:~， the entrance t 'O the ear canal is substantially
earpieces 100 are structured t 'O bew 'O m as 'O n-ear earcups , the
“ plugged" t 'O create the previ 'O usly discussed ac 'O ustic seal t'O
casl月 110 a吋 ear c'Oupli月 115 c 'O'O perate t 'O 'Overlie periphenable 吐le provisi 'O n 'O f PNR.
FIG. 2d depicts an'O ther in-ear physical c'O nfigurati 'On
eral p 'O rti 'O ns 'O f a pi uiJ.a that surroimd the entranc~ 'O{ an
1500d 'O fthe pers 'O nal ANR device 1000 that is substantially
ass 'O ciated ear canal. Thus , when c'O rrectly w 'Orn , the headband 102 and the casing 110 c'O'O perate t 'O press the ear c'O u- 20 similar t 'O the physical c'O nfigurati 'On 1500c, but in which 'O ne
pling 115 againstp 'O rti 'O ns 'O fthe pinna ina mannerthat likely
'O f the earpieces 100 is in the f'O rm 'O f a single-ear headset
leaves p 'O rti 'O ns 'O f the periphery 'O f the pinna visible. The
(s 'O metimes als 'O called an “ earset") that additi 'O nally inc 'O rp 'Orates a c'O mmunicati 'O ns micr'Oph'One 140 disp 'O sed 'O n the
pressing 'O f the f1exible material 'O f the ear c 'O upling 115
casing 110. When this earpiece 100 is c'O rrectly w 'O m , the
against eitherp 'O rti 'O ns 'O f a pinna 'O rp 'O rti 'O ns 'O f a side 'O f a head
surrounding a pinna serves b 'Oth t 'O ac 'O ustically c 'Ouple the ear 25 c 'Ommunicati 'O ns micr'Oph'O ne 140 is generally 'Oriented
t 'Owards the vicinity 'O f the m 'O uth 'O f the user in a manner
canal with the cavity 112 thr'O ugh the passage 117, and t 'O
ch'O sen t 'O detect speech s'O unds produced by the user. H 'Owf 'Orm the previ 'O usly discussed ac 'O ustic seal t 'O enable the
provisi 'O n 'O f PNR.
ever, and alth'O ugh n 'Ot specifically depicted, an altemative
FIG. 2b depicts an'Other 'Over-the-head physical c'O nfiguravariant 'O f the physical c 'O nfigurati 'O n 1500d is p 'O ssible in
ti 'O n 1500b that is substantially similar t 'O the physical c'O n- 30 which s'Ounds from the vicinity 'O fthe user's m 'O uth are c'O nveyed t 'O the c'O mmunicati 'O ns micr'Oph'One 140 thr'O ugh a tube
figurati 'O n 1500α ， but in which 'One 'O fthe earpieces 100 addi(n'O t sh'Own) , 'O r in which the c 'O mmunicati 'Ons micr'O ph'O ne
ti 'O nally inc 'O rp 'O rates a c 'Ommunicati 'O ns microph'O ne 140
140 is disp 'O sed 'O n a b 'O'O m (n'O t sh'Own) c 'O nnected t 'O the
c 'Onnected t 'O the casing 110 via a micr'O ph'O ne b 'O'Om 142.
m祖en this particular 'O ne 'O f the earpieces 100 is c 'O叮叮tly
casing 110 and p 'O siti 'O ning the c 'O mmunicati 'Ons micr'O ph'O ne
w 'Orn , the microph'O ne b 'O'Om 142 extends from the casing 110 35 140 in the vicinity 'O fthe user's m 'O uth.
and generally al 'O ngside a p 'O rti 'O n 'O f a cheek 'O f a user t 'O
Alth'O ugh n 'O t specifically depicted in FIG. 2d, the depicted
p 'O siti 'O n the c'O mmunicati 'O ns microph'O ne 140 cl 'O ser t 'O the
earpiece 100 'O fthe physical c'O nfigurati 'O n 1500d having the
m 'O uth 'O fthe user t 'O detect speech s'O unds ac 'O ustically 'Output
c 'Ommunicati 'O ns micr'Oph'O ne 140 may 'O r may n 'O t be acc 'O m企'Om the user's m 'O uth. H 'Owever, and alth'Ough n 'Ot specifipanied by an'O ther earpiece having the f 'O rm 'O f an in-ear
cally depicted, an altemative variant 'O fthe physical c'O nfigu- 40 earph'O ne (such as 'O ne 'O fthe earpieces 100 depicted in FIG.
rati 'O n 1500b is p 'O ssible in which the c 'Ommunicati 'O ns micro2c) that may 'Or may n 'O t be c'O nnected t 'O the earpiece 100
ph'One 140 is m 'O re directly disp 'O sed 'O n the casing 110, and
depicted in FIG. 2dvia a c'O rd 'Or c 'O nductive cabling (als 'O n 'O t
the microph'One b 'O'O m 142 is a h 'O ll 'Ow tube that 'O pens 'On 'O ne
sh'Own)
end in the vicinity 'O f the user' s m 'O uth and 'On the 'O ther end in
FIG. 2e depicts a tw'O -way c 'O mmunicati 'Ons handset physithe vicinity 'O f the c'O mmunicati 'O ns microph'O ne 140 t 'O c'O n- 45 cal c'O nfigurati 'O n 1500e 'O fthe pers 'OnalANR device 1000 that
vey s'O unds from the vicinity 'O fthe user's m 'Outh t 'O the vicininc 'Orp 'Orates a single earpiece 100 that is integrally f 'Ormed
ity 'O fthe c'O mmunicati 'O ns micr'O ph'O ne 140.
with the rest 'O f the handset such that the casing 110 is the
casing 'O fthe handset, and that may 'O r may n 'O t be c 'O nnected
FIG. 2b als 'O depicts the 'Other 'O f the earpieces 100 with
by c 'Onductive cabling (n'O t sh'Own) t 'O a cradle basewith which
broken lines t 'O make clear that still an'O ther variant 'O f the
physical c 'On且gurati'On 1500b 'O f the pers 'Onal ANR device 50 it may be paired. In a manner n 'Ot unlike 'O ne 'O fthe earpieces
1000 is p 'O ssible that inc 'O rp 'O rates 'Only the 'One 'O f the ear100 'O f an 'O n-the-earvariant 'O f either 'O fthe physical c 'O nfigupieces 100 that inc 'O rp 'O rates the micr'O ph'O ne b 'O'O m 142 and
rati 'O ns 1500a and 1500b , the earpiece 100 'O f the physical
the c 'Ommunicati 'Ons microph'One 140. In such an'O ther varic 'Onfigurati 'O n 1500e carries a f 'O rm 'O f the ear c 'Oupling 115
ant , the headband 102 w 'Ould still be present and w 'O uld c'O nthat is c 'O nfigured t 'O be pressed against p 'Orti 'Ons 'O fthe pinna
tinue t 'O be w 'O m 'Over the head 'O f the user.
55 'O f an ear t 'O enable the passage 117 t 'O ac 'O ustically c'O uple the
FIG. 2c depicts an “ in-ear" (als 'O c'O mm'O nly called “ intracavity 112 t 'O an ear canal. In vari 'O us p 'O ssible implementam凹的 physical c'O nfigurati 'On 1500c 'O f the pers 'O nal ANR
ti 'Ons , ear c'O upling 115 may be f'O rmed 'O f a material distinct
device 1000 that inc 'O rp 'O rates a pair 'O f earpieces 100 that are
fr 'O m the casing 110 , 'O r may be f'O rmed integrally with the
casing 110.
each in the f 'O rm 'O f an in-ear earph'O ne, and that may 'O r may
n 'O t be c'O nnected by a c'O rd and/'Or by electrically 'O r 'OpticallyωFIG. 21 depicts an'O ther tw 'O -way c'O mmunicati 'O ns handset
c 'Onductive cabling (n'O t sh'Own). H 'Owever, and alth'O ugh n 'O t
physical c 'O nfigurati 'On 15001 'O f the p位s'Onal ANR device
specifically depicted, an alternate variant 'O fthe physical c 'On1000 that is substantially similart 'O the physical c'O nfigurati 'On
figurati 'O n 1500c may inc 'O rp 'Orate 'Only 'One 'O f the earpieces
1500ε， but in which the casing 11 0 is shaped s'O mewhat m 'O re
100.
appropriately f'O r p 'Ortable wireless c 'O mmunicati 'Ons use , p 'O sAs previ 'O usly discussed, each 'O fthe earpieces 100 has the 65 sibly inc 'Orp 'Orating user interface c 'Ontr'O ls and/'O r display(s)
casing 110 in which the 'O pen cavity 112 is f 'Ormed, and that
t 'O enablethe dialing 'O fph'O nenumbers and/'Orthe selecti 'O n 'O f
carries the ear c'O upling 115. In this physical c 'O nfigurati 'On ,
radi 'O frequency channels with'O ut the use 'O f a cradle base

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FIGS. 3a and 3b depict possible internal architectur郎
eitherofwhichmay be employed by theANR circuit 2000 in
implementations ofthe personal ANR device 1000 in which
the ANR circuit 2000 is at least partially made up of dynami cally configurable digital circuitry. In other words , the internal architectures ofFIGS. 3a and 3b are dynamically con且直
urable to adopt any of a wide variety of signal processing
topologies and filter block topologies during operation of the
ANR circuit 2000. FIGS. 4α-g depict various ex紅nples of
signalprocessingtopologiesthatmaybeadoptedbytheANR
circuit 2000 in this manner, and FIGS. 5a-e depict various
examples offilter block topologies that may also be adopted
by the ANR circuit 2000 for use within an adopted signal
processing topology in this manner. However, and as those
skilled in the art will readily recogn日巴， other implementations ofthe personal ANR device 1000 are possible in which
the ANR circuit 2000 is largely or entirely implemented with
analog circuitry and/or digital circuitry lacking such dynamic
configurability.
In implementations in which the circuitry of the ANR
circuit 2000 is at least partially digital , analog signals representing sounds that are received or output by the ANR circuit
2000 may require conversion into or creation 企om digital
data that also represents those sonnds. More specifically, in
both of the internal architectures 2200a and 2200b , analog
signals received from the feedback microphone 120 and the
feedforward microphone 130 , as well as whatever analog
signal representing pass-through audio may be received 企om
either the audio source 9400 or the communications microphone 140, are digitized by analog-to-digital converters
(ADCs) of the ANR circuit 2000. Also , whatever analog
signal is provided to the acoustic driver 190 to cause the
aωc O us cdnve r 190 tωoaωc O u 叫叩 臼ll yo utput 祖ti-noise sonnds
∞ 叫昀tJ犯 企創 叮
叩
廿
∞ 昀 t lC a 妙 叩叩
叩 St 叫
1 世
叩 叮 伊臼
a nd/o rp as s -也rougl1 audio is created from digital data by a
軒
拉
digital-to-analog converter (DAC) ofthe ANR circuit 2000.
Further, either analog signals or digital data representing
sounds may be manipulated to alter the amplitudes of those
represented sounds by either analog or digital forms , respectJve紗， of variable gain amplifiers (VGAs).
FIG. 3a depicts a possible internal architecture 2200a of
theANR circuit 2000 in which digital circuits that manipulate
digital data representing sounds are selectively interconnected through one or more a叮ays of switching devices that
enable those interconnections to be dynamically con且 gured
during operation of the ANR circuit 2000. Such a use of
switching devices enables pathways for movement of digital
data among various digital circuits to be defined through
programming. More specifically, blocks of digital filters of
varying quantities and/or types are able to be defined through
which digital data associated with feedback-based ANR,
feedforward-basedANR and pass-throughaudio are routed to
perform these functions. In employing the internal architecture 2200a , the ANR circuit 2000 incorporates ADCs 210 ,
310 and 410; a processing device 510; a storage 520; an
interface (I/F) 530; a switch a叮ay 540; a filter bank 550; and
a DAC 910. Various possible variations may further incorporate one or more of analog VGAs 125 , 135 and 145; a VGA
bank 560; a clock bank 570; a compression controller 950; a
further ADC 955; and/or an audio amplifier 960.
The ADC 210 receives an analog signal from the feedback
microphone 120, theADC 310 receives an analog signal 企om
the feedforwardmicrophone 130 , and theADC 410 receives
an analog signal from either the audio source 9400 or the
commnnications microphone 140. As will be explained in
greaterdetail , oneormoreoftheADCs 210 , 310 and410may
receive their associated analog signals through one or more of
the analog VGAs 125 , 135 and 145 , respectively. The digital

of each oftheADCs 210 , 310 and 410 are coupled to
the switch array 540. EachoftheADCs 210 , 310and410may
be designed to employ a variant ofthe widely known sigmadelta analog-to-digital conversion algorithm for reasons of
power conservation and inherent ability to reduce digital data
representing audible noise sounds that might otherwise be
introduced as a result ofthe conversion process. However, as
those skilled in the art will readily recognize , any of a variety
of other analog-to-digital conversion algorithms may be
employed. Further, in some implementations , at least the
ADC 410 may be bypassed and/or entirely dispensed with
where at least the pass-through audio is provided to theANR
circuit 2000 as digital data , rather than as an analog signal.
The filter bank 550 incorporates multiple digital filters ,
each ofwhich has its inputs and outputs coupled to the switch
a叮ay 540. In some implementations , all ofthe digital filters
within the filter bank 550 are of the same type , while in other
implementations , the filter bank 550 incorporates a mixture of
different types of digital filters. As depicted, the filter bank
550 incorporates a mixture of multiple downsampling filters
552 , multiple biquadratic (biquad) filters 554 , multiple interpolating filters 556 , and multiple 函lÏte impulse response
(FIR) filters 558 , although other varieties of filters may be
incorporated，的 those skilled in the art will readily recognize
Further，紅nong each of the different types of digital filters
may be digital filters optimized to support different data transfer rates. By way of example , differing ones of the biquad
filters 554 may employ coefficient values of di芷ering bitwidtl芯， or differing ones of the FIR filters 558 may have
differing quantities oftaps. The VGA bank 560 (ifpresent)
incorporates multiple digital VGAs , each of which has its
t he
inputs and outputs coupled to the switch a叮ay 540. Also , 吐旭
DAC 910 haωs its di gita linputc ou 吋 也
挖叩 叫 呻 叫 ∞ 叩 dtωotheswitcha叮a y540
叫
a
1ψple
叮
The clock bank 570 (if present) provides multiple clock signal
outputs coupled to the switch a叮ay 540 that simultaneously
provide multiple clock signals for clocking data between
components at selected data transfer rates and/or other purposes. In some implementations , at least a subset ofthe multiple clock signals are synchronized multiples of one another
to simultaneously support different data transfer rates in different pathways in which the movement of data at those
different data transfer rates in those different pathways is
synchronized
The switching devices of the switch array 540 are operable
to selectively couple different ones of the digital outputs of
the ADCs 210 , 310 and 410; the inputs and outputs of the
digital filters ofthe filter bank 550; the inputs and outputs of
the digital VGAs ofthe VGA bank 560; and the digital input
of the DAC 910 to form a set of interconnections therebetweenthatdefineatopologyofpathwaysforthemovementof
digital data representing various sounds. The switching
devices of the switch a叮叮 540 may also be operable to
selectively couple different ones ofthe clock signal outputs of
theclockbank570todifferentonesofthedigitalfiltersofthe
filter bank 550 and/ordifferent ones ofthe digital VGAs ofthe
VGA bank 560. It is largely in this way that the digital circuitry ofthe internal architecture 2200a is made dynamically
configurable. In this w旬， varying quantities and types of
digital filters and/or digital VGAs may be positioned at various points along different pathways defined for flows of digital data associated with feedback-based ANR, feedforwardbased ANR and pass-through audio to modify sounds
represented by the digital data and/or to derive new digital
data representing new sonnds in each of those pathways.
Also ， in this way, different data transfer rates may be selected
by which digital data is clocked at different rates in each ofthe
pathways
outputs

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In supp 'Ort 'O f feedback-based ANR , feedf'O rward-based
ANR and/'O r pass-thr'O ugh audi 'O, the c 'Oupling 'O f the inputs
and 'Outputs 'O fthe digital filters within the filter bank 550 t 'O
the switch a叮叮 540 enables inputs and 'O utputs 'O f multiple
digital filters t 'O be c 'O upled thr'Ough the switch array 540 t 'O
create bl 'O cks 'O ffilters. As th'O se skilled in the art will readily
rec 'O gnize , by c 'Ombining multiple l'Ower- 'Order digital filters
int 'O a bl 'O ck 'O f filters , multiple l'Ower- 'O rder digital filters may
be caused t 'O c'O'O perate t'O implement higher 'Order functi 'O ns
with'Out the use 'O f a higher- 'O rder filter. Further, in implementati 'O ns having a variety 'O f types 'O f digital filte的， bl 'O cks 'O f
filters may be created that empl 'Oy a mix 'O f filters t'O perf'O rm
a still greater variety 'O f functi 'O ns. By way 'O f example, with
the depicted variety 'O f filters within the filter bank 550 , a filter
bl 'O ck (i.巴， a bl 'O ck 'O f filters) may be created having at least
'O ne 'O f the d 'O wnsampling filters 552 , multiple 'O nes 'O f the
biquad filters 554 , at least 'O ne 'O f the interp 'O lating filters 556 ,
and at least 'One 'O fthe FIR filters 558.
In s'O me implementati 'O ns , at least s'O me 'O f the switching
devices 'O f the switch a叮ay 540 may be implemented with
binary l'O gic devices enabling the switch a叮叮 540 ， itself, t 'O
be used t'O implement basic binary math 'O perati 'O ns t'O create
sUlllilling n 'O des where pathways al 'Ong which di芷erentpieces
'O f digital data fl 'O w are brought t 'O gether in a manner in which
th'O se different pieces 'O f digital data are arithmetically
sUlllilled , averaged , and/'O r 'Otherwise c 'O mbined. In such
implementati 'Ons , the switch array 540 may be based 'O n a
variant 'O f dynamically programmable a叮叮'O fl'O gic devices.
Alternatively and/'O r additi 'O nally, a bank 'O f binary l 'O gic
devices 'O r 'O ther f'O rm 'O f arithmetic l'O gic circuitry (n'O t sh'Own)
may als 'O be inc 'Orp 'O rated int'O the ANR circuit 2000 with the
inputs and 'O utputs 'O fth 'O se binary l'O gic devices and/'Or 'O ther
f 'Orm 'O f arithmetic l 'O gic circuitry als 'O being c'O upled t'O the
switch a叮ay 540.
In the 'O perati 'O n 'O f switching devices 'O f the switch array
540 t'O ad'O pt a t'O p'O l 'O gy by creating pathways f 'Or the fl 'Ow 'O f
data representing s'O unds , pri 'O rity may be given t'O creating a
pathway f 'Or the fl 'Ow 'O f digital data ass 'O ciated with feedbackbased ANR that has as l 'Ow a latency as p'O ssible thr'O ugh the
switching devices. Als 'O, pri 'Ority may be given in selecting
digital filters and VGAs that have as l'Ow a latency as p'O ssible
企'Om am'O ng th'O se available in the filter bank 550 and the
VGA bank 560 , respectively. Further, c 'O efì且cients and/'O r
'O ther settings provided t 'O digital filters 'O f the filter bank 550
that are empl 'O yed in the pathway f 'Or digital data ass 'O ciated
with feedback-based ANR may be adjusted in resp 'O nse t 'O
whatever latencies are incurred 企'Om the switching devices 'O f
the switch array 540 empl 'Oyed in defining the pathway. Such
measures may be taken in rec 'O gniti 'On 'O fthe higher sensitivity
'O f feedback-based ANR t 'O the latencies 'O f c 'O mp 'O nents
empl 'Oyed in perf'Orming the functi 'On 'O f deriving and/'O r
ac 'O ustically 'O utputting feedback anti-n'O ise s'O unds.Alth'O ugh
such latencies are als 'O 'O f c'O ncern in feedf'O rward-basedANR ,
feedf'O rward-based ANR is generally less sensitive t 'O such
latencies than feedback-based ANR. As a result , a degree 'O f
pri 'Ority less than that given t 'O feedback-based ANR , but
greater than that given t'O pass-thr'O ugh audi 'O, may be given t 'O
selecting digital filters and VGAs , and t'O creating a pathway
f 'Or the fl 'Ow 'O f digital data ass 'O ciated with feedf'O rward-based
ANR.
The pr'O cessing device 510 is c 'O upled t 'O the switch a叮ay
540 , as well as t 'O b 'Oth the st 'Orage 520 and the interface 530.
Theprocessing device 510 may be any 'O fa variety 'O ftypes 'O f
processing device , including and n 'O t limited t'O, a general
purp 'O se central pr'O cessing unit (CPU) , a digital signal process 'O r (DSP) , a reduced instructi 'O n set c 'O mputer (RIS C)
process 'O r, a microc 'Ontroller, 'O r a sequencer. The st'O rage 520

may be based 'O n any 'O f a variety 'O f data st'O rage techn'O l 'O gies ,
including andn'O t limited t'O, dynamic rand'O m access mem'O ry
(DRAM) , static rand'O m access mem'O ry (SRAM) , ferr 'Omagnetic disc st'O rage , 'O ptical disc st 'Orage , 'O r any 'O f a variety 'O f
n 'Onv'O latile s'O lid state st 'O rage techn'O l 'O gies. Indeed, the st'O rage 520 may inc 'O rp 'O rate b'O th v 'O latile and n 'O nv'O latile p'O rti 'Ons. Further, it will be rec 'O gnized by th'O se skilled in the art
that alth'O ugh the st 'Orage 520 is depicted and discussed as if it
were a single c'Omp 'One凶， the st'O rage 520 may be made up 'O f
multiple c 'Omp 'Oner恥， p 'O ssibly including a c 'Ombinati 'O n 'O f
v 'O latile and n 'Onv'O latile c'O mp 'Onents. The interface 530 may
supp 'Ort the c 'Oupling 'O f the ANR circuit 2000 t 'O 'O ne 'Or m 'O re
digital c 'Ommunicati 'O ns buses , including digital serial buses
by which the st'O rage device 170 (n'O t t 'O be c 'O nfused with the
st'O rage 520) and/'Or 'Other devices external t 'O the ANR circuit
2000 (e.g. , 'O ther pr'O cessing devices , 'Or 'O ther ANR circuits)
may be c 'Oupled. Further, the interface 530 may pr'Ovide 'O ne 'O r
m 'O re general purp 'O se inputl 'Output (GPIO) electrical c'O nnecti 'Ons and/'Or anal 'O g electrical c'O nnecti 'O ns t'O supp 'O rt the c'O upling 'O f manually- 'Operable c 'O ntrols , indicat'O r lights 'O r 'O ther
devices , such as a p 'Orti 'On 'O fthe p 'Ower s'O urce 180 providing
an indicati 'O n 'O f available p 'Ower.
In s'O me implementati 'O ns , the processing device 510
accesses the st 'O rage 520 t'O read a sequence 'O f instructi 'O ns 'O f
a l'O ading routine 522 , that when executed by the processing
device 510 , causes the pr'O cessing device 510 t 'O 'Operate the
interface 530 t 'O access the st'O rage device 170 t 'O retrieve 'O ne
'O r b 'O th 'O ftheANRr 'O utine 525 and theANR settings 527 , and
t'O st 'O re them in the st'O rage 520. In 'Other implementati 'O ns ,
'O ne 'O r b 'Oth 'O f theANR r 'O utine 525 and the ANR settings 527
are st'O red in a n 'O nv'O latile p 'O rti 'O n 'O fthe st 'Orage 520 such that
they need n 'O t be retrieved fr 'Om the st'O rage device 170 , even
if p 'Ower t'O the ANR circuit 2000 is l 'O st
Regardless 'O fwhether 'O ne 'Or b'O th 'O ftheANR r 'Outine 525
and the ANR settings 527 are retrieved fr 'O m the st'O rage
device 170 , 'O r n 'O t , the processing device 510 accesses the
st'O rage 520 t'O read a sequence 'O f instructi 'O ns 'O f the ANR
routine 525. The pr'O cessing device 510 then executes that
sequence 'O f instructi 'Ons , causing the pr'Ocessi月 device 510
t'O c 'Onfigure the switching devices 'O fthe switch a叮ay 540 t'O
ad'O pt a t 'O p'O l'O gy defining pathways f'O r fl 'Ows 'O f digital data
representing s'O unds and/'O r t 'O pr'Ovide differing cl 'O ck signals
t'O 'One 'O r m 'O re digital filters and/'Or VGAs , as previ 'O usly
detailed. In s'Ome implementati 'Ons , the processing device 510
is caused t'O c'O nfigure the switching devices in a manner
specified by a p'O rti 'O n 'O f the ANR settings 527 , which the
processing device 510 is als 'O caused t'O read fr 'O m the st'O rage
520. Further, the pr'O cessing device 510 is caused t 'O set filter
c 'Oe且cients 'O f vari 'O us digital filters 'O f the filter bank 550 ,
gain settings 'O fvari 'O us VGAs 'O fthe VGA b紅J.k: 560 , and/'O r
cl 'O ck frequencies 'O fthe cl 'O ck signal 'Outputs 'O fthe cl 'O ck bank
570 in a manner specified by a p 'Orti 'On 'O f the ANR settings
527.
In s'O me implementati 'O ns , the ANR settings 527 speci方
multiple sets 'O f filter c'O efficients , gain settings , cl 'O ck frequencies and/'O rc 'O nfigurati 'O ns 'O fthe switchi月 devices 'O fthe
switch array 540 , 'O f which different sets are used in resp 'Onse
t'O di芷erent situati 'Ons. In 'O ther implementati 'O ns , executi 'O n 'O f
sequences 'O f instructi 'Ons 'O f the ANR r 'O utine 525 causes the
processing device 510 t'O derive different sets 'O ffilter c'O efficients , gain settings , cl 'O ck frequencies and/'Or switching
device c 'On且 gurati'Ons in resp 'O nse t'O different situati 'Ons. By
way 'O f example, the pr'O cessing device 510 may be caused t'O
'O perate the interface 530 t 'O m 'O nit 'O r a signal fr 'O m the p 'O wer
s 'Ource 180 that is indicative 'O fthe p 'Ower available from the
p 'Ower s'O urce 180 , and t'O dynamically switch between different sets 'O ffilter c'O e且cients ， gain settin軒， cl 'O ck frequencies

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US 8,073 ,151 B2

15
and/or switching device configurations in response to
changes in the amount of available power.
By way of another example, the processing device 510 may
be caused to monitor characteristics of sounds represented by
digital data involved in feedback-based ANR, feedforwardbasedANR and/or pass-tl宜。ugh audio to determine whether
or not it is desirable to alterthe degree feedback-based and/or
feedforward-based ANR provided. As will be familiar to
those skilled in the art, while providing a high degree ofANR
can be very desirable where there is considerable environmental noise to be attenuated, there can be other situations
where the provision of a high degree of ANR can actually
create a noisier or otherwise more unpleasant acoustic environment for a user of a personal ANR device than would the
provision ofless ANR. Therefore , the processing device 510
may be caused to alter the provision of ANR to adjust the
degree of attenuation and/or the range offrequencies of envi ronmental noise attenuated by the ANR provided in response
to observed characteristics of one or more sounds. Further，的
will also be familiar to those skilled in the a此， where a reduction in the degree of attenuation and/or the range of frequencies is desired, it may be possible to simplify the quantity
and/or type of filters used in implementi月 feedback-based
and/or feedforward-based ANR, and the processing device
510 may be caused to dynamically switch between different
sets offilter coefficients , gain settings , clock frequencies and/
or switching device con且gurations to perform such simpli fYm皂， with the added benefit of a reduction in power consumption.
The DAC 910 is provided with digital data from the switch
a叮叮 540 representing sounds to be acoustically output to an
ear of a user ofthe personal ANR device 1000 , and converts
it to an analog signal representi月 those sounds. The audio
amplifier 960 receives this analog signal from the DAC 910 ,
and amplifies it sufficiently to drive the acoustic driver 190 to
effect the acoustic output of those sounds.
The compression controller 950 (if present) monitors the
sounds to be acoustically output for an indication of their
amplitude being too high, indications of impending instances
of clipping , actual instances of clipping , and/or other impending or actual instances of other audio artifacts. 立起 compression controller 150 may either directly monitor digital data
provided to the DAC 910 or the analog signal output by the
audio amplifier 960 (through the ADC 955 , if present). In
response to such an indication, the compression controller
950 may alter gain settings of one ormore ofthe analog VGAs
125, 135 and 145 (ifpresent); and/or one ormore ofthe VGAs
ofthe VGA bank 560 placed in a pathway associated with one
or more of the feedback-based ANR, feedforward-based
ANR and pass-t趾ough audio functions to adjust amplitude ,
as will be explained in greater detai l. Further, in some implementations , the compression controller 950 may also make
such an a句 ustment in response to receiving an extemal control signal. Such an external signal may be provided by
another component coupled to the ANR circuit 2000 to provide such an extemal control signal in response to detecting a
condition such as an exceptionally loud environmental noise
sound that may cause one or both of the feedback-based and
feedforward-based ANR functions to react unpredictably.
FIG. 3b depicts another possible internal architecture
2200b of the ANR circuit 2000 in which a processing device
accesses and executes stored machine-readable sequences of
instructions that cause the processing device to manipulate
digital data representing sounds in a marmer that can be
dynamically configured during operation of the ANR circuit
2000. Such a use of a processing device enables pathways for
movement of digital data ofa topology to be defined through

16
programming. More specifically, digital filters of varying
quantities and/or types are able to be defined and instantiated
in which each type of digital filter is based on a sequence of
instructions. In employing the intemal architecture 2200b ,
5 the ANR circuit 2000 incorporates the ADCs 210 , 310 and
410; the processing device 510; the storage 520; the interface
530; a directmemory access (DMA) device 540; and the DAC
910. Various possible variations may further incorporate one
or more ofthe analog VGAs 125, 135 and 145; theADC 955;
10 and/or the audio amplifier 960. The processing device 510 is
coupled directly or indirectly via one or more buses to the
storage 520; the interface 530; the Dl\也屯 device 540; the
ADCs 210 , 310 and 410; and the DAC 910 to at least enable
the processing device 510 to control their operation. The
15 processing device 510 may also be similarly coupled to one or
more ofthe analog VGAs 125 , 135 and 145 (ifpresent); and
to the ADC 955 (if present).
As in the intemal architecture 2200a , the processing device
510 may be any of a variety oftypes of processing device , and
20 once again , the storage 520 may be based on any of a variety
of data storage technologies and may be made up of multiple
components. Further, the interface 530 may support the coupling oftheANR circuit 2000 to one or more digital communications buses , and may provide one or more general pur25 pose inputloutput (GPIO) electrical counections and/or
analog electrical connections. The DMA device 540 may be
based on a secondary processing device , discrete digitallogic ,
a bus mastering sequencer, or any of a variety of other technologies
30
Stored within the storage 520 are one or more of a loading
routine 522 , an ANR routine 525 , ANR settings 527 , ANR
data 529 , a downsampling filter routine 553 , a biquad filter
routine 555 , an interpolating filter routine 557 , a FIR filter
routine 559 , and a VGA routine 56 1. In some implementa35 tions , the processing device 510 accesses the storage 520 to
read a sequence ofinstructions ofthe loading routine 522 , that
when executed by the processing device 510 , causes the processing device 510 to operate the interface 530 to access the
storage device 170 to retrieve one or more ofthe ANR routine
的 525 ， the ANR settings 527 , the downsampling filter routine
553 , the biquad filter routine 555 , the interpolating filter routine 557 , the FIRroutine 559 and the VGAroutine 561 , and to
store them in the storage 520. In other implementations , one
or more of these are stored in a nonvolatile portion of the
45 storage 520 such that they need not be retrieved from the
storage device 170.
As was the case in the intemal architecture 2200a , theADC
210 receives an analog signal from the feedback microphone
120 , the ADC 310 receives an analog signal from the feed50 forward microphone 130 , and the ADC 410 receives an analog signal from either the audio source 9400 or the communications microphone 140 (u凶的 s the use of one or more of
the ADCs 210 , 310 and 410 is obviated through the direct
receiptofdigitaldata).Again, oneormoreoftheADCs210 ,
55 310 and 410 may receive their associated analog signals
tl宜。ugh one or more ofthe analog VGAs 125 , 135 and 145 ,
respectively. As was also the case in the intemal architecture
2200a , the DAC 910 converts digital data representing sounds
to be acoustically output to an ear of a user of the personal
ωANR device 1000 into an analog signal , and the audio amplifier 960 ampl泊的 this signal sufficiently to drive the acoustic
driver 190 to effect the acoustic output ofthose sounds.
However, unlike the intemal architecture 2200a where
digital data representing sounds were routed via an array of
65 switching devices , such digital data is stored in and retrieved
from the storage 520. In some implementations , the processing device 510 repeatedly accesses the ADCs 210 , 310 and

US 8,073 ,151 B2

17
410 t 'O retrieve digital data ass 'O ciated with the anal 'O g signals
they receive f'O r st'O rage in the st 'Orage 520 , and repeatedly
retrieves the digital data ass 'O ciated with the anal 'O g signal
'O utput by the DAC 910 from the st 'O rage 520 and provides that
digital data t'O the DAC 910 t 'O enable the creati 'On 'O f that 5
anal 'O g signal.In 'O therimplementati 'Ons , theDMAdevice540
(if present) transfers digital data am'O ng the ADCs 210 , 310
and 410; the st'O rage 520 and the DAC 910 independently 'O f
the pr'O cessing device 510. In still 'Other implementati 'Ons , the . ~
10
ADCs 210 , 310 and410 and/'O rtheDAC 910 inc 'Orp 'O rate “ bus 'v
mastering" capabilities enabling each t'O write digital data t 'O
and/'Or read digital data from the st 'Orage 520 independently 'O f
the processing device 510. The ANR data 529 is made up 'O f
the digital data retrieved fr 'O m the ADCs 210 , 310 and 410 , 15
and the digital data pr'Ovided t'O the DAC 910 by the pr'O cessing device 510 , the Dl\也屯 device 540 and/'O r bus mastering
functi 'O nality.
The d 'Ownsampling filter r 'O utine 553 , the biquad filter routine 555 , the interp 'O lating filter r 'O utine 557 and the FIR filter 20
r 'Outine 559 are each made up 'O f a sequence 'O f instructi 'O ns
that cause the processing device 510 t'O perf'O rm a c 'Ombinati 'O n 'O f calculati 'O ns that define a d 'Ownsampling filter, a
biquad filter, an interp 'O lating filter and a FIR filter, respectively. Further, am 'Ong each 'O f the different types 'O f digital 25
filters may be variants 'O f th'O se digital filters that are 'Optimized f'O r different data transfer rates , including and n 'Ot limited t'O, differing bit widths 'O f c 'O efficients 'O r differing quantities 'O ftaps. Similarly, the VGA routine 561 is made up 'O f a
sequence 'O f instructi 'O ns that cause the processing device 510 30
t'O perf'Orm a c 'Ombinati 'On 'O f calculati 'O ns that define a VGA.
Alth'Ough n 'O t specifically depicted , a summing n 'O de r 'Outine
may als 'O be st'O red in the st 'Orage 520 made up 'O f a sequence
'O f instructi 'O ns that similarly defines a summing n 'O de.
The ANR routine 525 is made up 'O f a sequence 'O f instruc- 35
ti 'O ns that cause the processing device 510 t'O create a signal
processing t'O p 'O l 'O gy having pathways inc 'O rp 'O rating varying
quantities 'O fthe digital filters andVGAs defined by the d'Ownsampling filter routine 553 , the biquad filter routine 555 , the
interp 'O lating filter r 'O utine 557 , the FIR filter routine 559 and 40
the VGA r 'Outine 561 t'O supp 'O rt feedback-basedANR , feedf 'Orward-based ANR and/'O r pass-thr'Ough audi 'O. The ANR
r 'Outine 525 als 'O causes the pr'O cessing device 510 t'O perf'O rm
the calculati 'Ons defining each 'O fthe vari 'Ous filters and VGAs
inc 'O rp 'Orated int'O that t'O p 'O l'O gy. Further, theANR routine 525 45
either causes the processing device 510 t'O perf'O rm the m 'Oving 'O f data am'O ng ADCs 210 , 310 and 410 , the st 'Orage 520
and the DAC 910 , 'O r causes the processing device 510 t'O
c 'O'O rdinate the perf'O rmance 'O f such m 'Oving 'O f data either by
the Dl\也屯 device 540 (if present) 'O r by bus mastering 'Opera- 50
ti 'O ns perf'O rmed by the ADCs 210 , 310 and 410 , and/'O r the
DAC 910.
TheANR settings 527 is made up 'O f data defining t 'Op 'O l'O gy
characteristics (including selecti 'Ons 'O f digital filters) , filter
c 'Oe且cients ， gain settings , cl 'O ck frequencies , data transfer 55
rates and/'Or data sizes. In s'Ome implementati 'O ns , the t'O p 'O l'O gy characteristics may als 'O define the characteristics 'O f any
SUlllilll月 n'Odes t 'O be inc。中'Orated int 'O the t 'Op 'O l'O gy. The
processing device 510 is caused by the ANR routine 525 t'O
empl 'Oy suchdata takenfrom theANRsettings 527 increating 60
a signal processing t 'O p'O l'O gy (including selecting digital filters) , setting the filter c 'O efficients f 'Or each digital filter inc 'Orp 'O rated int'O the t 'Op 'O l'O gy, and setting the gains f'O r each VGA
inc 'O rp 'Orated int'O the t'Op 'Ol 'Ogy. 立le processing device 510
may be further caused by theANR routine 525 t 'O empl 'Oy such 65
data 企'Om the ANR settings 527 in setting cl 'O ck frequencies
and/'Or data transfer rates f 'Or theADCs 210 , 310 and 410; f'O r

18
the digital filters inc 'O rp 'Orated int 'O the t'O p'O l 'O gy; f'O rthe VGAs
inc 'Orp 'Orated int'O the t'O p 'O l'O gy; and f 'Or the DAC 910.
In s'O me implementati 'O ns , the ANR settings 527 speci fY
multiple sets 'O f t 'Op 'O l'O gy characteristics , filter c'O efficier肘，
gain settin軒， cl 'O ck frequencies and/'Or data transfer rates , 'O f
which different sets are used in resp 'O nse t'O different situati 'Ons. In 'O ther implementati 'Ons , executi 'On 'O f sequences 'O f
instructi 'Ons 'O f the ANR routine 525 causes the processing
device 510 t'O derive different sets 'O f filter c'O e且cients ， gain
settings , cl 'O ck frequencies and/'O r data transfer rates f 'Or a
given signal processing t 'O p'O l'O gy in different situati 'Ons. By
way 'O f example, the pr'O cessing device 510 may be caused t'O
'O perate the interface 530 t 'O m 'O nit 'O r a signal fr 'O m the p 'O wer
s'Ource 180 that is indicative 'O fthe p 'Ower available from the
p 'Ower s'Ource 180 , and t'O empl 'Oy different sets 'O ffilter c 'O efficients , gain settings , cl 'O ck frequencies and/'O r data transfer
rates in resp 'O nse t'O changes in the am'O unt 'O f available p 'Ower
By way 'O f an'O ther example, the processing device 510 may
be caused t'O alter the provisi 'On 'O f ANR t 'O adjust the degree 'O f
ANR required in resp 'O nse t 'O 'Observed characteristics 'O f 'O ne
'O r m 'O re s'O unds. Where a reducti 'O n in the degree 'O f attenuati 'On and/'O r the range 'O f frequencies 'O f n 'O ise s'O unds a加nuated is p 'O ssible and/'Or desired , it may be p 'O ssible t 'O simpli fY
the quantity and/'Or type 'O ffilters used in implementing feedback-based and/'O r feedf'O rward-basedANR , and the pr'O cessing device 510 may be caused t'O dynamically switch between
different sets 'O f filter c 'O efì且clen的， gain settings , cl 'O ck frequencies and/'O r data transfer rates t'O perf'O rm such simpli fYing , with the added benefit 'O f a reducti 'On in p 'Ower c 'O nsumpti 'On.
Theref'O re , in executing sequences 'O f instructi 'O ns 'O f the
ANR routine 525 , the pr'O cessing device 510 is caused t'O
retrieve data from the ANR settings 527 in preparati 'O n f'O r
ad'O pting a signal processing t'O p'O l'O gy defining the pathways
t'O be empl 'Oyed by the pr'O cessing device 510 in providing
feedback-based ANR , feedf'O rward-based ANR and passtl宜。ugh audi 'O. The pr'O cessing device 510 is caused t 'O instantiate multiple instances 'O f digital filters , VGAs and/'O r summing n 'O des , empl 'Oying filter c 'O efficien的， gain settings and/'O r
'O ther data fr 'Om theANR settings 527. The pr'O cessing device
510 is then further caused t 'O perf'O rm the calculati 'Ons defining
each 'O fth'O se instances 'O f digital filters , VGAs and summing
n 'O des; t 'O m 'Ove digital data 紅n'Ong th'O se instances 'O f digital
filters , VGAs and summing n 'O des; and t'O at least c 'O'Ordinate
them'Oving 'O fdigital data am'O ngtheADCs 210 , 310 and410 ,
the st 'O rage 520 and the DAC 910 in a mauner that c'O nf'O rms
t'O the data retrieved 企'Om the ANR settings 527. At a subsequent time , the ANR routine 525 may cause the processing
device 510 t'O change the signal processing t'O p 'O l 'O gy, a digital
filter, filter c 'Oe且cients ， gain settings , cl 'O ck frequencies and/
'O r data transfer rates during 'O perati 'O n 'O f the pers 'O nal ANR
device 1000. It is largely in this way that the digital circuitry
'O fthe intemal architecture 2200b is made dynamically c'O nfigurable. Als 'O, in this way, varying quantities and types 'O f
digital filters and/'O r digital VGAs may be p'O siti 'O ned at vari'O US p 'O ints al 'O ng a pathway 'O f a t 'O p 'O l'O gy defined f'O r a fl 'O w 'O f
digital data t'O m 'O di fY s'O unds represented by that digital data
and/'O r t 'O derive new digital data representing new s'O unds , as
will be explained in greater detai l.
In s'Ome implementati 'O ns , the ANR r 'Outine 525 may cause
the processing device 510 t'O give pri 'Ority t'O 'O perating the
ADC 210 and perf'Orming the calculati 'O ns 'O f the digital fil峙的， VGAs and/'O r summing n 'O des p 'O siti 'O ned al 'O ng the pathway defined f'O r the fl 'Ow 'O f digital data ass 'O ciated with feedback-based ANR. Such a measure may be taken in
rec 'O gniti 'O n 'O fthe 1世拉er sensitivity 'O ffeedback-basedANR

US 8,073 ,151 B2

19

20

to the latency between the detection of feedback reference
incorporates one or more ofthe ADCs 210 , 310 , 410 and/or
sounds and the acoustic output offeedback anti-noise sounds.
955; filter blocks 250 , 350 and/or 450; and/or summing nodes
The processing device 510 may be further caused by the
270 and/or 290.
ANR routine 525 to monitor the sounds to be acoustically
Where the provision offeedback-basedANR is supported,
output for indications ofthe amplitude being too high, clip- 5 the ADC 210 receives an analog signal from the feedback
ping , indications of clipping about to occur, and/or other
microphone 120 rel?res~nting feedback _ref~ence ~s~~ds
aud1o art1facts actually occ11rnng or indcatIons of being
detected by the feedback microphone120.The ADC210
about to occur.The processing device510may be caused to
digtizes the analog signal from the feedback microphone
either directly monitor digital data provided to the DAC910120 , md provides feedback reference data correspondmg to
10 the analog signal output by the feedback microphone 120 to
or the analog signal output by the audio amplifier 960
the filter block 250. One or more digital filters within the filter
(through the ADC 955) for such indications. In response to
block 250 are employed to modi fY the data from theADC 210
such an indication, the processing device 510 may be caused
to derive feedback anti-noise data representing feedback antito operate one or more oftIEanalog VGAs125 , 135and14511OISE Sounds The alter block 250provIdes tIEfeedback
to adjust at least one amplitude of an a?~lo~ _~gna.l， an~or 15 anti-noise data to the VGA 280 , pos~ibly through the summay be caused to operate one or more ofthe VGAs based on
ming node270where feedforward-based ANR is also supthe VGA routine 561 and position~d within a pathway of a
port~d.
topology to 吋 ust the amplitude of at least one sound repreWhere the provision of feedforward-based ANR is also
sented by digital data, as will be explained in greater detai l.
supported, the ADC 310 receives an analog signal from the
FIGS.4αthrough 4g depict some possible signal process- 20 feedforward microphone 130 , digitizes it , and provides feedforward reference data corresponding to the analog signal
ing topologies that may be adopted by the ANR circuit 2000
of the personal ANR device 1000 of FIG. 1. As previously
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
discussed, some implementations ofthe personalANR device
employed to modi fY the feedforward reference d伽 received
1000 may employ a variant of the ANR circuit 2000 that is at
least partially progr紅nmable such that the ANR circuit 2000 25 from the ADC 310 to derive feedforward anti -noise data
representing feedforward anti-noise sounds. The filter block
is able to be dynamically configured to adopt different signal
350 provides the feedforward anti-noise data to the VGA 280 ,
processing topologies during operation of the ANR circuit
2000. Altematively, other implementations of the personal
possibly through the summi月 node 270 where feedbackANR device 1000 may incorporate a variant of the ANR
basedANR is also supported.
At the VGA 280 , the amplitude of one or both of the
circuit 2000 that is substantially inalterably structured to 30
adopt one unchanging signal processing topology.
feedback and feedforward anti-noise sounds represented by
the data received by the VGA 280 (either through the sumAs previously discussed, separate ones oftheANR circuit
mi月 node 270 , or not) may be altered underthe control ofthe
2000 are associated with each earpiece 100, and therefore ,
implementations ofthe personal ANR device 1000 having a
compression controller 950. The VGA 280 outputs its data
pair ofthe earpieces 100 also incorporate a pair ofthe ANR 35 (with or without amplitude alteration) to the DAC 910 , poscircuits 2000. However, as those skilled in the art will readily
sibly through the summing nodes 290 where talk-through
audio is also supported.
recognize , other electronic components incorporated into the
personal ANR device 1000 in support of a pair of the ANR
In some implementations where pass-through audio is supcircuits 2000 , such as the power source 180 , may not be
ported, the ADC 410 digitizes an analog signal representing
duplicated. Forthe sake of simplicity of discussion and under- 的 pass-through audio received from the audio source 9400 , the
communications microphone 140 or another source and prostanding , signal processing topologies for only a singleANR
vides the digitized result to the filter block 450. In other
circuit 2000 are presented and discussed in relation to FIGS.
4α -g.
implementations where pass-tl宜。ugh audio is supported, the
audio source 9400 , the communications microphone 140 or
As also previously discussed, different implementations of
the personal ANR device 1000 may provide only one of either 的 another source provides digital data representing passthrough audio to the filter block 450 without need of analogfeedback-based ANR or feedforward-based ANR, or may
to-digital conversion. One or more digital filters within the
provide both. Further, di芷erent implementations may or may
filter block 450 are employed to modify the digital data repnot additionally provide pass-tl宜。ugh audio. Therefore ,
although signal processing topologies implementing all three
resenting the pass-through audio to derive a modified variant
of feedback-based ANR, feedforward-based ANR and pass- 到 of the pass-through audio data in which the pass-through
audio may be re-equalized and/or enhanced in other ways.
through audio are depicted in FIGS. 4α哼， it is to be underThe filter block 450 provides the pass-through audio data to
stood that variants of each of these signal processi月 topologies are possible in which only one or the other ofthese two
the summing node 290 where the pass-tl宜。ugh audio data is
forms of ANR is provided, and/or in which pass-through
combined with the data being provided by the VGA 280 to the
audio is not provided. In implementations in which theANR 55 DAC 910.
The analog signal output by the DAC 910 is provided to the
circuit 2000 is at least partially progr紅nmable ， which ofthese
audio amplifier 960 to be 紅npli自己，d sufì且ciently to drive the
two forms of ANR are provided and/or whether or not both
forms of ANR are provided may be dynamically selectable
acoustic driver 190 to acoustically output one or more of
during operation ofthe ANR circuit 2000.
feedback anti-noise sounds , feedforward anti-noise sounds
FIG. 4a depicts a possible signal processing topology ωand pass-through audio. The compression controller950 con2500αfor which the ANR circuit 2000 may be structured
trolsthegainoftheVGA280toenablethe 紅nplitude of sound
and/or programmed. Where the ANR circuit 2000 adopts the
represented by data output by one or both of the filter blocks
signal processing topology 2500a , the ANR circuit 2000
250 and 350 to be reduced in response to indications of
incorporates at least the DAC 910 , the compression controller
impending instances of clipping , actual occurrences of clip950 , and the audio amplifier 960. Depending , in part on 65 ping and/or other undesirable audio artifacts being detected
bythecompressioncontroller950. Thecompressioncontrolwhether one or both of feedback-based and feedforwardler 950 may either monitor the data being provided to the
based ANR are supported, the ANR circuit 2000 further

US 8,073 ,151 B2

21
DAC 910 by the summing node 290 , or may monitor the
analog signal output of the audio amplifier 960 through the
ADC 955.
As further depicted in FIG. 4a , the signal processing topology 2500a defines multiple pathways along which digital 5
data associated with feedback-based ANR, feedforwardbased ANR and pass-through audio flow. Where feedbackbasedANR is supported, the flow offeedback reference data
and feedback anti -noise data among at least the ADC 210 , the
filter block 250 , the VGA 280 and the DAC 910 defines a 10
feedback-basedANR pathway 200. Similarly, where feedforward-based ANR is supported, the flow of feedforward reference data and feedforward anti-noise data among at least
theADC 310 , the filter block 350 , the VGA 280 and the DAC
910 defines a feedforward-basedANR pathway 300. Further, 15
where pass-through audio is supported, the flow of passthrough audio data and modified pass-through audio data
among at least theADC 410 , the filter block 450 , the summing
node 290 and the DAC 910 defines a pass-through audio
pathway 400. Where both feedback-based and feedforward- 20
based ANR are supported, the pathways 200 and 300 both
further incorporate the sunmIÏng node 270. Further, where
pass-tl宜。ugh audio is also supported勻 the pathways 200 and/
or 300 incorporate the summi月 node 290.
In some implementations , digital data representing sounds 25
may be clocked through all ofthe pathways 200 , 300 and 400
that are present at the same data transfer rate. Thus , where the
pathways 200 and 300 are combined at the summing node
270 , and/or where the pathway 400 is combined with one or
both ofthe pathways 200 and 300 at the sunmIÏng node 400 , 30
all digital data is clocked through at a common data transfer
rate, and that common data transfer rate may be set by a
common synchronous data transfer clock. However, as is
known to those skilled in the art and as previously discussed,
the feedforward-based ANR and pass-through audio func- 35
tions are less sensitive to latencies than the feedback-based
ANR function. Further, the feedforward-based ANR and
pass-tl宜。ugh audio functions are more easily implemented
with su且ciently high quality of sound with lower data sampling rates than the feedback-basedANR function. Therefore ，的
in other implementations , portions ofthe pathways 300 and/
or 400 may be operated at slower data transfer rates than the
pathway 200. Preferably, the data transfer rates of each ofthe
pathways 200 , 300 and 400 are selected such that the pathway
200 operates with a data transfer rate that is an integer mul- 的
tiple of the data transfer rates selected for the portions of the
pathways 300 and/or 400 that are operated at slower data
transfer rates.
By way of example in an implementation in which all three
of the pathways 200 , 300 and 400 are present, the pathway 50
200 is operated at a data transfer rate selected to provide
sufì且ciently low latency to enable sufì且ciently 1世拉 quality of
feedback-basedANR that the provision ofANR is not unduly
compromised (e.g. , by having anti-noise sounds out-of-phase
with the noise sounds they are meant to attenuate , or instances 55
of negative noise reduction such that more noise is actually
being generated than a加nuated， etc.) , and/or sufficiently
high quality of sound in the provision of at least the feedback
anti-noise sounds. Meanwhile , the portionofthepathway 300
from theADC 310 to the summing node 270 and the portion 60
ofthe pathway 400 from the ADC 410 to the sunmIÏng node
290 are both op位ated at lower data transfer rates (eith位 the
S紅ne lower data transfer rates or different ones) that still also
enablesu且ciently high quality offeedforward-basedANR in
the pathway 300 , and sufficiently 1可h quality of sound in the 65
provision ofthe feedforward anti-noise through the pathway
300 and/or pass-through audio through the pathway 400.

22
Inrecognitionofthelikelihoodthatthepass-tl宜。ughaudio

function may be even more tolerant of a greater latency and a
lower sampling rate than the feedforward-based ANR function, the data transfer rate employed in that portion of the
pathway 400 may be stilllower than the data transfer rate of
that portion ofthe pathway 300. To support such differences
in transfer rates in one variation, one or both ofthe summing
nodes 270 and 290 may incorporate sample-and-hold, buffering or other appropriate functionality to enable the combining of digital data received by the summing nodes 270 and
290 at different data transfer rates. This may entail the provision oftwo different data transfer clocks to each ofthe summing nodes 270 and 290. Alternative紗， to support such differences in transfer rates in another variation, one or both of
the filter blocks 350 and 450 may incorporate an upsampling
capability (p erhaps through the inclusion of an interpolating
filter or other variety of filter incorporating an upsampling
capability) to increase the data transfer rate at which the filter
blocks 350 and 450 provide digital data to the summing nodes
270 and 290 , respectively, to match the data transfer rate at
which the filter block 250 provides digital data to the summing node 270 , and subsequently, to the sunmIÏng node 290.
It may be that in some implementations , multiple power
modes may be supported in which the data transferrates ofthe
pathways 300 and 400 are dynamically altered in response to
the availability of power from the power source 180 and/or in
response to changing ANR requirements. More specifically,
the data transfer rates of one or both ofthe pathway 300 and
400 up to the points where they are combined with the pathway 200 may be reduced in response to an indication of
diminishing power being available from the power supply
180 and/orinresponsetotheprocessingdevice510 detecting
characteristics in sounds represented by digital data indicating that the degree of attenuation and/or range of frequencies
of noise sounds attenuated by the ANR provided can be
reduced. In making determinations of whether or not such
reductions in data transfer rates are possible, the processing
device 510 may be caused to evaluate the e芷ects of such
reductions in data transfer rates on quality of sound through
one or more of the pathways 200 , 300 and 400 , and/ or the
quality of feedback-based and/or feed-forward based ANR
provided.
FIG. 4b depicts a possible signal processing topology
2500b for which the ANR circuit 2000 may be structured
and/or programmed. \\屯ere the ANR circuit 2000 adopts the
signal processing topology 2500b , the ANR circuit 2000
incorporates at least the DAC 910 , the audio amplifier 960 ,
theADC 210 , a pairofsummingnodes 230 and270 , anda pair
of filter blocks 250 and 450. The ANR circuit 2000 may
further incorporate one or more of the ADC 410 , the ADC
310 , a filter block 350 and a sunmIÏng node 370.
TheADC 210 receives and digitizes an analog signal from
the feedback microphone 120 representing feedback reference sounds detected by the feedback microphone 120 , and
provides corresponding feedback reference data to the summing node 230. In some implementations , theADC 410 digitizes an analog signal representing pass-through audio
received from the audio source 9400 , the communications
microphone 140 or another source and provides the digitized
result to the filter block 450. In other implementations , the
audio source 9400 , the communications microphone 140 or
another source provides digital data representing passthrough audio to the filter block 450 without need of analogto-digital conversion. One or more digital filters within the
filter block 450 are employed to modify the digital data representing the pass-tl宜。ugh audio to derive a modified variant
of the pass-through audio data in which the pass-through

US 8,073 ,151 B2

23

24

audio may be re-equalized and/or enhanced in other ways.
acoustic driver 190 to acoustically output one or more of
One or more digital filters within the filter block 450 also
feedback anti-noise sounds , feedforward anti-noise sounds
function as a crossoverthat divides the modified pass-through
and pass-through audio.
audio data into higher and lower frequency sounds , with data
As further depicted in FIG. 4b , the signal processing topolrepresenting the higher frequency sounds being output to the 5 ogy 2500b defines its own variations ofthepathways 200 , 300
summing node 270 , and data representing the lower freand 400 along which digital data associated with feedbackquency sounds being output to the summi月 node 230. In
based ANR, feedforward-based ANR and pass-through
various implementations , the crossover frequency employed
audio , respectively, flow. In a mauner not unlike the pathway
in the filter block 450 is dynamically selectable during opera- . ~ 200 of the signal processing topology 2500a , the flow of
10
tion of the ANR circuit 2000 , and may be selected to effec- 'v feedback reference data and feedback anti-noise data among
tively disable the crossover function to cause data representtheADC 210 , the summing nodes 230 and270 , the filter block
ing all frequencies of the modified pass-tl宜。ugh audio to be
250 and the DAC 910 defines the feedback-basedANR pathoutputto eitherofthe summingnodes 230 or270. In this way,
way 200 of the signal processing topology 2500b. Where
the point at which the modified pass-through audio data is 15 feedforward-basedANR is supported, in a mauner not u凶 ike
combined withdata forthe feedbackANR function within the
the pathway 300 ofthe signal processing topology 2500α ， the
signal processing topology 2500a can be made selectable.
flow of feedforward reference data and feedforward antiAs just discussed, feedback reference data from the ADC
noise data among the ADC 310 , the filter block 350 , the
210 may be combined with data 企om the filter block 450 for
summing nodes 270 and 370 , and the DAC 910 defines the
the pass-t尬。ugh audio function (either the lower frequency 20 feedforward-based ANR pathway 300 ofthe signal processsoun白， or all of the modified pass-through audio) at the
ing topology 2500b. However, in a marmer very much u凶 ike
summing node 230. The summing node 230 outputs the posthe pathway 400 ofthe signal processing topology 2500α ， the
sibly combined data to the filter block 250. One or more
abilityofthefilterblock4500fthesignalprocessingtopology
digital filters within the filter block 250 are employed to
2500b to split the modified pass-through audio data into
modi fY the data from summing node 230 to derive modified 25 higher frequency and lower frequency SOUI由 results in the
data representing at least feedback anti-noise sounds and
pathway 400 ofthe signal processing topology 2500b being
padially split.More speciacally, the How ofdigital data from
possibly aIrther-Inodiaed pass-through audio sounds-The
alter block 250provides the Inodiaed data to the smm111ng
the ADC410to the alter block 450is split at the alter block
node 270.The smmning node270combmes the data fromthe450.One spl1t port1on of the pathway400continues to the
alter block 450that possibly represents higher frequency 3Osmm111ng node230 , where it is combmed w1th tIEpathway
sounds of the modified pass-through audio with the modified
200 , before continui月 through the filter block 250 and the
data from the filter block 250 , and provides the result to the
ing node 270 , and ending at the DAC 910. The other
DAC 910 to create an analog signal. The provision of data by
the alter block 450to the s1HIHnIng node270Inay be through
split portion of the pathway400continues to the sUHHning
the summing node 370where the provision offeedforward-35node 370(ifpresent), where it is combinedwith the pathway
based ANR is also supported.
~ ~~ (if ~res~~t) ， bef?re:~n!i~~~ng through the summing node
Where the crossov~r~frequency employed in the filter block
270 ~nd endi~~ at the DAC 910
450 is dynamically select a""b le , ~ario~s ~haracteristics of the
Also not unlike thepathways 200 , 300 and400 ofthe signal
processing topology 2500α， thepathways 200 , 300 and400 of
alters maKIng up thealterblock450may also be dynamically
configurable. By way of example, the number and/or type of 40 the signal processing topology 2500b may be operated with
digital filters making up the filter block 450 may be dynamidifferent data transfer rates. However, differences in data
transfer rates between the pathway 400 and both ofthe pathcally alterable , as well as the coefficients for each of those
digital filters. Such dynamic configurability may be deemed
ways 200 and 300 would have to be addressed. Sample-andhold, buffering or other functionality may be incorporated
desirable to correctly accommodate changes 紅nong having
no data from the filter block 450 being combined with feed- 45 into each ofthe summing nodes 230 , 270 and/or 370. Alternatively and/or additional紗， the filter block 350 may incorbackreference data from theADC 210 , having data from the
filter block 450 representing lower frequency sounds being
porateinterpolationorotherupsamplingcapabilityinproviding digital data to the summing node 370 , and/or the filter
combined with feedback reference data from the ADC 210 ,
block 450 may incorporate a similar capability in providing
and having data representing all ofthe modified pass-through
audio from the filter block 450 being combined with feedback 50 digital data to each of the summing nodes 230 and 370 (or
reference data from the ADC 210.
270 , ifthe pathway 300 is not present).
Where the provision of feedforward-based ANR is also
FIG. 4c depicts another possible signal processing topolsupported, the ADC 310 receives an analog signal from the
ogy 2500c for which the ANR circuit 2000 may be structured
feedforwardmicrophone 130, digitizes 泣， and provides feedand/or programmed. \\屯ere the ANR circuit 2000 adopts the
forward reference data corresponding to the analog signal 55 signal processing topology 2500c , the ANR circuit 2000
incorporates at least the DAC 910 , the audio amplifier 960 ,
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
theADC 210 , the summing node 230 , the filter blocks 250 and
employed to modify the feedforward reference data received
450 , the VGA 280 , another summing node 290 , and the comfrom the ADC 310 to derive feedforward anti-noise data
pressor 950. The ANR circuit 2000 may further incorporate
representing feedforward anti-noise sounds. The filter block ωone or more ofthe ADC 410 , the ADC 310 , the filter block
350 provides the feedforward anti-noise data to the summing
350 , the summing node 270 , and the ADC 955. The signal
node 370 where the feedforward anti-noise data is possibly
processing topologies 2500b and 2500c are similar in numercombined with data that may be provided by the filter block
ous ways. However, a substantial difference between the sig450 (eitherthe higher frequency sounds , or all ofthe modified
nal processing topologies 2500b and 2500c is the addition of
pass-through audio).
的 the compressor 950 in the signal processing topology 2500c
The analog signal output by the DAC 910 is provided to the
to enable the 紅nplitudes of the sounds represented by data
output by both of the filter blocks 250 and 350 to be reduced
audio amplifier 960 to be amplified sufficiently to drive the

US 8,073 ,151 B2

25

26

in response to the compressor 950 detecting actual instances
incorporates at least the DAC 910; the audio amplifier 960;
or indications of impending instances of clipping and/or other
the ADCs 210 and 310; the summing nodes 230 , 270 and 370;
undesirable audio artifacts.
the filter blocks 250 , 350 and 450; the compressor 950; and a
The filter block 250 provides its modified data to the VGA
pairofVGAs 240 and 340. TheANR circuit 2000 may further
280 where the amplitude ofthe sounds represented by the data 5 incorporate one or both of the ADCs 410 and 955. The signal
provided to the VGA 280 may be altered under the control of
processing topologies 2500b , 2500c and 2500e are similar in
the compression controller950. The VGA 280 outputs its data
numerous ways. The manner in which the data output by each
(with or without amplitude alteration) to the summing node
of the filter blocks 250 , 350 and 450 are combined in the
signal processing topology 2500ε is substantially similar to
290 , where it may be combined with data that may be output
by the filter block 450 (p erhaps the higher frequency sounds 10 that of the signal processing topology 2500b. Also , like the
ofthe modified pass-through audio , orperhaps the entirety of
signal processing topology 2500c , the signal processing
topology 2500e incorporates the compression controller 950.
the modified pass-through audio). In tum, the summing node
However, a substantial difference between the signal process290 provides its output data to the DAC 910. Where the
ing topologies 2500c and 2500e is the replacement of the
provision of feedforward-based ANR is also supported, the
data output by the filter block 250 to the VGA 280 is routed 15 single VGA 280 in the signal processing topology 2500c for
through the summing node 270 , where it is combined with the
the separately controllable VGAs 240 and 340 in the signal
data output by the filter block 350 representing feedforward
processing topology 2500ε.
anti-noise sounds , and this combined data is provided to the
The summing node 230 provides data representing feedVGA 280.
back reference sounds possibly combined with data that may
FIG. 4d depicts another possible signal processing topol- 20 be output by the filter block 450 (perhaps the lower frequency
ogy 2500d for which the ANR circuit 2000 may be structured
sounds of the modified pass-through audio , or perhaps the
and/or programmed. Where the ANR circuit 2000 adopts the
entirety ofthe modified pass-through audio) to the filter block
250 through the VGA 240 , and the ADC 310 provides data
signal processing topology 2500d, the ANR circuit 2000
representing feedforward reference sounds to the filter block
incorporates at least the DAC 910 , the compression controller
950 , the audio amplifi位 960 ， the ADC 210 , the summing 25 350 through the VGA 340. The data output by the filter block
350 is combined with data that may be output by the filter
nodes 230 and 290 , the filter blocks 250 and 450 , the VGA
block 450 (p erhaps the higher frequency sounds ofthe modi280 , and still other VGAs 445 , 455 and 460. TheANR circuit
且ed pass-through audio , or perhaps the entirety ofthe modi2000 may further incorporate one or more of the ADCs 310
and/or 410 , the filter block 350 , the sunmIÏng node 270 , the
fied pass-through audio) at the summing node 370. In turn, the
ADC 955 , and still another VGA 360. The signal processing 30 sunmIÏngnode 370 provides its data to the summing node 270
topologies 2500c and 2500d are similar in numerous ways.
to be combined with data output by the filter block 250. The
sunmIÏng node 270 , in turn, provides its combined data to the
However, a substantial difference between the signal processDAC 910
ing topologies 2500c and 2500d is the addition ofthe ability
The compression controller 950 controls the gains ofthe
to direct the provision ofthe higher frequency sounds ofthe
modified pass-through audio to be combined with other audio 35 VGAs 240 and 340 , to enable the amplitude of the sounds
at either or both of two different locations within the signal
represented by data output by the summing node 230 and the
ADC 310 , respectively, to be reduced in response to actual
processing topology 2500 d.
One or more digital filters within the filter block 450 are
instances or indications of upcoming instances of clipping
employed to modi fY the digital data representing the passand/or other undesirable audio artifacts being detected by the
through audio to derive a modified variant ofthe pass-through 40 compression controller 950. The gains ofthe VGAs 240 and
audio data and to function as a crossover that divides the
340 may be controlled in a coordinated manner, or may be
modified pass-through audio data into higher and lower frecontrolled entirely independently of each other
quency sounds. Data representi月 the lower frequency
FIG. 4f depicts another possible signal processing topolsounds are output to the summing node 230 through the VGA
ogy 2500jfor which the ANR circuit 2000 may be structured
445. Data representing the higher frequency sounds are out- 45 and/or programmed. \\屯ere the ANR circuit 2000 adopts the
put both to the summing node 230 through the VGA 455 and
signal processing topology 2500元 the ANR circuit 2000
incorporates at least the DAC 910; the audio amplifier 960;
to the DAC 910 through the VGA 460. The VGAs 445 , 455
theADCs 210 and310; the summingnodes 230 , 270 and370;
and 460 are operable both to control the amplitudes of the
the filter blocks 250 , 350 and 450; the compressor 950; and
lower frequency and higher frequency sounds represented by
the data output by the filter block 450 , and to selectively direct 50 the VGAs 125 and 135. The ANR circuit 2000 may further
incorporate one or both of the ADCs 410 and 955. The signal
the flow of the data representing the higher frequency sounds.
processing topologies 2500e and 2500j are similar in numerHowever, as has been previously discussed, the crossover
functionality of the filter block 450 may be employed to
ous ways. However, a substantial difference between the sigselectively route the entirety of the modified pass-through
nal processing topologies 2500e and 2500jis the replacement
audio to one or the other of the summing node 230 and the 55 of the pair of VGAs 240 and 340 in the signal processing
DAC 910.
topology 2500e for the VGAs 125 and 135 in the signal
Where the provision of feedforward-based ANR is also
processing topology 2500f
supported, the possible provision ofhigher frequency sounds
The VGAs 125 and 135 positioned at the analog inputs to
theADCs 210 and 310 , respectively, are analog VGAs , u凶 ike
(or perhaps the entirety ofthe modified pass-through audio)
by the filter block 450 through the VGA 460 and to the DACωthe VGAs 240 and 340 of the signal processing topology
2500e. This enables the compression controller 950 to
910 may be through the summing node 290. The filter block
350 provides the feedforward anti-noise data to the sunmIÏng
respond to actual occurrences and/or indications of soon-tonode 270 through the VGA 360.
occur instances of clipping and/or other audio artifacts in
FIG. 4e depicts another possible signal processing topoldriving the acoustic driver 190 by reducing the amplitude of
ogy 2500e for which the ANR circuit 2000 may be structured 的 one or both of the analog signals representing feedback and
and/or programmed. Where the ANR circuit 2000 adopts the
feedforwardreference sounds. This may be deemed desirable
where it is possible for the analog signals provided to the
signal processing topology 2500ιthe ANR circuit 2000

US 8,073 ,151 B2
27
ADCs 210 and 310 t'O be at t 'O'O great an amplitude such that
clipping at the p 'O int 'O f driving the ac 'O ustic driver 190 might
be m 'Ore readily caused t'O 'O ccur. The provisi 'O n 'O fthe ability
t'O reduce the amplitude 'O f these anal 'O g signals (and perhaps
als 'O including the anal 'O g signal pr'Ovided t 'O theADC 410 via
趾 VGA 145 depicted els凹h的) may be deemed 由 s lra
de 吋
臼叩
tω enable balancing '0吋
'0
fampμlitu de s between 吐旭 ana l'Og si g吋臼
吋
1
t hese 址
挖
nals, and/or to limit the numeric values of the digital data
produced by one or more ofthe ADCs210 , 310and 410to
er magnitudes t 'O reduce st 'O rage and/'O r transmissi 'O n
bandwidth requirements.
FIG. 4g depicts an'Other p 'O ssible signal processing t'O p 'O l'O gy 2500g f 'O r which the ANR circuit 2000 may be program1ed or otherwmstructured where tIEANR circ111t
2000adopts the SIgnal processmg topology2500g, theANR
circuit 20"00 inc'OrP'Orat~s at leasÙhe" c'O~pressi'O~ c 'Ontr'O ller
950 , theDAC910 ，-theaudi'O amplifier960~theADCs210and
310 , a pair 'O fVGAs 220 and 320 , the summing n 'O des 230 and
270 , the filter bl 'O cks 250 and 350 , an'O ther pair 'O fVGAs 355
and 360 , and the VGA 280. TheANR circuit 2000 may further
inc 'O rp 'Orate 'O ne 'O r m 'O re 'O ftheADC 410 , the filter bl 'O ck 450 ,
still an'O ther VGA 460 , the summing n 'O de 290 , and the ADC
955.
The ADC 210 receives an anal 'O g signal from the feedback
micr'Oph'O ne 120 and digitizes it , bef'O re pr'Oviding c 'Orresp 'O nding feedback reference data t'O the VGA 220. The VGA
220 'O utputs the feedback reference data , p 'O ssibly after m 'O di fying its amplitud且， t 'O the sUlllilling n 'O de 230. Similarly, the
ADC 310 receives an anal 'O g signal 企'Om the feedf'Orward
micr'Oph'O ne 130 and digitizes 泣， bef'O re pr'Oviding c 'Orresp 'O nding feedf'Orward reference data t'O the VGA 320. The
VGA 320 'Outputs the feedf'Orward reference data , p'O ssibly
after m 'O di fY ing its amplitud巴， t'O the filter bl 'O ck 350. One 'O r
m 'O re digital filters within the filter bl 'O ck 350 are empl 'O yed t 'O
m 'O di fY the feedf'O rward reference data t'O derive feedf'O rward
anti-n'O ise data representing feedf'O rward anti-n'O ise s'Ounds ,
and the filter bl 'O ck 350 pr'Ovides the feedf'Orward anti -n'O ise
data t'O b 'O th 'O fthe VGAs 355 and 360. In vari 'O us implementati 'O ns , the gains 'O fthe VGAs 355 and 360 are dynamically
selectable and can be 'O perated in a c 'O'O rdinated mauner like a
thr臼 -way switch t 'O enable the feedf'O rward anti-n'O ise data t 'O
be selectively pr'Ovided t'O either 'O fthe summing n 'O des 230
and 270. Thus , where the feedf'Orward anti-n'O ise data is c 'O mbined with data related t'O feedback ANR within the signal
processing t 'O p'O l'O gy 2500g is made selectable.
Theref'O re , depending 'O n the gains selected f'O r the VGAs
355 and 360 , the feedf'Orward anti-n'O ise data fr 'O m the filter
bl 'O ck 350 may be c 'Ombined with the feedback reference data
from the ADC 210 at the summing n 'O de 230 , 'O r may be
c 'Ombined with feedback anti-n'O ise data derived by the filter
bl 'O ck 250 fr 'Om the feedback reference data at the sUlllilling
n 'O de 270. If the feedf'Orward anti-n'O ise data is c'O mbined with
the feedback reference data at the summing n 'O de 230 , then
the filter bl 'O ck 250 derives data representing a c 'Ombinati 'On 'O f
feedback anti-n'O ise s'Ounds and further-m 'O dified feedf'Orward
anti-n'O ise s'O unds , and this data is provided t'O the VGA 280
thr'Ough the summing n 'O de 270 at which n'O c 'Ombining 'O f data
'O ccurs. Alternatively, if the feedf'O rward anti -n'O ise data is
c 'Ombined with the feedback anti-n'O ise data at the sUlllilling
n 'O de 270 , then the feedback anti-n'O ise data will have been
derived by the filter bl 'O ck 250 fr 'Om the feedback reference
data received thr'O ugh the sUlllilling n 'O de 230 at which n 'O
c 'Ombining 'O f data 'O ccurs , and the data resulting fr 'Om the
c 'Ombining at the summing n'O de 270 is pr'Ovided t 'O the VGA
280. With 'Or with'O ut an alterati 'O n in amplitude , the VGA 280
provides whichever f 'O rm 'O f c 'Ombined data is received fr 'Om
the sUlllilling n'O de 270 t'O the DAC 910 t'O create an anal 'O g

28
signal. This pr'Ovisi 'O n 'O fthis c 'O mbined data by the VGA 280
may be thr'O ugh the summing n'O de 290 where the provisi 'On 'O f
pass-thr'O ugh audi 'O is als 'O supp 'Orted.
Where the provisi 'O n 'O f pass-thr'O ugh audi 'O is supp 'O rted ,
5 the audi 'O s'Ource 9400 may provide an anal 'O g signal repreand the ADC 410 digitizes the anal 'O g signal and pr'Ovides
pass-throughaudio data cOITespondingto the analog signal to
the alter block 450.AItematively, where the audio source
10
9400 provides digital data representing pass-thr'Ough audi 'O,
such digital data may be pr'Ovided directly t'O the filter bl 'O ck
450. One 'Or m 'O re digital filters within the filter bl 'O ck 450 may
beemployedtomodtythedIPtal datarepresent1月 the passnthroughaudio to derive aInodikdvariant ofthepass-throud1
audi 'O ~~a that may be re-e~ualized and/'Or enhan~.e_d i.n 'O ther
ways. The filter bl 'O ck 450 provides the m 'O dified passthr'Ough audi 'O data t'O the VGA 460 , and eitherwith 'Or with'O ut
altering the amplitude 'O fthe pass-thr'O ugh audi 'O s'Ounds rep20 resented by the m 'O dified pass-thr'Ough audi 'O data , the VGA
460 provides the m 'O dified pass-thr'O ugh audi 'O data t'O the
DAC 910 thr'O ugh the summing n 'O de 290.
The c'O mpressi 'O n c'O ntr'O ller 950 c 'O ntrols the gain 'O f the
VGA 280 t 'O enable the amplitude 'O f whatever c 'Ombined f 'O rm
25 'O f feedback and feedf'O rward anti -n'O ise s'O unds are received
by the VGA 280 t'O be reduced under the c'O ntr'O l 'O f the
c 'Ompressi 'On c 'O ntroller 950 in resp 'O nse t'O actual 'O ccurrences
and/'O r indicati 'O ns 'O f impending instances 'O f clipping and/'O r
'O ther audi 'O artifacts
30
FIGS. 5a thr'Ough 公 depict s'O me p 'O ssible filter bl 'O ck
t'O p 'O l 'O gies that may be empl 'O yed in creating 'One 'O r m 'O re
bl 'O cks 'O f filters (such as filter bl 'O cks 250 , 350 and 450) within
signal proc的 sing t 'Op 'O l'O gies ad'O pted by the ANR circuit
2000 (such as the signal processing t'Op 'O l'O gi的 2500α -g). It
35 sh'O uld be n'O ted that the designati 'O n 'O f a multitude 'O f digital
filters as a “ filter bl 'O ck" is an arbitrary c 'O nstruct meant t'O
simpli fY the earlier presentati 'O n 'O f signal pr'O cessing t 'Op 'O l'Ogies. In truth , the selecti 'O n and p 'O siti 'Oning 'O f 'One 'O r m 'O re
digital filters at any p 'O int al 'Ong any 'O fthe pathways (such as
40 the pathways 200 , 300 and 400) 'O f any signal processing
t'O p 'O l 'O gy may be acc 'O mplished in a m amJer identical t 'O the
selecti 'On and p'O siti 'O ning 'O f VGAs and summing n 'O des
Theref'Ore , it is entirely p 'O ssible f'O rvari 'Ous digital filters t'O be
p 'O siti 'O ned al 'O ng a pathway f 'Or the m 'Ovement 'O f data in a
的 mauner in which th 'O se digital filters are interspersed am'O ng
VGAs and/'Or summing n 'O des such that n 'O distinguishable
bl 'O ck 'O f filters is created. Or, as will be illustrated, it is
entirely p 'O ssible f 'Or a filter bl 'O ck t 'O inc 'O rp 'O rate a summing
n 'O de 'O r 'O ther c'O mp 'O nent as part 'O fthe m紅mer in which the
50 filters 'O f a filter bl 'O ck are c 'Oupled as part 'O fthe filter bl 'O ck
t'O p 'O l 'O gy 'O f a filter bl 'O ck.
H 'Owever, as previ 'O usly discussed , multiple l 'Ower- 'O rder
digital filters may be c 'O mbined in vari 'O us ways t'O perf'O rm the
equivalent functi 'O n 'O f 'One 'Or m 'O re higher- 'Order digital filters.
55 Thus , alth'O ugh the creati 'On 'O f distinct filter bl 'O cks is n 'O t
necessary in defining a pathway having multiple digital filters , it can be desirable in numer'O us situati 'O ns. Furtl間， the
creati 'O n 'O f a bl 'O ck 'O f filters at a single p'O int al 'O ng a pathway
can m 'Ore easily enable alterati 'O ns in the characteristics 'O f
60 filtering perf'O rmed in that pathway. By way 'O f example ,
multiple l'Ower- 'O rder digital filters c 'Onnected with n'O 'O ther
c 'Omp 'O nents interp 'O sed between them can be dynamically
c 'Onfigured t 'O c 'O'Operate t'O perf'O rm any 'O f a variety 'O fhigher'O rder filter functi 'O ns by simply changing their c'O e且cients
65 and/'O r changing the manner in which they are interc 'Onnected.
Als 'O, in s'Ome implementati 'O ns , such cl 'O se interc 'O nnecti 'On 'O f
digital filters may ease the task 'O f dynamically c 'On且直unnga

US 8,073 ,151 B2

29

30

pathway to add or remove digital filters with a minimum of
changes to the interconnections that define that pathway.
It should be noted that the selections of types of filters ,
quantities of filters , interconnections of filters and filter block
topologies depicted in each ofFIGS. 5αtl宜。ugh 5e are meant
to serve as examples to facilitate understandi唔， and should
not be taken as limiting the scope ofwhat is described or the
scope ofwhat is claimed herein.
FIG. 5a depicts a possible filter block topology 3500αfor
which the ANR circuit 2000 may be structured and/or programmed to define a filter block, such as one of the filter
blocks 250 , 350 and 450. The filter block topology 3500αis
made up of a serial chain of digital filters with a downsampling filter 652 at its input; biquad filters 654 , 655 and 656;
and a FIR filter 658 at its output.
As more explicitly depicted in FIG. 5a , in some implementations , the ANR circuit 2000 employs the internal architecture 2200a such that the ANR circuit 2000 incorporates the
filterb紅J.k: 550 incorporating multitudes ofthe downsampling
filters 552 , the biquad filters 554 , and the FIR filters 558. One
or more of each ofthe downsampling filters 552 , biquad filters
554 and FIR filters 558 may be interconnected in any of a
number ofways via the switch a叮ay 540 , including in a way
that defines the filter block topology 3500a. More specifically, the downsampling filter 652 is one ofthe downsampling
filters 552; the biquad filters 654 , 655 and 656 are each one of
the biquad filters 554; and the FIR filter 658 is one of the FIR
filters 558.
Alternati、rely， and as also more explicitly depicted in FIG.
5a , in other implementations , the ANR circuit 2000 employs
the internal architecture 2200b such that the ANR circuit
2000 incorporates a storage 520 in which is stored the downsampling filter routine 553 , the biquad filter routine 555 and
the FIR filter routine 559. Varying quantities of downsampling , biquad and/or FIR filters may be instantiated within
available storage locations of the storage 520 with any of a
variety of interconnections defined between them, including
quantities of filters and interconnections that define the filter
block topology 3500a. More specifically, the downsampling
filter 652 is an instance of the downsampling filter routine
553; the biquad filters 654 , 655 and 656 are each instances of
the biquad filter routine 555; and the FIR filter 658 is an
instance ofthe FIR filter routine 559.
As previously discussed, power conservation and/or other
benefits may be realized by employing different data transfer
rates along different pathways of digital data representing
sounds in a signal processing topology. In support of converting between different data transfer rates , includi月 where one
pathway operating at one data transfer rate is coupled to
another pathway operating at another data transfer rate , different data transfer clocks may be provided to different ones
ofthe digi的1 filters within a filter block, and/or one or more
digital filters within a filter block may be provided with multiple data transfer clocks.
By way of example , FIG. 5a depicts a possible combination of di芷erent data transfer rates that may be employed
within the filter block topology 3500αto support digital data
being received at one data transfer ra峙， digital data being
transfe叮ed among these digital filters at another data transfer
rate, and digital data being output at still another data transfer
rate. More specifically, the downsampling filter 652 receives
digital data representing a sound at a data transfer rate 672 ,
and at least downsamples that digital data to a lower data
transfer rate 675. The lower data transfer rate 675 is employed
in transferring digital data among the downsampling filter
652 , the biquad filters 654-656 , and the FIR filter 658. The
FIR filter 658 at least upsamples the digital data that it

receives from the lower data transfer rate 675 to a higher data
transfer rate 678 as that digital data is output by the filter block
to which the digital filters in the filter block topology 3500a
belong. Many other possible examples ofthe use of more than
one data transfer rate within a filter block and the possible
corresponding need to employ multiple data transfer clocks
within a filter block will be clear to those skilled in the art.
FIG. 5b depicts a possible filter block topology 3500b that
is substantially similar to the filter block topology 3500a , but
in which the FIR filter 658 ofthe filter block topology 3500a
has been replaced with an interpolating filter 657. Where the
internal architecture 2200a is employed, such a change from
the filter block topology 3500αto the filter block topology
3500b entails at least altering the configuration ofthe switch
a叮ay 540 to exchange one ofthe FIR filters 558 with one of
the interpolating filters 556. Where the internal architecture
2200b is employed, such a change entails at least replacing
the instantiation of the FIR filter routine 559 that provides the
FIR filter 658 with an inst訕訕訕。n ofthe interpolating filter
routine 557 to provide the interpolating filter 657
FIG. 5c depicts a possible filter block topology 3500c that
is made up of the same digital filters as the filter block topology 3500b , but in which the interconnections between these
digital filters have been reconfigured into a branching topology to provide two outpu的， whereas the filter block topology
3500b had only one. Where the internal architecture 2200αlS
employed, such a change from the filter block topology 3500b
to the filter block topology 3500c entails at least altering the
configuration ofthe switch a叮ay 540 to disconnect the input
to the biquad filter 656 from the output of the biquad filter
655 , and to connect that input to the output ofthe downsampling filter 652 , instead. Where the internal architecture
2200b is employed, such a change entails at least alteri月 the
instantiation of biquad filter routine 555 that provides the
biquad filter 656 to receive its input from the instantiation of
the downsampling filter routine 553 that provides the downsampling filter 652. The filter block topology 3500c may be
employed where it is desired that a filter block be capable of
providing two different outputs in which data representing
audio provided at the input is altered in different ways to
create two different modified versions ofthat data , such as in
the case ofthe filter block 450 in each ofthe signal processing
topologies 2500b :f
FIG. 5d depicts another possible filter block topology
3500d that is substantially similar to the filter block topology
3500α ， but in which the biquad filters 655 and 656 have been
removed to shorten the chain of digital filters from the quantity of five in the filter block topology 3500αto a quantity of
three.
FIG. 5e depicts another possible filter block topology
3500e that is made up of the same digital filters as the filter
block topology 3500b , but in which the interconnections
between these digital filters have been reconfigured to put the
biquad filters 654 , 655 and 656 in a parallel configuration,
whereas these same filters were in a serial chain configuration
in the filter block topology 3500b. As depicted, the output of
the downsampling filter 652 is coupled to the inputs of all
three ofthe biquad filters 654 , 655 and 656 , and the outputs of
all three of these biquad filters are coupled to the input of the
interpolating filter 657 through an additionally incorporated
surnnlÏ ng node 659
Taken together, the FIGS. 5αtl宜。ugh 公 depict the manner
in which a given filter block topology of a filter block is
dynamically configurable to so as to allow the types of filters ,
quantities of filters and/ or interconnections of digital filters to
be altered during the operation of a filter block. However, as
those skilled in the art will readily recogniz巴， such changes in

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US 8,073 ,151 B2

31
types , quantities and interconnections of digital filters are
likely to require corresponding changes in filter coefficients
and/or other settings to be made to achieve the higher-order
filter function sought to be achieved with such changes. As
will be discussed in greater detail , to avoid or at least mitigate 5
the creation of audible distortions or other undesired audio
artifacts arising from making such changes during the operation of the personal ANR device, such changes in interconnections , quantities of components (including digital filters) ,
types of components , filter coefficients and/or VGA gain 10
values are ideally buffered so as to enable their being made in
a manner coordinated in time with one or more data transfer
rates.
立le dynamic configurability of both of the internal archi tectures 2200a and 2200b , as exemplified throughout the 15
preceding discussion of dynamically configurable signal processing topologies and dynamically configurable filter block
topologies , enables numerous approaches to conserving
power and to reducing audible artifacts caused by the introduction of microphone self noise , quantization errors and 20
other influences arising from components employed in the
personal ANR device 1000. Ind臼d， there can be a synergy
between achieving both goals , since at least some measures
taken to reduce audible artifacts generated by the components
ofthe personal ANR device 1000 can also result in reductions 25
in power consumption. Reductions in power consumption
can be of considerable importance given that the personal
ANR device 1000 is preferably powered from a battery or
other portable source of electric power that is likely to be
30
somewhat limited in ability to provide electric power.
In either ofthe internal architectures 2200a and 2200b , the
processing device 510 may be caused by execution of a
sequence of instructions of the ANR routine 525 to monitor
the availability of power from the power source 180. Alternatively and/or additional紗， the processing device 510 may 35
be caused to monitor characteristics of one or more sounds
(e.g. , feedback reference and/or anti-noise sounds , feedforwardreference and/or anti-noise sounds , and/orpass-through
audio sounds) and alter the degree of ANR provided in
response to the characteristics observed. As those familiar 的
with ANR will readily recogniz巴， it is often the case that
providing an increased degree of ANR often requires the
implementation of a more complex transfer function, which
often requires a greater number of filters and/or more complex types offilters to implement , and this in t凹'll， often leads 的
to greater power consumption. Analogously, a lesser degree
of ANR often requires the implementation of a simpler transfer function, which often requires fewer and/or simpler filters ,
whichin 仙阻 often leads to less power ∞ 叩 mpμion.
t urn
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n
c ons un耶朋
1 t
且 抖
世
Further, there can arise situations , such as an enviroument 50
with relatively low enviromnental noise levels or with enviromnental noise sounds occurring within a relatively na叮ow
range of frequencies , where the provision of a greater degree
of ANR can actually result in the components used in providing theANR generating noise sounds greater than the attenu- 55
ated enviromnental noise sounds. Still further, and as will be
familiar to those skilled in the art of feedback-based ANR,
under some circumstances , providing a considerable degree
offeedback-basedANR can lead to instability as undesirable
60
audible feedback noises are produced.
In response to either an indication of diminishing availability of electric power or an indication that a lesser degree of
ANR is needed (or is possibly more desirable) , the processing
device 510 may disable one or more functions (including one
or both of feedback-based and feedforward-based ANR) ，的
lower data transfer rates of one or more pathways , disable
branches within pathways , lower data transfer rates between

32
digital filters within a filter block, replace digital filters that
consume more power with digital filters that consume less
power, reduce the complexity of a transfer function employed
in providingANR, reducethe overall quantity of digital filters
within a filter block, and/or reduce the gain to which one or
more sounds are subjected by reducing VGA gain settings
and/or altering filter coefficients. However, in taking one or
more ofthese or other similar actions , the processing device
510 may be further caused by theANR routine 525 to estimate
a degr伐。 f reduction in the provision of ANR that balances
one or both of the goals of reducing power consumption and
avoiding the provision of too great a degree of ANR with one
or both of the goals of maintaining a predetermined desired
degree of quality of sound and quality of ANR provided to a
user of the personal ANR device 1000. A minimum data
transfer rate , a maximum signal-to-noise ratio or other measure may be used as the predetermined degree of quality or
ANR and/or sound.
As an example , and referring back to the signal processing
topology 2500a of FIG. 4a in which the pathways 200 , 300
and 400 are explicitly depicted, a reduction in the degree of
ANR provided and/or in the consumption of power may be
realized through turning off one or more of the feedbackbasedANR, feedforward-basedANR and pass-tl宜。ughaudio
functions. This would result in at least some of the components along one or more of the pathways 200 , 300 and 400
either being operated to enter a low power state in which
operations involving digital data would cease within those
components , or bei月 substantially disconnected 企om the
power source 180. A reduction in power consumption and/or
degree of ANR provided may also be realized through lowering the data transfer rate(s) of at least portions of one or
more of the pathways 200 , 300 and 400 , as previously discussed in relation to FIG. 4α.
As another example, and referring back to the signal processing topology 2500b of FIG. 4b in which the pathways
200 , 300 and 400 are also explicitly depicted, a reduction in
power consumption and/or in the complexity oftransferfunctions employed may be realized through turning offthe fIow
of data through one ofthe branches ofthe split in the pathway
400. More specifically, and as previously discussedinrelation
to FIG. 4b , the crossover frequency employed by the digital
filters within the filter block 450 to separate the modified
pass-through audio into higher 企equency and lower frequency sounds may be selected to cause the entirety of the
modified pass-through audio to be directed towards only one
of the branches of the pathway 400. This would result in
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data 加趾Ougl one or the other ofthe summing nodes 230 and
t 叩拉
h
370 , thereby enabling a reduction in power consumption and/
or in the introduction of noise sounds from components by
allowing the combining function of one or the other of these
sUlllilling nodes to be disabled or at least to not be utilized
Similarly, and referring back to the signal processing topology 2500d ofFIG. 4d (despite the lack of explicit marking of
its pathways) , eitherthe crossoverfrequency employed bythe
filter block 450 or the gain settings ofthe VGAs 445 , 455 and
460 may be selected to direct the entirety of the modified
pass-through audio data down a single one of the three possible pathway branches into which each ofthese VGAs lead.
Thus , a reduction in power consumption and/or in the introduction of noise sounds would be enabled by allowing the
combining function of one or the other of the summing nodes
230 and 290 to be disabled or at least not be utilized. Still
further， one or more ofthe VGAs 445 , 455 and 460 through
which modified pass-through audio data is not being transfe叮ed may be disabled.

US 8,073 ,151 B2
33

34

As still another example , and referring back to the filter
block topology 3500a of FIG. 5αin which the allocation of
thr臼 data transfer rates 672 , 675 and 678 are explicitly
depicted, a reduction in the degree ofANR provided and/or in
power consumption may be realized through lowering one or
more ofthese data transfer rates. More specifically, within a
filter block adopting the filter block topology 3500a , the data
transfer rate 675 at which digital data is transferred among the
digital filters 652 , 654-656 and 658 may be reduced. Such a
change in a data transfer rate may also be accompanied by
exchanging one or more of the digital filters for variations of
the same type of digital filter that are better optimized for
lower bandwidth calculations. As will be familiar to those
skilled in the art of digital signal processin皂， the level of
calculation precision required to maintain a desired predetermined degree of quality of sound and/or quality of ANR in
digital processing changes as sampling rate changes. Therefore , as the data transfer rate 675 is reduced, one or more of
the biquad filters 654-656 which may have been optimized to
maintain a desired degree of quality of sound and/or desired
degree of quality ofANR at the original data transfer rate may
be replaced with other variants of biquad filter that are optimized to maintain substantially the same quality of sound
and/or ANR at the new lower data transfer rate with a reduced
level of calculation precision that also reduces power consumption. This may entail the provision of different variants
of one or more of the different types of digital filter that
employ coefficient values of differing bit widths and/or incorporate differing quantities oftaps.
As still other examples , and referring back to the filter
block topologies 3500c and 3500d of FIGS. 5c and 5d,
respectively, as well as to the filter block topology 3500α ， a
reduction in the degree of ANR provided and/or in power
consumption may be realized through reducing the overall
quantity of digital filters employed in a filter block. More
specifically, the overall quantity of five digital filters in the
serial chainofthe filterblocktopology 3500a maybereduced
to the overall quantity of three digital filters in the shorter
serial chain of the filter block topology 3500d. As those
skilled in the art wouldreadily recogniz巴， such a change in the
overall quantity of digital filters would likely need to be
accompanied by a change in the coefficients provided to the
one or more of the digital filters that remain, since it is likely
that the transfer function(s) performed by the original five
digital filters would have to be altered or replaced by transfer
function(s) that are able to be performed with the three digital
filters that remain.Also more specifically, the overall quantity
of five digital filters in the branching topology of the filter
block topology 3500c may be reduced to an overall quantity
ofthree digital filters by removing or otherwise deactivating
the filters of one ofthe branches (e.g. , the biquadfilter 656 and
the interpolating filter 657 of one branch that provides one of
the 阿o outputs). This may be done in concert with selecti月
a crossover frequency for a filter block providing a crossover
function to effectively direct all frequencies of a sound represented by digital data to only one ofthe two outputs , and/or
in concert with operating one or more VGAs external to a
filter block to remove or otherwise cease the transfer of digital
data through a branch of a signal processing topology.
Reductions in data transfer rates may be carried out in
various ways in either of the intemal architectures 2200a and
2200b. By way of example in the internal architecture 2200a ,
various ones ofthe data transfer clocks provided by the clock
b紅J.k: 570 may be directed through the switch a汀ay 540 to
differing ones ofthe digital filters , VGAs and summing nodes
of a signal processing topology and/or filter block topology to
enable the use of multiple data transfer rates and/or conver-

sions between di芷erent data transfer rates by one or more of
those components. By way of example in the intemal architecture 2200b , the processing device 510 may be caused to
execute the sequences of instructions of the various instantiations of digital filters , VGAs and summing nodes of a
signal processing topology and/or filter block topology at
intervals of differing lengths of time. Thus , the sequences of
instructions for one instantiation of a given component are
executed at more 企'equent intervals to support a higher data
transfer rate than the sequences of instructions for another
instantiation ofthe same component where a lower data tra的fer rate is supported.
As yet another example, and referring back to any of the
earlier-depicted signal processing topologies and/or filter
block topologies , a reduction in the degree of ANR provided
and/or in power consumption may be realized through the
reduction of the gain to which one or more sounds associated
with the provision of ANR (e.g. , feedback reference and/or
anti-noise sounds , or feedforward reference and/or anti-noise
sounds). Where a VGA is incorporated into at least one of a
feedback-basedANR pathway and a feedforward-basedANR
pathway, the gain setting of that VGA may be reduced. Alternatively and/or additionally, and depending on the transfer
function implemented by a given digital filter, one or more
coe且cients ofthat digital filter may be altered to reduce the
gain imparted to whatever sounds are represented by the
digital data output by that digital filter. As will be familiar to
those skilled in the art, reducing a gain in a pathway can
reduce the perceptibility of noise sounds generated by components. In a situation where there is relatively little in the
way of environmental noise sounds , noise sounds generated
by components can become more prevalent, and thus , reducing the noise sounds generated by the components can
become more important than generating anti -noise sounds to
attenuate what little in the way of environmental noise sounds
may be present. In some implementations , such reduction(s)
in gain in response to relatively low environmental noise
sound levels may enable the use oflower cost microphones.
In some implementations , performing such a reduction in
gain at some point along a feedback-basedANR pathway may
prove more useful than along a feedforward-basedANR pathway, since environmental noise sounds tend to be more
attenuated by the PNR provided by the personal ANR device
before ever reaching the feedback microphone 120. As a
result ofthe feedback microphone 120 tending to be provided
with weaker variants of environmental noise sounds than the
feedforwardmicrophone 130 , the feedback-basedANR function may be more easily susceptible to a situation in which
noise sounds introduced by components become more prevalent than environmental noise sounds at times when there is
relatively little in the way of environmental noise sounds. A
VGA may be incorporated into a feedback-basedANR pathway to p位form this function by normally employing a gain
value of 1 which would then be reduced to 悅。r to some other
preselected lower value in response to the processing device
510 and/or another processing device extemal to the ANR
circuit 2000 and to which the ANR circuit 2000 is coupled
determini月 that environmental noise levels are low enough
that noise sounds generated by components in the feedbackbased ANR pathway are likely to be significant enough that
such a gain reduction is more advantageous than the production of feedback anti -noise sounds
The monitoring of characteristics of environmental noise
sounds as part of determining whether or not changes inANR
settings are to be made may entail any of a number of
approaches to measuring the strength, frequencies and/or
other characteristics of the environmental noise sounds. In

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US 8,073 ,151 B2

35

36

s'Ome implementati 'O ns , a simple s'O und pressure level (SPL)
FIG. 6a depicts the triple-buffering 'O f VGA settings ,
'O r 'Other signal energy measurement with'O ut weighting may
including gain values , empl 'Oying variants 'O f the buffers
be taken 'O f envir'O nmental n'O ise s'O unds as detected by the
620a-c that each st'O re differing 'O nes 'O fVGA settings 626. An
feedback microph'O ne 120 and/'O r the feedf'Orward microexample 'O f a use 'O f such triple-buffering 'O fVGA gain values
ph'One 130 within a preselected range 'O f frequencies. Alter- 5 may be the c 'Ompressi 'On c'O ntroller 950 'O perating 'O ne 'Or m 'O re
y'GA~ t'O reduce the amp!itude 'O f s'O unds represented ~y
natively, the frequencies within the preselected range 'O f frequencies of a SPL or other SIgnal energy measurement may
digital data in response to detecting occu叮ences and/'Or indisubjected to the widely known and used1-weid1ted"fre-cations of impending occu叮ences 'O f clipping and/'O r 'O ther
quency weisuing curve developed to renect the relative sen-audible art1facts in the aco1IStic output ofthe acoustic driver
10 190. In s'O me implementati 'Ons , the c'O mpressi 'O n c'O ntr'O ller
sitivities 'O f the average human ear t'O different audible fre950 st'O res new VGA settings int'O a selected 'One 'O fthe buffers
quencles.
620a and 620b. At a subsequent time that is synchr'O nized t'O
FIGS-6Gthroughkdepict aspects and possible imPIe-the How ofpieces ofdigital data throud1one or more ofthe
mentati 'O ns 'O f triple-buffering b 'O th t 'O enable syncl宜。nized
VGAs , th.~ ~~ttings st~;~d in the selected ~~e 'O f the buffers
ANR setting cha峙的 a吋 t'O enabl~ a_~ail_safe resp 'O nse t 'O an 15 620αa吋 620b are pr'Ovided tω th'Os eVGA趴， the昕ebyav'Oidin
'O 昀 臼
s 迪r
叮
昀
∞ 叩 叩臼
O cc u叮enc e and/'O r t'O indicati 'Ons 'O f a likely 叩 ∞'Ommg 'Occu ru pc
盯
the generati 'O n 'O f audible artifacts. As th'O se skilled in the art
wilCreadily rec 'O gnize , the c'O mpressi 'O n c 'O ntroller 950 may
rence 'O f an 'Out- 'O f-b 'O und c'O nditi 'On , including and n'O t limited
t'O, clipping and/'O r excessive 紅nplitude 'O f ac 'Oustically 'Output
repeatedly updat~ the gain settiri:gs 'O fVGAs 'Over a peri 'O d 'O f
time t'O "r紅np d 'Own" the amplitude 'O f 'One 'O r m 'O re s'Ounds t'O
s'Ounds , pr'O ducti 'O n 'O f a s'O und within a specific range 'O f
E民quencies that is ass 'O ciated with a malfuncti 'O n , instability 20 a desired level 'O f amplitud巴， rather than t 'O immediately
'O f at least feedback-based ANR , 'O r 'O ther c 'O nditi 'O n that may
reduce the amplitude t 'O that desired level. In such a situati 'O n ,
generate undesired 'Or unc 'O mf'O rtable ac 'Oustic 'O utput. Each 'O f
the c 'O mpressi 'O n c 'O ntroller 950 w 'O uld alternate between st'O ring updated gain settings t'O the buffer 620a and st'O ring
these variati 'Ons 'O f triple-buffering inc 'Orp 'Orate at least a tri 'O
'O fbu芷ers 620α ， 620b and 620c. In each depicted variati 'O n 'O f
updated gain settings t'O the buffer 620b , thereby enabling the
triple-bufferi 峙， tw'O 'O f the buffers 620a and 620b are alter- 25 dec 'O upling 'O fthe times at which each 'O fthe buffers 620a and
nately empl 'Oyed during n 'Ormal 'O perati 'O n 'O f the ANR circuit
620b are each written t'O by the c 'Ompressi 'O n c 'O ntroller 950
2000 t'O synchr'O n'O usly update desired ANR settings “'O n the
and the times at which each 'O fthe buffers pr'Ovide their st 'Ored
fly," including and n'O t limited t'O, t'O p 'O l 'O gy interc 'Onnecti 'O ns ,
VGA settings t 'O the VGAs. H 'Owever, a set 'O f m 'O re c'O nservatively selected VGA settings is st 'O red in the buffer 620c ,
data cl 'O ck settings , data width settings , VGA gain settings ,
and filter c 'O efficient settings. Als 'O, in each depicted variati 'O n 30 and these failsafe settings may be provided t'O the VGAs in
'O f triple-bufferin皂， the third buffer 620c maintains a set 'O f
resp 'O nse t 'O an 'O ut- 'O f-b 'Ound c 'Onditi 'O n being detected. Such
ANR settings deemed t 'O be “ c 'O nservative" 'O r “ failsafe" setprovisi 'O n 'O fthe VGA settings st'O red in the buffer 620c 'Overtings that may be res 'O rted t 'O bring theANR circuit 2000 back
rides the pr'Ovisi 'O n 'O f any VGA settings st 'O red in either 'O fthe
int 'O stable 'O perati 'O n and/'Or back t'O safe ac 'O ustic 'O utput levels
bu芷ers 620a and 620b
in resp 'O nse t'O an 'O ut- 'O f-b 'Ound c'O nditi 'On being detected.
35
FIG. 6b depicts the triple-buffering 'O f filter settings ,
As will be familiar t 'O th'O se skilled in the art 'O f c 'Ontrolling
including filter c 'O efficien郎， empl 'Oying variants 'O fthe buffers
digital signal processing f'O r audi 'O sign站， it is 'O ften neces620α-c that each st'O re differing 'O nes 'O ffilter settings 625. An
sary t 'O c'O'O rdinate the updating 'O f vari 'O us audi 'O processing
ex紅nple 'O f a use 'O f such triple-buffering 'O f filter c 'O efficients
settings t'O 'O ccur during intervals between the pr'O cessing 'O f
maybeadjustingtherange 'O ffrequenciesan d/'O rthedegree 'O f
pieces 'O f audi 'O data , and it is 'O ften necessary t 'O cause the 40 attenuati 'O n 'O f n 'O ise s'O unds that are reduced in the feedbackbased ANR provided by the pers 'O nal ANR device 1000. In
updating 'O f at least s'O me 'O fth'O se settings t'O be made during
the same interval. Failing t'O d'O s'O can result in the inc 'O mplete
s'Ome implementati 'O ns , pr'O cessing device 510 is caused by
programming 'O f filter c 'Oe且cler恥， an inc 'O mplete 'Or malthe ANR r 'Outine 525 t'O st'O re new filter c 'O efficients int 'O a
selected 'One 'O f the buffers 620a and 620b. At a subsequent
f 'Ormed definiti 'O n 'O f a transfer functi 'On , 'O r 'O ther mismatched
c 'Onfigurati 'O n issue that can result in undesirable s'O unds 45 time that is synchr'Onized t 'O the fl 'Ow 'O f pieces 'O f digital data
being created and ultimately ac 'O ustically 'O utput , including
thr'Ough 'O ne 'O r m 'O re 'O fthe digital filters , the settings st'O red in
and n 'Ot limited t 'O, sudden p 'O pping 'O r b 'O'O ming n 'O ises that can
the selected 'One 'O f the bu芷ers 620a and 620b are pr'Ovided t'O
surprise 'Or frighten a listener, sudden increases in v'O lnme that
th'O se digital filters , thereby av'O iding the generati 'On 'O f
are unpleasant and can be harmful t 'O a listener, 'O r h'Owling
audible artifacts. An'Other example 'O f a use 'O f such triplefeedback s'Ounds in the case 'O f updating feedback-basedANR 50 buffering 'O f filter c 'O efficients may be adjusting the cross 'Over
frequency empl 'Oyed by the digital filters within the filter
settings that can als 'O be harmfu l.
In s'O me implementati 'Ons , the buffers 620α-c 'O f any 'O f
bl 'O ck 450 in s'Ome 'O fthe ab 'Ove signal processing t 'Op 'O l'O gies
FIGS. 6a-c are dedicated hardware-implemented registers ,
t'O divide the s'O unds 'O fthe m 'O dified pass-tl宜。ugh audi 'O int'O
the c 'Ontents 'O fwhich are able t'O be cl 'O cked int'O registers
l'Owerandhigherfrequencys 'O unds.Atatimesynchr'O nizedt'O
within the VGAs , the digital filters , the summing n 'O des , the 55 at least the fl 'Ow 'O f pieces 'O f digital data ass 'O ciated with
cl 'O cks 'O f the cl 'O ck bank 570 (if present) , switch array 540 (if
pass-加'Ough audi 'O thr'Ough the digital filters 'O f the filter
present) , the DMA device 541 (ifprese凶) and/'O r 'O ther c 'O mbl 'O ck 450 , filter settings st'O red in 'O ne 'Or the 'O ther 'O f the
p 'O nents. In 'O ther implementati 'O ns , the buffers 620a-c 'O f
bu芷ers 620a and 620b are pr'Ovided t 'O at least s'O me 'O f the
FIGS. 6a-c are assigned l 'O cati 'O ns within the st'O rage 520 , the
digital filters.
c 'Ontents 'O f which are able t 'O be retrieved by the processing 60
FIG. 6c depicts the triple-buffering 'O f either all 'Or a selectdevice 510 and written by the pr'O cessing device 510 int 'O
able subset 'O f cl 'O ck , VGA , filter and t 'O p'O l'O gy settings ,
'O ther l 'O cati 'O ns within the st 'O rage 520 ass 'O ciated with instanempl 'Oying variants 'O fthe buffers 620α-c that each st'O re differing 'Ones 'O ft 'O p'O l'O gy settings 622 , filter settings 625 , VGA
tiati 'O ns 'O f the VGAs , digital filters , and summing n'O des ,
and/'Or written by the processing device 510 int 'O registers
settings 626 and cl 'O ck settings 627. An example 'O f a use 'O f
within the cl 'O cks 'O fthe cl 'O ck bank 570 (ifpresent) , the switch 的 triple-buffering 'O f all 'O f these settings may be changing from
a叮ay 540 (if present) , the DMA device 541 (if present) and/'O r
'O ne signal processing t 'O p 'O l 'O gy t 'O an 'Other in resp 'O nse t 'O a
'O ther c 'O mp 'O nents.
user 'O f the pers 'Onal ANR device 1000 'O perating a c 'Ontr'O l t'O

US 8,073 ,151 B2
37
actJvate a “ talk-through" feature in which the ANR provided
by the personal ANR device 1000 is altered to enable the user
to more easily hear the voice of another person without having to remove the personal ANR device 1000 or completely
turn offtheANR function. The processing device 510 may be
caused to store the settings required to specify a new signal
processing topology in which voice sounds are more readily
able to pass to the acoustic driver 190 from the feedforward
microphone 130 , and the various settings ofthe VGAs , digital
filters , data clocks and/or other components ofthe new signal
processing topology within one or the other of the buffers
620a and 620b. Then, at a time synchronized to the flow of at
least some pieces of digital data representing sounds through
at least one component (e 皂， anADC ， a VGA , a digital filter,
a sunmIÏng node, or a DAC), the settings are used to create the
interconnections for the new signal processing topology (by
being provided to the switch a汀ay 540 , if present) and are
provided to the components that are to be used in the new
signal processing topology.
However, some variants ofthe triple-buffering depicted in
FIG. 6c may further incorporate a mask 640 providing the
ability to determine which settings are actually updated as
either ofthe buffers 620a and 620b provide their stored contents to one or more components. In some embodiments , bit
locations within the mask are selectively set to either 1 or 0 to
selectively enable the contents of different ones ofthe settings
corresponding to each of the bit locations to be provided to
one or more components when the contents of one or the other
of the buffers 620a and 620b are to provide updated settings
to the components. The granularity ofthe mask 640 may be
such that each individual setting may be selectively enabled
for updating , or may be such that the entirety of each ofthe
topology settings 622 , the filter settings 625 , the VGA setting
626 and the clock setting 627 are able to be selected for
updating through the topology settings mask 642 , the filter
settings mask 645 , the VGA settings mask 646 and the clock
settings mask 647, respectively.
Other implementations are within the scope ofthe following claims and other claims to which the applicant may be
entitled.
The invention claimed is:
1. A method of operating a dynamically configurableANR
circuit to provide ANR in an earpiece of a personal ANR
device , the method comprising:
incorporating a plurality of digital filters of a quantity
specified by a first set of ANR settings into a filter block
located along a pathway through which digital data associated with the provision of the ANR flows within the
ANR circuit;
selecting a type of digital filter specified by a first set of
ANR settings for each digital filter from among a plurality of types of digital filter supported by the ANR
clrcmt;
adopting a filter block topology specified by the first set of
ANR settings within the filter block by configuring
interconnections 紅nong each ofthe digital filters;
configuring each ofthe digital filters with filter coe且cients
specified by the first set of ANR settings;
setting a data transfer rate at which digital data flows
through at least one ofthe digital filters as specified by
the first ANR settings;
operating the filter block to enable the ANR circuit to
provide ANR in the earpiece; and
changing an ANR setting specified by the first set of ANR
settings to an ANR setting specified by a second set of
ANR settings in syncl宜。nization with a transfer of digi tal data through at least a portion of the pathway.

38
2. The method of claim 1 , wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set ofANR settings comprises
changing at least one of:
5
an interconnection of the filter block topology specified by
the first ANR settings;
a selection of a type of digital filter specified by the first set
of ANR settings for one ofthe digital filters;
the quantity of digital filters specified by the first ANR
10
settings ofthe plurality of digital filters;
a filter coefficient specified by the first ANR settings; and
the data transfer rate specified by the first ANR settings.
3. The method of claim 1 , further comprising monitoring
an amount of power available from a pow位 so叮白， and
15 wherein changing anANR setting specified by the first set of
ANR settings to anANR setting specified by the second set of
ANR settings occurs in response to a reduction in the amount
of power available from the power source.
4. The method of claim 1 ，臼rther comprising monitoring a
20 characteristic of a sound represented by digital data , and
wherein changing anANR setting specified by the first set of
ANR settings to anANR setting specified by the second set of
ANR settings occurs in response to a change in the characteristic.
25
5. The method of claim 4 , wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set of ANR settings reduces a
degree ofANR provided by the configurable ANR circuit and
reduces consumption of power by the configurable ANR cir30 cuit from a power supply coupled to the configurable ANR
circuit.
6. The method of claim 1 , further comprising awaiting
receipt of the second set of ANR settings from an external
processing device coupled to the ANR circuit, and wherein
35 changing an ANR setting specified by the first set of ANR
settings to anANR setting specified by the second set ofANR
settings occurs inresponse to receiving the second set ofANR
settings from the external processing device.
7. The method of claim 1 , wherein:
40
theANR provided by theANR circuit comprises feedbackbased ANR; and
changing an ANR setting specified by the first set of ANR
settings to anANR setting specified by the second set of
ANR settings occurs in response to an instance of insta45
bilityinatleastthefeedback-basedANRbeingdetected,
and comprises changing a filter coefficient specified by
the first ANR settings to a filter coefficient specified by
the second ANR settings to restore stability
8. The method of claim 1 , wherein:
50
adopting a filter block topology specified by the first set of
ANR settings further comprises incorporating a summing node into the filter block, and configuring interconnectlOns 紅nong the digital filters and the summing
node as specified by the first set of ANR settings to
55
combineoutputsofatleasttwoofthedigitalfiltersatthe
summing node; and
changing an ANR setting specified by the first set of ANR
settings to anANR setting specified by the second set of
ANR settings comprises changing an interconnection of
ωthe filter block topology specified by the first ANR settings to remove the summing node and one ofthe at least
two digital filters.
9. The method of claim 1 , wherein:
adopting a filter block topology specified by the first set of
的
ANR settings further comprises configuring interconnections among a first digital filter, a second digital filter
and a third digital filter of the plurality of digital filters

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40

such that an output ofthe first digital filter is coupled to
inputs of the second and third digital filters to form a
branch in a f10w of digital data through the fir泣， second
and third digital filters; and
changing an ANR setting specified by the first set of ANR
settings to anANR setting specified by the second set of
ANR settings comprises changing an interconnection of
the filter block topology specified by the first ANR settings to uncouple the third digital filter from the first and
second digital filters.
10. The method of claim 1 , wherein:
adopting a filter block topology specified by the first set of
ANR settings further comprises configuring interconnections among a first digital filter, a second digital filter
and a third digital filter of the plurality of digital filters
such that an output ofthe first digital filter is coupled to
inputs of the second and third digital filters to form a
branch in a f10w of digital data through the fir泣， second
and third digital filters; and
configuring each ofthe digital filters with filter coefficients
specified by the first set of ANR settings comprises
configuring the second and third digital filters with coefficients that cause at least the second and third digital
filters to cooperate to form a crossover having a selected
crossover frequency.
11. The method of claim 10 , wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set ofANR settings comprises
configuring filter coefficients of the second and third digital
filters to change the crossover frequency.
12. The method of claim 1, wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set ofANR settings comprises
replaci月 one of the digital filters that is of a selected type
with another digital filter ofthe same selected type , wherein
the one ofthe digital filters supports a filter coe且cient at a first
bit width and consumes power at a first rate during operation,
and wherein the other digital filter supports the same filter
coefficient at a second bit width that is na叮ower than the first
bit width and consumes power at a second rate during operation that is lower than the first rate.
13. The method of claim 1 , wherein:
setting a data transfer rate at which digital data f1 0ws
tl宜。ugh at least one ofthe digital filters as specified by
the 且rstANR settings comprises setting a first data transfer rate at which digital data is clocked into an input of
the digital filter and clocked out of an output of the
digital filter at the first data transfer rate; and
changing anANR setting specified by the first set of ANR
settings to anANR setting specified by the second set of
ANR settings comprises:
setting a second data transfer rate at which digital data is
clocked out of the output of the digital filter, wherein
the second data transfer rate differs from the first data
transfer rate; and
setting a coefì且cient of the digital filter to convert
between the first and second data transfer rates.
14. An apparatus comprising an ANR circuit , the ANR
circuit comprising:
aADC;
a DAC;
a processing device; and
a storage in which is stored a sequence of instructions that
when executed by the processing device , causes the
processing device to:
incorporate a plurality of digital filters of a quantity
specified by a first set of ANR settings into a filter

block located along a pathway extending from the
ADC to the DAC through which digital data associated with providing ANR f1 0ws within the ANR circuit;
select a type of digital filter specified by a first set of
ANR settings for each digital filter from among a
plurality of types of digital filter supported by the
ANR circuit;
adopt a filter block topology specified by the first set of
ANR settings within the filter block by configuring
interconnections 紅nong each ofthe digital filters;
configure each ofthe digital filters with filter coefficients
specified by the first set of ANR settings;
set a data transfer rate at which digital data f10ws through
at least one of the digital filters as specified by the first
ANR settings;
cause the ADC , the filter block and the DAC to be operated to enable the ANR circuit to provide ANR using
reference sounds represented by an analog signal
received by ANR circuit through the ADC to derive
anti-noise sounds represented by an analog signal
output by the ANR circuit through the DAC; and
change an ANR setting specified by the first set of ANR
settings to anANR setting specified by a second set of
ANR settings in syncl宜。nization with a transfer of
digital data through at least a portion ofthe pathway.
15. The apparatus of claim 14 , wherein:
a plurality of filter routines is stored within the storage that
defines the plurality of types of digital filter;
each filter routine of the plurality of filter routines comprises a sequence of instructions that when executed by
the processing device causes the processing device to
perform filter calculations of a type of digital filter; and
the processi月 device is further caused to:
incorporate the plurality of digital filters and select a
type of digital filter for each digital filter by at least
instantiating each digital filter based on a filter routine
selected from the plurality of filter routines in accordance with the type of digital filter specified for each
digital filter by the first set of ANR settings; and
adopt the filter block topology and cause the ADC , the
filter block and the DAC to be operated by at least
causing digital data to be transferred among theADC ,
the digital filters and the DAC
16. The apparatus of claim 15, wherein the processing
device directly transfers digital data among the ADC , the
digital filters and the DAC.
17. The apparatus of claim 15, wherein the processing
device operates a DMA device to transfer digital data among
at least a subset ofthe ADC , the digital filters and the DAC.
18. The apparatus of claim 14, wherein the processing
device is caused to change an ANR setting specified by the
first set of ANR settings to an ANR setting specified by the
second set of ANR settings by changing at least one of:
an interconnection of the filter block topology specified by
the first ANR settings;
a selection of a type of digital filter specified by the first set
of ANR settings for one ofthe digital filters;
the quantity of digital filters specified by the first ANR
settings ofthe plurality of digital filters;
a filter coefficient specified by the first ANR settings; and
the data transfer rate specified by the first ANR settings.
19. The apparatus of claim 14 , wherein the ANR circuit
further comprises an interface to enable an amount of power
available from a power source coupled to the ANR circuit to
be monitored, and wherein the processing device is further
caused to:

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30

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40

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50

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60

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monitor the amount of power available from the power
adopt a filter block topology specified by the first set of
source; and
ANR settings further by at least configuring interconchange an ANR setting specified by the first set of ANR
nections among a first digital filter, a second digital filter
and a third digital filter of the plurality of digital filters
settings to anANR setting specified by the second set of
ANR settings in response to a reduction in the amount of 5
such that an output of the first digital filter is coupled to
power available from the power source.
inputs of the second and third digital filters to form a
20. The apparatus of claim 14 , wherein the processing
branch in a flow of digital data through the first , second
device is further caused to:
and third digital filters; and
change an ANR setting specified by the first set of ANR
monitor a characteristic of a sound represented by digital
data; and
10
settings to anANR setting specified by the second set of
change an ANR setting specified by the first set of ANR
ANR settings by at least changing an intercounection of
settings to anANR setting specified by the second set of
the filter block topology specified by the first ANR setANR settings in response to a change in the charactertings to uncouple the third digital filter from the first and
istic.
second digital filters.
27. The apparatus of claim 14, wherein the processing
21. The apparatus of claim 20 , wherein the change of an 15
ANR setting specified by the first set of ANR settings to an
device is further caused to:
ANR setting specified by the second set of ANR settings
adopt a filter block topology specified by the first set of
reduces a degree of ANR provided by the con且gurable ANR
ANR settings by at least configuring intercounections
circuit andreduces consumption of power by the configurable
紅nong a first digital filter, a second digital filter and a
ANR circuit from a power supply coupled to the configurable 20
third digital filter of the plurality of digital filters such
ANR circui t.
that an output ofthe first digital filter is coupled to inputs
of the second and third digital filters to form a branch in
22. The apparatus of claim 21 ，臼rther comprising selecting
a flow of digital data through the fir泣， second and third
at least one ANR setting of the second set of ANR settings to
digital filters; and
maintain a preselected degree of quality of sound output by
25
con且 gure each of the digital filters with filter coefficients
the configurable ANR circuit.
specified by the first set of ANR settings by at least
23. The apparatus of claim 14 , further comprising:
configuring the second and third digital filters with coefan external processing device external to the ANR circuit;
ficients that cause at least the second and third digital
wherein the ANR circuit further comprises an interface
filters to cooperate to form a crossover having a selected
coupling the ANR circuit to the external processing
30
crossover frequency.
device; and
wherein the processing device is further caused to:
28. The apparatus of claim 27, wherein the processing
device is further caused to change an ANR setting specified
await receipt of the second set of ANR settings from the
bythe first set ofANR settings to anANR setting speci自己dby
external processi月 device; and
change anANR setting specified by the first set of ANR
the second set of ANR settings by at least configuring filter
settings to anANR setting specified by the second set 35 coefficients ofthe second and third digital filters to change the
of ANR settings in response to receiving the second
crossover frequency.
29. The apparatus of claim 14, wherein the processing
set of ANR settings from the external processing
device through the interface.
device is further caused to change an ANR setting specified
24. The apparatus of claim 14 , wherein:
bythe first set ofANR settings to anANR setting speci自己dby
theANR provided by theANR circuit comprises feedback- 40 the second set ofANR settings by at least replacing one ofthe
based ANR; and
digital filters that is of a selected type with another digital
filter ofthe same selected type , wherein the one ofthe digital
the processing device is further caused to .
await detection of an instance of instability in at least the
filters supports a filter coefficient at a first bit width and
feedback-based ANR; and
consumes power at a first rate during operation, and wherein
in response to detecting an instance of instability in at 的 the other digital filter supports the same filter coe且cient at a
least the feedback-basedANR , changing anANR setsecond bit width that is na叮ower than the first bit width and
consumes power at a second rate during operation that is
ting specified by the first set of ANR settings to an
ANR setting specified by the second set of ANR setlower than the first rate.
30. The apparatus of claim 14, wherein the processing
tings by changing a filter coe且cient specified by the
first ANR settings to a filter coefficient specified by 50 device is further caused to:
set a data transfer rate at which digital data flows through at
the second ANR settings to restore stability.
least one of the digital filters as specified by the first
25. The apparatus of claim 14 , wherein the processing
ANR settings by at least setting a first data transfer rate
device is further caused to .
at which digital data is clocked into an input ofthe digital
adopt a filter block topology specified by the first set of
ANR settings by at least incorporating a summing node 55
filter and clocked out of an output of the digital filter at
the first data transfer rate; and
into the filter block; and configuri月 interconnections
among the digital filters and the summing node as speci change an ANR setting specified by the first set of ANR
fied by the first set ofANR settings to combine outputs of
settings to anANR setting specified by the second set of
at least two ofthe digital filters at the sUlllilling node; and
ANR settings by at least:
setting a second data transfer rate at which digital data is
change an ANR setting specified by the first set of ANR 60
clocked out ofthe output ofthe digital filter, wherein
settings to anANR setting specified by the second set of
ANR settings by at least changing an interconnection of
the second data transfer rate differs from the first data
the filter block topology specified by the first ANR settransfer rate; and
tings to remove the summing node and one ofthe at least
setting a coefficient of the digital filter to convert
65
between the first and second data transfer rates.
two digital filters.
26. The apparatus of claim 14 , wherein the processing
device is further caused .
to
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