Bose Corporation v. Beats Electronics LLC et al

Filing 1

COMPLAINT filed with Jury Demand - against Beats Electronics International Limited, Beats Electronics LLC - Magistrate Consent Notice to Pltf. ( Filing fee $ 400, receipt number 0311-1560024.) - filed by Bose Corporation. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3, # 4 Exhibit 4, # 5 Exhibit 5, # 6 Exhibit 6, # 7 Exhibit 7, # 8 Exhibit 8, # 9 Exhibit 9, # 10 Exhibit 10, # 11 Civil Cover Sheet)(rwc)

Exhibit 3

UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
July 07, 2014
THIS IS TO CERTIFY THAT ANNEXED HERETO IS A TRUE COPY FROM
THE RECORDS OF THIS OFFICE OF:

U.S. PATENT: 8,073,150
ISSUE DATE: December 06,2011

By Authority of the
Under Secretary of Commerce for Intellectual Property
and Director of the United States Patent and Trademark Office

M. TARVER
Certifying Officer

i'

L

IIIIII

1111111111111111111111111111 IIIII 1111111111 1111111111 11111111
US008073150B2

United States Patent

(10)

Joho et al.

c12)

(45)

(54)

Inventors: Marcel Joho, Framingham, MA (US);
Ricardo F. Carreras, Southborough,
MA(US)

(73)

Assignee: Bose Corporation, Framingham, MA
(US)

(*)

Notice:

5,724,433
5,815,582
5,825,897
5,841,856
6,035,050
6,041,126
6,061,456
6,094,489
6,118,878
6,160,893

DYNAMICALLY CONFIGURABLE ANR
SIGNAL PROCESSING TOPOLOGY

(75)

Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 420 days.

Patent No.:
US 8,073,150 B2
Date of Patent:
Dec. 6, 2011
3/1998 Engebretson et al.
A
9/1998 Claybaugh eta!.
A
10/1998 Andrea eta!.
A
A
1111998 Ide
A * 3/2000 Weinfurtner eta! .......... 3811313
A
3/2000 Terai eta!.
5/2000 Andrea eta!.
A
7/2000 Ishige et a!.
A
9/2000 Jones
A
A "' 12/2000 Saunders eta! .............. 381/71.6

(Continued)
FOREIGN PATENT DOCUMENTS
DE

3733132 AI

4/1989

(Continued)
(21)

Appl. No.: 12/430,990

(22)

Filed:

OTHER PUBLICATIONS
Apr. 28, 2009

(65)

Prior Publication Data
US 2010/0272277 Al

(51)

Invitation to Pay Additional Fees dated Jul. 26, 2010 for PCT/201 0/
032486.

(Continued)

Oct. 28, 2010

Int. Cl.

GJOK 11116

(52)
(58)

(2006.01)
U.S. Cl....................................................... 381/71.6
Field of Classification Search .................. 381/71.6
See application file for complete search history.
References Cited

(56)

U.S. PATENT DOCUMENTS
4,455,675
5,018,202
5,138,664
5,172,416
5,202,927
5,255,325
5,303,306
5,337,366
5,388,062
5,416,846
5,452,361
5,481,615
5,699,436
5,710,819

A
A
A
A
A
A
A
A
A
A
A
A
A
A

*
*
*

*

6/1984
511991
811992
12/1992
4/1993
10/1993
4/1994
811994
2/199 5
5/1995
9/1995
111996
12/1997
111998

Bose et al.
Takahashi et al.
Kimura et al.
Allie et al.
Topholm
Ishimitsu eta!.
Brillhart et al. ............... 3811315
Eguchi et al. .............. 381/71.11
Knutson .. ... ... ... ... ... .... .. 708/323
Tamura eta!.
Jones
Eatwell eta!.
Claybaugh eta!.
T.o slashed.pholm
eta! .............................. 3811316

Primary Examiner- Elvin G Enad
Assistant Examiner- Robert W Hom
(57)

ABSTRACT

In anANR circuit, possibly of a personal ANR device, each of
a feedback ANR pathway in which feedback anti-noise
sounds are generated from feedback reference sounds, a feedforward ANR pathway in which feedforward anti-noise
sounds are generated from feedforward reference sounds, and
a pass-through audio pathway in which modified passthrough audio sounds are generated from received passthrough audio sounds incorporate at least a block of filters to
perform those functions; and may each incorporate one or
more VGAs and/or summing nodes. For each of these pathways, ANR settings for interconnections of each of the pathways, coefficients of each of the filters, gain settings of any
VGA, along with still other ANR settings, are dynamically
configurable wherein dynamic configuration is performed in
synchronization with the transfer of one or more pieces of
digital data along one or more of the pathways.
24 Claims, 18 Drawing Sheets

filter bank

storage

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250, 350, 450

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US 8,073,150 B2
Page2

U.S. PATENT DOCUMENTS
6,236,731
6,418,228
6,522,753
6,567,524
6,717,537
6,741,707
6,744,882
6,829,365
6,870,940
6,937,738
6,993,140
6,996,241
7,039,195
7,215,766
7,216,139
7,248,705
7,251,335
7,260,209
7,277,722
7,292,973
7,317,802
7,433,481
7,627,127
7,706,550
7,813,515
7,822,210
7,853,028
7,885,422
7,933,420
7,945,065
7,983,908
200110039190
2003/0021429
2003/0053636
2003/0228019
2004/0138769
2004/0240677
2005/0025323
2005/0069146
2005/0078845
2005/0117754
2006/0088171
2007/0003078
2007/0076896
2007/0223715
2007/0250314
2007/0253569
2008/0025530
2008/0037801

B1 *
B1
B1 *
B1
B1
B2
B1
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B2
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A1
A1
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5/2001
7/2002
2/2003
5/2003
4/2004
5/2004
6/2004
12/2004
3/2005
8/2005
112006
212006
5/2006
5/2007
5/2007
7/2007
7/2007
8/2007
10/2007
11/2007
1/2008
10/2008
12/2009
4/2010
10/2010
10/2010
12/2010
2/2011
4/2011
5/2011
7/2011
11/2001
112003
3/2003
12/2003
7/2004
12/2004
2/2005
3/2005
4/2005
6/2005
4/2006
112007
4/2007
9/2007
10/2007
11/2007
1/2008
2/2008

Brennan et al ................ 3811316
Terai et al.
Matsuzawa et a!. ......... 381/71.1
Svean et al.
Fang eta!.
Ray eta!.
Gupta et al.
Kim
Meyer et al ................... 3811314
Armstrong et al.
Chen
Rayet al.
Svean et al.
Wurtz
Langhammer et al ........ 708/501
Mishan
Chen
Harvey et al.
Rosenzweig
Johnston et al ............ 704/200.1
Wurtz
Armstrong et al.
Aida et al.
Amadaet al.
Botti et al. .. .................. 3811120
Barnhill ............................ 38112
Fischer ......................... 3811312
Sinai ............................. 3811119
Copley et al ............... 381/71.11
Menzl et al ................... 3811314
Kuboki et al. .... ...... .... .. 704/228
Bhatnagar
Ratcliff et al. .. .............. 3811119
Goldberg et al ........... 381/71.11
Eichler et al.
Akiho
Onishi et al.
Botti et al. .. .................. 3811120
Bum
Aschoff et al. ............... 3811322
Sakawaki
Yeh
Escott et al.
Hosakaet a!.
Barath et al.
Kuboki et al.
Bose
Romesburg
Alves et al.

2008/0095383
2008/0162072
2008/0165981
2008/0192957
2008/0207123
2008/0292113
2008/0310652
2009/0034748
2009/0034768
2009/0103750
2009/0161889
2010/0166203
2010/0254550
2010/0260362
2010/0266136
2010/0266137
2010/0272275
2010/0272276
2010/0272277
2010/0272278
2010/0272279
2010/0272280
2010/0272281
2010/0272282
2010/0272283
2010/0272284
2010/0274564
2010/0310086
2010/0322432
201110130176
201110188665

A1
A1
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4/2008
7/2008
7/2008
8/2008
8/2008
1112008
12/2008
2/2009
2/2009
4/2009
6/2009
7/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
10/2010
12/2010
12/2010
6/2011
8/2011

Pan et al.
Copley et al.
Wurtz
Kubo
Andersen ..................... 455/41.1
Tian
Gustavsson
Sibbald
Lunner ......................... 3811318
Chilakapati et al .......... 381194.5
Magrath
Peissig et al.
Martinet al. . ................ 3811123
Sander et al. ................. 3811309
Kelloniemi et a!.
Sibbald et al ................ 381/71.6
Carreras eta!. .............. 381/71.6
Carreras et al ............... 381/71.6
Joho et al.
Joho et al ..................... 381/71.6
Joho et al ..................... 381/71.6
Joho et al ..................... 381/71.6
Carreras et al ............... 381/71.6
Carreras ...................... 381/71.6
Carreras
Joho et al ..................... 381/71.8
Bakalos et al. .. ............. 704/500
Magrath et al ............. 381/71.11
Clemow ....................... 381/71.1
Magrath et al ................ 455/570
Burge

FOREIGN PATENT DOCUMENTS
JP
JP

JP
JP

wo
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2254898
5341792
8006571
2005257720
2005112849
2009041012

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10/1990
12/1993
111996
9/2005
12/2005
4/2009

OTHER PUBLICATIONS
International Search Report and Written Opinion dated Oct. 1, 2010
for PCT/2010/032486.
Invitation to Pay Additional Fees dated Aug. 3, 2010 for PCT/
US2010/032557.
International Search Report and Written Opinion dated Sep. 16, 2010
for PCTIUS10/032557.

* cited by examiner

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1

2

ing a signal processing topology specified by the first set of
ANR settings by configuring interconnections among at least
the first and secondADCs, the first and second pluralities of
digital filters and the DAC so that digital data representing
TECHNICAL FIELD
5 sounds flows through the first pathway from the first ADC to
the DAC through at least the first plurality of digital filters;
This disclosure relates to personal active noise reduction
digital data representing sounds flows through the second
(ANR) devices to reduce acoustic noise in the vicinity of at
pathway from the secondADC to the DAC through at least the
least one of a user's ears.
second plurality of digital filters; and the first and second
10 pathways are combined at a first location along the first pathBACKGROUND
way and at a second location along the second pathway such
that the digital data from both the first and second pathways
Headphones and other physical configurations of personal
are combined before flowing to the DAC; configuring each
ANR device worn about the ears of a user for purposes of
digital filter of the first and second pluralities of digital filters
isolating· the user's ears from unwanted environmental
sounds have become commonplace. In particular, ANR head- 15 with filter coefficients specified by the first set of ANR settings; setting a data transfer rate at which digital data flows
phones in which unwanted environmental noise sounds are
through at least a portion ofat least one of the first and second
countered with the active generation of anti-noise sounds,
pathways as specified by the firstANR settings; operating the
have become highly prevalent, even in comparison to headfirst and second ADCs, the first and second pluralities of
phones or ear plugs employing only passive noise reduction
(PNR) technology, in which a user's ears are simply physi- 20 digital filters and the DAC to provide ANR in the earpiece;
and changing anANR setting specified by the first set ofANR
cally isolated from environmental noises. Especially of intersettings to anANR setting specified by a second set of ANR
est to users are ANR headphones that also incorporate audio
settings in synchronization with a transfer of digital data
listening functionality, thereby enabling a user to listen to
along at least a portion of at least one of the first and second
electronically provided audio (e.g., playback of recorded
audio or audio received from another device) without the 25 pathways.
Implementations may include, and are not limited to, one
intrusion of unwanted environmental noise sounds.
or more of the following features. The method may further
Unfortunately, despite various improvements made over
include incorporating a thirdADC oftheANR circuit, a third
time, existing personal ANR devices continue to suffer from
plurality of digital filters of a quantity specified by a first set
a variety of drawbacks. Foremost among those drawbacks are
undesirably high rates of power consumption leading to short 30 ofANR settings, and the DAC into a third pathway; selecting
a type of digital filter specified by the first set ofANR settings
battery life, undesirably narrow ranges of audible frequencies
for each digital filter of the third plurality of digital filters
in which unwanted environmental noise sounds are countered
from among the plurality of types of digital filter supported by
through ANR, instances of unpleasant ANR-originated
the ANR circuit; adopting a signal processing topology specisounds, and instances of actually creating more unwanted
noise sounds than whatever unwanted environmental sounds 35 tied by the first set of ANR settings further comprises configuring interconnections among a thirdADC, the third plurality
may be reduced.
of digital filters and the DAC so that digital data representing
sounds flows through the third pathway from thethirdADC to
SUMMARY
the DAC through at least the third plurality of digital filters,
In anANR circuit, possibly of a personalANR device, each 40 and the third pathway is combined with one of the first and
of a feedback ANR pathway in which feedback anti-noise
second pathways at a third location along the third pathway
sounds are generated from feedback reference sounds, a feedand at a fourth location along the one of the first and second
forward ANR pathway in which feedforward anti-noise
pathways such that the digital data from the third pathway and
sounds are generated from feedforward reference sounds, and
the one of the first and second pathways are combined before
a pass-through audio pathway in which modified pass- 45 flowingtotheDAC;configuringeachdigitalfilterofthethird
through audio sounds are generated from received passplurality of digital filters with filter coefficients specified by
through audio sounds incorporate at least a block of filters to
the first set ofANR settings; and operating the thirdADC and
perform those functions; and may each incorporate one or
the third plurality of digital filters, in conjunction with opermore VGAs and/or summing nodes. For each of these pathating the first and secondADCs, the first and second pluraliways, ANR settings for interconnections of each of the path- 50 ties of digital filters and the DAC to provide ANR in the
ways, coefficients of each of the filters, gain settings of any
earpiece.
VGA, along with still other ANR settings, are dynamically
The method may further include monitoring an amount of
configurable wherein dynamic configuration is performed in
power available from a power source, wherein changing an
ANR setting specified by the first set of ANR settings to an
synchronization with the transfer of one or more pieces of
55 ANR setting specified by the second set of ANR settings
digital data along one or more of the pathways.
In one aspect, a method of operating a dynamically conoccurs in response to a reduction in the amount of power
figurable ANR circuit to provide ANR in an earpiece of a
available from the power source; or monitoring a characteris tic of a sound represented by digital data, wherein changing
personal ANR device includes: incorporating a first ADC of
the ANR circuit, a first plurality of digital filters of a quantity
anANR setting specified by the first set ofANR settings to an
specified by a first set ofANR settings, and a DAC of theANR 60 ANR setting specified by the second set of ANR settings
circuit into a first pathway; incorporating a secondADC of the
occurs in response to a change in the characteristic; and either
ANR circuit, a second plurality of digital filters of a quantity
way, wherein changing theANR setting specified by the first
specified by the first set of ANR settings, and the DAC into a
set ofANR settings to anANR setting specified by the second
second pathway; selecting a type of digital filter specified by
set of ANR settings includes changing at least one of an
the first set of ANR settings for each digital filter of the first 65 interconnection of the signal processing topology defined by
and second pluralities of digital filters from among a plurality
the first ANR settings, a selection of a digital filter specified
of types of digital filter supported by the ANR circuit; adoptby the first ANR settings, a filter coefficient specified by the
DYNAMICALLY CONFIGURABLE ANR
SIGNAL PROCESSING TOPOLOGY

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r.nnv nrovided bv USPTO from the PIRS lmane Database on 07/01/2014

US 8,073,150 B2

3

4

firstANR settings, and a data transfer rate specified by the first
instructions that when executed by the processing device
causes the processing device to perform filter calculations of
ANR settings. The method may further include awaiting
receipt of the second set of ANR settings from an external
the type of digital filter; and the processing device is further
processing device coupled to the ANR circuit; wherein
caused to instantiate each digital filter of the first and second
changing an ANR setting specified by the first set of ANR 5 pluralities of digital filters based on filter routines of the
settings to anANR setting specified by the second set ofANR
plurality of filter routines that defines the type of digital filter
settings occurs in response to receiving the second set ofANR
specified by the first set of ANR settings. The processing
device may directly transfer digital data among the first and
settings from the external processing device. It may be that in
secondADCs, each of the digital filters of the first and second
the method: the first set of ANR settings specifies a third
location along the first pathway and a fourth location along 10 pluralities of digital filters instantiated by the processing
device, and the DAC, and/or the processing device may operthe second pathway at which the first and second pathways
ate a DMA device to transfer digital data among at least a
are combined; the first set ofANR settings specifies a split in
the second pathway that creates a first branch in the second
subset of the first and secondADCs, each ofthe digital filters
of the first and second pluralities of digital filters instantiated
pathway that is combined with the first pathway at the first
location along the first pathway and the second location along 15 by the processing device, and the DAC.
TheANR circuit may further include an interface to enable
second pathway, and creates a second branch in the second
an amount of power available from a power source coupled to
pathway that is combined with the first pathway at the third
the ANR circuit to be monitored, and the processing device
location along the first pathway and the fourth location along
may be further caused to: monitor the amount of power availthe second pathway; and adopting a signal processing topology specified by the first set of ANR settings further com- 20 able from the power source; and change an ANR setting
specified by the first set of ANR settings to an ANR setting
prises configuring interconnections among the first and secspecified by the second set of ANR settings in response to a
ond ADCs, the first and second pluralities of filters and the
DAC to create the first and second branches of the second
reduction in the amount of power available from the power
pathway.
source, wherein the change comprises a change of at least one
In one aspect, an apparatus includes an ANR circuit, and 25 of an interconnection of the signal processing topology
theANR circuit includes a firstADC; a secondADC; a DAC;
defined by the firstANR settings, a selection of a digital filter
a processing device; and a storage in which is stored a
specified by the first ANR settings, a filter coefficient specisequence of instructions. When the sequence of instructions
fied by the first ANR settings, and a data transfer rate specified
by the first ANR settings. The processing device may be
is executed by the processing device, the processing device is
caused to: incorporate the first ADC, a first plurality of digital 30 further caused to monitor a characteristic of a sound reprefilters of a quantity specified by a first set ofANR settings, and
sented by digital data; and change an ANR setting specified
the DAC into a first pathway; incorporate the secondADC, a
by the first set ofANR settings to anANR setting specified by
the second set of ANR settings in response to a change in the
second plurality of digital filters of a quantity specified by the
first set ofANR settings, and the DAC into a second pathway;
characteristic, wherein the change comprises a change of at
select a type of digital filter specified by the first set of ANR 35 least one of an interconnection ofthe signal processing topology defined by the first ANR settings, a selection of a digital
settings for each digital filter of the first and second pluralities
of digital filters from among a plurality of types of digital
filter specified by the first ANR settings, a filter coefficient
filter supported by the ANR circuit; adopt a signal processing
specified by the first ANR settings, and a data transfer rate
topology specified by the first set of ANR settings by configspecified by the first ANR settings. The processing device
uring interconnections among at least the first and second 40 may be further caused to configure interconnections among
ADCs, the first and second pluralities of digital filters and the
the firstADC, the first plurality of digital filters, the DAC and
DAC so that digital data representing sounds flows through
a VGA; and configure the VGA with a gain setting specified
the first pathway from the first ADC to the DAC through at
by the first set ofANR settings; cause the VGA to be operated
least the first plurality of digital filters; digital data representin conjunction with the first and second ADCs, the first and
ing sounds flows through the second pathway from the second 45 second pluralities of digital filters and the DAC to provide
ADC to the DAC through at least the second plurality of
ANR in the earpiece; wherein the processing device being
caused to change anANR setting specified by the first set of
digital filters; and the first and second pathways are combined
ANR settings to anANR setting specified by the second set of
at a first location along the first pathway and at a second
ANR settings comprises the processing device being caused
location along the second pathway such that the digital data
from both the first and second pathways are combined before 50 to configure the VGA with a gain setting specified by the
second set of ANR settings. The apparatus may further
flowing to the DAC; configure each digital filter of the first
and second pluralities of digital filters with filter coefficients
include an external processing device external to the ANR
circuit; wherein the ANR circuit further comprises an interspecified by the first set of ANR settings; set a data transfer
face coupling the ANR circuit to the external processing
rate at which digital data flows through at least a portion of at
least one of the first and second pathways as specified by the 55 device; and wherein the processing device oftheANR circuit
is further caused to await receipt of the second set of ANR
first ANR settings; cause the first and second ADCs, the first
settings from the external processing device and change an
and second pluralities of digital filters and the DAC to be
ANR setting specified by the first set of ANR settings to an
operated to provideANR in the earpiece; and change anANR
ANR setting specified by the second set of ANR settings in
setting specified by the first set of ANR settings to an ANR
setting specified by a second set of ANR settings in synchro- 60 response to the second set of ANR settings being received
from the external processing device through the interface.
nization with a transfer of digital data along at least a portion
In the method, above, changes to ANR settings may be
of at least one of the first and second pathways.
made in a manner selected to maintain a selected quality of
Implementations may include, and are not lilnited to, one
sound and/or selected quality ofANR, possibly while balancor more of the following features. In the ANR circuit, it may
be that a plurality of filter routines that defines a plurality of 65 ing the quality of sound and/or ANR with reducing power
consumption. Analogously, in the apparatus above, the protypes of digital filter is stored in the storage; each filter routine
cessing device may be caused to select changes in ANR
of the plurality of filter routines comprises a sequence of

Copy provided by USPTO from the PIRS lmaae Database on 07/01/2014

US 8,073,150 B2

5

6

settings to maintain a selected quality of sound and/or
selected quality of ANR, and the processing device may be
caused to select the changes in the ANR settings to balance
the quality of sound and/or ANR with reducing power consumption.
Other features and advantages of the invention will be
apparent from the description and claims that follow.

ofANR in relatively small spaces in which a person may sit or
stand, including and not limited to, phone booths, car passenger cabins, etc.
FIG. 1 provides a block diagram of a personal ANR device
1000 structured to be worn by a user to provide active noise
reduction (ANR) in the vicinity of at least one of the user's
ears. As will also be explained in greater detail, the personal
ANR device 1000 may have any of a. number of physical
configurations, some possible ones of which are depicted in
FIGS. 2a through 2/ Some of these depicted physical configurations incorporate a single earpiece 100 to provideANR
to only one of the user's ears, and others incorporate a pair of
earpieces 100 to provide ANR to both of the user's ears.
However, it should be noted that for the sake of simplicity of
discussion, only a single earpiece 100 is depicted and
described in relation to FIG. 1. As will also be explained in
greater detail, the personal ANR device 1000 incorporates at
least one ANR circuit 2000 that may provide either or both of
feedback-basedANR and feedforward-basedANR, in addition to possibly further providing pass-through audio. FIGS.
3a and 3b depict a couple of possible internal architectures of
the ANR circuit 2000 that are at least partly dynamically
configurable. Further, FIGS. 4a through 4e depict some possible signal processing topologies and FIGS. Sa through Se
depict some possible filter block topologies that may theANR
circuit 2000 may be dynamically configured to adopt. Further, the provision of either or both of feedback-based ANR
and feedforward-based ANR is in addition to at least some
degree of passive noise reduction (PNR) provided by the
structure of each earpiece 100. Still further, FIGS. 6a through
6c depict various forms of triple-buffering that may be
employed in dynamically configuring signal processing
topologies, filter block topologies and/or still other ANR
settings.
Each earpiece 100 incorporates a casing 110 having a
cavity 112 at least partly defined by the casing 110 and by at
least a portion of an acoustic driver 190 disposed within the
casing to acoustically output sounds to a user's ear. This
manner of positioning the acoustic driver 190 also partly
defines another cavity 119 within the casing 110 that is separated from the cavity 112 by the acoustic driver 190. The
casing 110 carries an ear coupling 11S surrounding an opening to the cavity 112 and having a passage 117 that is formed
through the ear coupling 11S and that communicates with the
opening to the cavity 112. In some implementations, an
acoustically transparent screen, grill or other form of perforated panel (not shown) may be positioned in or near the
passage 117 in a manner that obscures the cavity and/or the
passage 117 from view for aesthetic reasons and/or to protect
components within the casing 110 from damage. At times
when the earpiece 100 is worn by a user in the vicinity of one
of the user's ears, the passage 117 acoustically couples the
cavity 112 to the ear canal of that ear, while the ear coupling
11S engages portions of the ear to form at least some degree
of acoustic seal therebetween. This acoustic seal enables the
casing 110, the ear coupling 11S and portions of the user's
head surrounding the ear canal (including portions of the ear)
to cooperate to acoustically isolate the cavity 112, the passage
117 and the ear canal from the environment external to the
casing 110 and the user's head to at least some degree, thereby
providing some degree of PNR.
In some variations, the cavity 119 may be coupled to the
environment external to the casing 110 via one or more acoustic ports (only one of which is shown), each tuned by their
dimensions to a selected range of audible frequencies to
enhance characteristics of the acoustic output of sounds by
the acoustic driver 190 in a manner readily recognizable to

5

DESCRIPTION OF THE DRAWINGS
10

FIG. 1 is a block diagram of portions of an implementation
of a personal ANR device.
FIGS. 2a through 2/ depict possible physical configurations of the personalANR device of FIG. 1.
FIGS. 3a and 3b depict possible internal architectures of an
ANR circuit of the personal ANR device of FIG. 1.
FIGS. 4a through 4g depict possible signal processing
topologies that may be adopted by the ANR circuit of the
personal ANR device of FIG. 1.
FIGS. Sa through Se depict possible filter block topologies
that may be adopted by the ANR circuit of the personal ANR
device of FIG. 1.
FIGS. 6a through 6c depict possible variants of triplebuffering that may be adopted by the ANR circuit of the
personal ANR device of FIG. 1.

15

20

25

DETAILED DESCRIPTION
What is disclosed and what is claimed herein is intended to
be applicable to a wide variety of personal ANR devices, i.e.,
devices that are structured to be at least partly worn by a user
in the vicinity of at least one of the user's ears to provideANR
functionality for at least that one ear. It should be noted that
although various specific implementations of personal ANR
devices, such as headphones, two-way communications
headsets, earphones, earbuds, wireless headsets (also known
as "earsets") and ear protectors are presented with some
degree of detail, such presentations of specific implementations are intended to facilitate understanding through the use
of examples, and should not be taken as limiting either the
scope of disclosure or the scope of claim coverage.
It is intended that what is disclosed and what is claimed
herein is applicable to personal ANR devices that provide
two-way audio communications, one-way audio communications (i.e., acoustic output of audio electronically provided
by another device), or no communications, at all. It is
intended that what is disclosed and what is claimed herein is
applicable to personal ANR devices that are wirelessly connected to other devices, that are connected to other devices
through electrically and/or optically conductive cabling, or
that are not connected to any other device, at all. It is intended
that what is disclosed and what is claimed herein is applicable
to personal ANR devices having physical configurations
structured to be worn in the vicinity of either one or both ears
of a user, including and not limited to, headphones with either
one or two earpieces, over-the-head headphones, behind-theneck headphones, headsets with communications microphones (e.g., boom microphones), wireless headsets (i.e.,
earsets ), single earphones or pairs of earphones, as well as
hats or helmets incorporating one or two earpieces to enable
audio communications and/or ear protection. Still other
physical configurations of personal ANR devices to which
what is disclosed and what is claimed herein are applicable
will be apparent to those skilled in the art.
Beyond personal ANR devices, what is disclosed and
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those skilled in the art. Also, in some variations, one or more
tuned ports (not shown) may couple the cavities 112 and 119,
and/or may couple the cavity 112 to the environment external
to the casing 110. Although not specifically depicted, screens,
grills or other forms ofperforated or fibrous structures may be
positioned within one or more of such ports to prevent passage of debris or other contaminants therethrough and/or to
provide a selected degree of acoustic resistance therethrough.
In implementations providing feedforward-basedANR, a
feedforward microphone 130 is disposed on the exterior of
the casing 110 (or on some otherportionofthepersonalANR
device 1 000) in a manner that is acoustically accessible to the
environment external to the casing 110. This external positioning of the feedforward microphone 130 enables the feedforward microphone 130 to detect environmental noise
sounds, such as those emitted by an acoustic noise source
9900, in the environment external to the casing 110 without
the effects of any form of PNR or ANR provided by the
personal ANR device 1000. As those familiar with feedforward-based ANR will readily recognize, these sounds
detected by the feedforward microphone 130 are used as a
reference from which feedforward anti-noise sounds are
derived and then acoustically output into the cavity 112 by the
acoustic driver 190. The derivation of the feedforward antinoise sounds takes into account the characteristics ofthe PNR
provided by the personal ANR device 1000, characteristics
and position of the acoustic driver 190 relative to the feedforward microphone 130, and/or acoustic characteristics of the
cavity 112 and/or the passage 117. The feedforward antinoise sounds are acoustically output by the acoustic driver
190 with amplitudes and time shifts calculated to acoustically
interact with the noise sounds of the acoustic noise source
9900 that are able to enter into the cavity 112, the passage 117
and/or an ear canal in a subtractive manner that at least attenuates them.
In implementations providing feedback-based ANR, a
feedback microphone 120 is disposed within the cavity 112.
The feedback microphone 120 is positioned in close proximity to the opening of the cavity 112 and/or the passage 117 so
as to be positioned close to the entrance of an ear canal when
the earpiece 100 is worn by a user. The sounds detected by the
feedback microphone 120 are used as a reference from which
feedback anti-noise sounds are derived and then acoustically
output into the cavity 112 by the acoustic driver 190. The
derivation of the feedback anti-noise sounds takes into
account the characteristics and position of the acoustic driver
190 relative to the feedback microphone 120, and/or the
acoustic characteristics of the cavity 112 and/or the passage
117, as well as considerations that enhance stability in the
provision offeedback-basedANR. The feedback anti-noise
sounds are acoustically output by the acoustic driver 190 with
amplitudes and time shifts calculated to acoustically interact
with noise sounds of the acoustic noise source 9900 that are
able to enter into the cavity 112, the passage 117 and/or the
ear canal (and that have not been attenuated by whatever
PNR) in a subtractive manner that at least attenuates them.
The personal ANR device 1000 further incorporates one of
theANR circuit 2000 associated with each earpiece 100 of the
personal ANR device 1000 such that there is a one-to-one
correspondence ofANR circuits 2000 to earpieces 100. Either
a portion of or substantially all of each ANR circuit 2000 may
be disposed within the casing 110 of its associated earpiece
100. Alternatively and/or additionally, a portion of or substantially all of each ANR circuit 2000 may be disposed within
another portion of the personal ANR device 1000. Depending
on whether one or both offeedback-basedANR and feedforward-basedANR are provided in an earpiece 100 associated

with the ANR circuit 2000, the ANR circuit 2000 is coupled
to one or both of the feedback microphone 120 and the feedforward microphone 130, respectively. TheANRcircuit 2000
is further coupled to the acoustic driver 190 to cause the
acoustic output of anti-noise sounds.
In some implementations providing pass-through audio,
the ANR circuit 2000 is also coupled to an audio source 9400
to receive pass-through audio from the audio source 9400 to
be acoustically output by the acoustic driver 190. The passthrough audio, unlike the noise sounds emitted by the acoustic noise source 9900, is audio that a user of the personal ANR
device 1000 desires to hear. Indeed, the user may wear the
personalANRdevice 1000 to be able to hear the pass-through
audio without the intrusion of the acoustic noise sounds. The
pass-through audio may be a playback of recorded audio,
transmitted audio, or any of a variety of other forms of audio
that the user desires to hear. In some implementations, the
audio source 9400 may be incorporated into the personal
ANR device 1000, including and not limited to, an integrated
audio playback component or an integrated audio receiver
component. In other implementations, the personal ANR
device 1000 incorporates a capability to be coupled either
wirelessly or via an electrically or optically conductive cable
to the audio source 9400 where the audio source 9400 is an
entirely separate device from thepersonalANR device 1000
(e.g., a CD player, a digital audio file player, a cell phone,
etc.).
In other implementations pass-through audio is received
from a communications microphone 140 integrated into variants of the personal ANR device 1000 employed in two-way
communications in which the communications microphone
140 is positioned to detect speech sounds produced by the
user of the personal ANR device 1000. In such implementations, an attenuated or otherwise modified form ofthe speech
sounds produced by the user may be acoustically output to
one or both ears of the user as a communications sidetone to
enable the user to hear their own voice in a manner substantially similar to how they normally would hear their own
voice when not wearing the personal ANR device 1000.
In support ofthe operation of at least theANR circuit 2000,
the personal ANR device 1000 may further incorporate one or
both of a storage device 170, a power source 180 and/or a
processing device (not shown). As will be explained in greater
detail, the ANR circuit 2000 may access the storage device
170 (perhaps through a digital serial interface) to obtainANR
settings with which to configure feedback-based and/or feedforward-based ANR. As wiii also be explained in greater
detail, the power source 180 may be a power storage device of
limited capacity (e.g., a battery).
FIGS. 2a through 2fdepict various possible physical configurations that may be adopted by the personal ANR device
1000 ofFIG.1. As previously discussed, different implementations of the personal ANR device 1000 may have either one
or two earpieces 100, and are structured to be worn on or near
a user's head in a manner that enables each earpiece 100 to be
positioned in the vicinity of a user's ear.
FIG. 2a depicts an "over-the-head" physical configuration
1500a of the personal ANR device 1000 that incorporates a
pair of earpieces 100 that are each in the form of an earcup,
and that are connected by a headband 102. However, and
although not specifically depicted, an alternate variant of the
physical configuration 1500a may incorporate only one of the
earpieces 100 connected to the headband 102. Another alternate variant of the physical configuration 1500a may replace
the headband 102 with a different band structured to be worn
around the back of the head and/or the back of the neck of a
user.

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In the physical configuration 1500a, each of the earpieces
100 may be either an "on-ear'' (also commonly called "supraaural") or an "around-ear'' (also commonly called "circumaural") form of earcup, depending on their size relative to the
pinna of a typical human ear. As previously discussed, each
earpiece 100 has the casing 110 in which the cavity 112 is
formed, and that 110 carries the ear coupling 115. In this
physical configuration, the ear coupling 115 is in the form of
a flexible cushion (possibly ring-shaped) that surrounds the
periphery of the opening into the cavity 112 and that has the
passage 117 formed therethrough that communicates with the
cavity 112.
Where the earpieces 100 are structured to be worn as overthe-ear earcups, the casing 110 and the ear coupling 115
cooperate to substantially surround the pinna of an ear of a
user. Thus, when such a variant of the personal ANR device
1000 is correctly worn, the headband 102 and the casing 110
cooperate to press the ear coupling 115 against portions of a
side of the user's head surrounding the pinna of an ear such
that the pinna is substantially hidden from view. Where the
earpieces 100 are structured to be worn as on-earearcups, the
casing 110 and ear coupling 115 cooperate to overlie peripheral portions of a pinna that surround the entrance of an
associated ear canal. Thus, when correctly worn, the headband 102 and the casing 110 cooperate to press the ear coupling 115 against portions of the pinna in a manner that likely
leaves portions of the periphery of the pinna visible. The
pressing of the flexible material of the ear coupling 115
against either portions of a pinna or portions of a side of a head
surrounding a pinna serves both to acoustically couple the ear
canal with the cavity 112 through the passage 117, and to
form the previously discussed acoustic seal to enable the
provision of PNR.
FIG. 2b depicts another over-the-head physical configuration 1500b that is substantially similar to the physical configuration 1500a, but in which one of the earpieces 100 additionally incorporates a communications microphone 140
connected to the casing 110 via a microphone boom 142.
When this particular one of the earpieces 100 is correctly
worn, the microphone boom 142 extends from the casing 110
and generally alongside a portion of a cheek of a user to
position the communications microphone 140 closer to the
mouth of the user to detect speech sounds acoustically output
from the user's mouth. However, and although not specifically depicted, an alternative variant of the physical configuration 1500b is possible in which the communications microphone 140 is more directly disposed on the casing 110, and
the microphone boom 142 is a hollow tube that opens on one
end in the vicinity of the user's mouth and on the other end in
the vicinity of the communications microphone 140 to convey sounds from the vicinity of the user's mouth to the vicinity of the communications microphone 140.
FIG. 2b also depicts the other of the earpieces 100 with
broken lines to make clear that still another variant of the
physical configuration 1500b of the personal ANR device
1000 is possible that incorporates only the one of the earpieces 100 that incorporates the microphone boom 142 and
the communications microphone 140. In such another variant, the headband 102 would still be present and would continue to be worn over the head of the user.
FIG. 2c depicts an "in-ear" (also commonly called "intraaural") physical configuration 1500c of the personal ANR
device 1000 that incorporates a pair of earpieces 100 that are
each in the form of an in-ear earphone, and that may or may
not be connected by a cord and/or by electrically or optically
conductive cabling (not shown). However, and although not

specifically depicted, an alternate variant ofthe physical configuration 1500c may incorporate only one of the earpieces
100.
As previously discussed, each of the earpieces 100 has the
casing 110 in which the open cavity 112 is formed, and that
carries the ear coupling 115. In this physical configuration,
the ear coupling 115 is in the form of a substantially hollow
tube-like shape defining the passage 117 that communicates
with the cavity 112. In some implementations, the ear coupling 115 is formed of a material distinct from the casing 110
(possibly a material that is more flexible than that from which
the casing 110 is formed), and in other implementations, the
ear coupling 115 is formed integrally with the casing 110.
Portions of the casing 110 and/or of the ear coupling 115
cooperate to engage portions of the concha and/or the ear
canal of a user's ear to enable the casing 110 to rest in the
vicinity of the entrance of the ear canal in an orientation that
acoustically couples the cavity 112 with the ear canal through
the ear coupling 115. Thus, when the earpiece 100 is properly
positioned, the entrance to the ear canal is substantially
"plugged" to create the previously discussed acoustic seal to
enable the provision ofPNR.
FIG. 2d depicts another in-ear physical configuration
1500d of the personal ANR device 1000 that is substantially
similar to the physical configuration 1500c, but in which one
of the earpieces 100 is in the form of a single-ear headset
(sometimes also called an "earset") that additionally incorporates a communications microphone 140 disposed on the
casing 110. When this earpiece 100 is correctly worn, the
communications microphone 140 is generally oriented
towards the vicinity of the mouth of the user in a manner
chosen to detect speech sounds produced by the user. However, and although not specifically depicted, an alternative
variant of the physical configuration 1500d is possible in
which sounds from the vicinity of the user's mouth are conveyed to the communications microphone 140 through a tube
(not shown), or in which the communications microphone
140 is disposed on a boom (not shown) connected to the
casing 110 and positioning the communications microphone
140 in the vicinity of the user's mouth.
Although not specifically depicted in FIG. 2d, the depicted
earpiece 100 of the physical configuration 1500d having the
communications microphone 140 may or may not be accompanied by another earpiece having the form of an in-ear
earphone (such as one of the earpieces 100 depicted in FIG.
2c) that may or may not be connected to the earpiece 100
depicted in FIG. 2d via a cord or conductive cabling (also not
shown).
FIG. 2e depicts a two-way communications handset physical configuration 1500e ofthe personalANR device 1000 that
incorporates a single earpiece 100 that is integrally formed
with the rest of the handset such that the casing 110 is the
casing of the handset, and that may or may not be connected
by conductive cabling (not shown) to a cradle base with which
it may be paired. In a manner not unlike one of the earpieces
100 of an on-the-ear variant of either of the physical configurations 1500a and 1500b, the earpiece 100 of the physical
configuration 1500e carries a form of the ear coupling 115
that is configured to be pressed against portions of the pinna
of an ear to enable the passage 117 to acoustically couple the
cavity 112 to an ear canal. In various possible implementations, ear coupling 115 may be formed of a material distinct
from the casing 110, or may be formed integrally with the
casing 110.
FIG. 2/depicts another two-way communications handset
physical configuration 1500/ of the personal ANR device
1000 that is substantially similar to the physical configuration

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1500e, but in which the casing 110 is shaped somewhat more
an analog signal from either the audio source 9400 or the
appropriately for portable wireless communications use, poscommunications microphone 140. As will be explained in
sibly incorporating user interface controls and/or display(s)
greater detail, one or more of theADCs 210, 310 and 410 may
to enable the dialing ofphone numbers and/or the selection of
receive their associated analog signals through one or more of
radio frequency channels without the use of a cradle base.
5 the analog VGAs 125, 135 and 145, respectively. The digital
outputs of each oftheADCs 210,310 and 410 are coupled to
FIGS. 3a and 3b depict possible internal architectures,
either of which may be employed by theANR circuit 2000 in
the switch array 540. Each oftheADCs 210,310 and410 may
implementations of the personal ANR device 1000 in which
be designed to employ a variant of the widely known sigmadelta analog-to-digital conversion algorithm for reasons of
the ANR circuit 2000 is at least partially made up of dynamically configurable digital circuitry. In other words, the inter- 10 power conservation and inherent ability to reduce digital data
nal architectures of FIGS. 3a and 3b are dynamically configrepresenting audible noise sounds that might otherwise be
introduced as a result of the conversion process. However, as
urable to adopt any of a wide variety of signal processing
topologies and filter block topologies during operation of the
those skilled in the art will readily recognize, any of a variety
ANR circuit 2000. FIGS. 4a-g depict various examples of
of other analog-to-digital conversion algorithms may be
signal processing topologies that maybe adopted bytheANR 15 employed. Further, in some implementations, at least the
ADC 410 may be bypassed and/or entirely dispensed with
circuit 2000 in this manner, and FIGS. 5a-e depict various
where at least the pass-through audio is provided to theANR
examples of filter block topologies that may also be adopted
circuit 2000 as digital data, rather than as an analog signal.
by the ANR circuit 2000 for use within an adopted signal
processing topology in this manner. However, and as those
The filter bank 550 incorporates multiple digital filters,
skilled in the art will readily recognize, other implementa- 20 each ofw hich has its inputs and outputs coupled to the switch
array 540. In some implementations, all of the digital filters
tions of the personal ANR device 1000 are possible in which
the ANR circuit 2000 is largely or entirely implemented with
within the filter bank 550 are of the same type, while in other
analog circuitry and/or digital circuitry lacking such dynamic
implementations, the filter bank550 incorporates a mixture of
different types of digital filters. As depicted, the filter bank
configurability.
In implementations in which the circuitry of the ANR 25 550 incorporates a mixture of multiple downsampling filters
552, multiple biquadratic (biquad) filters 554, multiple intercircuit 2000 is at least partially digital, analog signals reprepolating filters 556, and multiple finite impulse response
senting sounds that are received or output by theANR circuit
(FIR) filters 558, although other varieties of filters may be
2000 may require conversion into or creation from digital
incorporated, as those skilled in the art will readily recognize.
data that also represents those sounds. More specifically, in
both of the internal architectures 2200a and 2200b, analog 30 Further, among each of the different types of digital filters
may be digital filters optimized to support different data transsignals received from the feedback microphone 120 and the
feedforward microphone 130, as well as whatever analog
fer rates. By way of example, differing ones of the biquad
filters 554 may employ coefficient values of differing bitsignal representing pass-through audio may be received from
widths, or differing ones of the FIR filters 558 may have
either the audio source 9400 or the communications microphone 140, are digitized by analog-to-digital converters 35 differing quantities of taps. The VGA bank 560 (if present)
(ADCs) of the ANR circuit 2000. Also, whatever analog
incorporates multiple digital VGAs, each of which has its
inputs and outputs coupled to the switch array 540. Also, the
signal is provided to the acoustic driver 190 to cause the
acoustic driver 190 to acoustically output anti-noise sounds
DAC 910 has its digital input coupled to the switch array 540.
and/or pass-through audio is created from digital data by a
The clock bank 570 (ifpresent) provides multiple clock signal
digital-to-analog converter (DAC) of the ANR circuit 2000. 40 outputs coupled to the switch array 540 that simultaneously
provide multiple clock signals for clocking data between
Further, either analog signals or digital data representing
sounds may be manipulated to alter the amplitudes of those
components at selected data transfer rates and/or other purposes. In some implementations, at least a subset of the mulrepresented sounds by either analog or digital forms, respectiple clock signals are synchronized multiples of one another
tively, of variable gain amplifiers (VGAs).
FIG. 3a depicts a possible internal architecture 2200a of 45 to simultaneously support different data transfer rates in diftheANR circuit 2000 in which digital circuits that manipulate
ferent pathways in which the movement of data at those
different data transfer rates in those different pathways is
digital data representing sounds are selectively interconsynchronized.
nected through one or more arrays of switching devices that
The switching devices of the switch array 540 are operable
enable those interconnections to be dynamically configured
during operation of the ANR circuit 2000. Such a use of 50 to selectively couple different ones of the digital outputs of
switching devices enables pathways for movement of digital
the ADCs 210, 310 and 410; the inputs and outputs of the
data among various digital circuits to be defined through
digital filters of the filter bank 550; the inputs and outputs of
the digital VGAs of the VGA bank 560; and the digital input
programming. More specifically, blocks of digital filters of
varying quantities and/or types are able to be defined through
of the DAC 910 to form a set of interconnections therebewhich digital data associated with feedback-based ANR, 55 tween that define a topology ofpathways for the movement of
feedforward-basedANR and pass-through audio are routed to
digital data representing various sounds. The switching
devices of the switch array 540 may also be operable to
perform these functions. In employing the internal architecselectively couple different ones ofthe clock signal outputs of
ture 2200a, the ANR circuit 2000 incorporates ADCs 210,
the clock bank 570 to different ones ofthe digital filters of the
310 and 410; a processing device 510; a storage 520; an
interface (I/F) 530; a switch array 540; a filter bank 550; and 60 filter bank 550 and/or different ones ofthe digital VGAs ofthe
VGA bank 560. It is largely in this way that the digital cira DAC 910. Various possible variations may further incorpo~
cuitry of the internal architecture 2200a is made dynamically
rate one or more of analog VGAs 125, 135 and 145; a VGA
configurable. In this way, varying quantities and types of
bank 560; a clock bank 570; a compression controller 950; a
digital filters and/or digital VGAs may be positioned at varifurther ADC 955; and/or an audio amplifier 960.
The ADC 210 receives an analog signal from the feedback 65 ous points along different pathways defined for flows of digital data associated with feedback-basedANR, feedforwardmicrophone 120, theADC 310 receives an analog signal from
based ANR and pass-through audio to modifY sounds
the feedforwardmicrophone 130, and theADC 410 receives

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represented by the digital data and/or to derive new digital
data representing new sounds in each of those pathways.
Also, in this way, different data transfer rates may be selected
by which digital data is clocked at different rates in each of the
pathways.
In support of feedback-based ANR, feedforward-based
ANR and/or pass-through audio, the coupling of the inputs
and outputs of the digital filters within the filter bank 550 to
the switch array 540 enables inputs and outputs of multiple
digital filters to be coupled through the switch array 540 to
create blocks of filters. As those skilled in the art will readily
recognize, by combining multiple lower-order digital filters
into a block of filters, multiple lower-order digital filters may
be caused to cooperate to implement higher order functions
without the use of a higher-order filter. Further, in implementations having a variety of types of digital filters, blocks of
filters may be created that employ a mix of filters to perform
a still greater variety of functions. By way of example, with
the depicted variety of filters within the filter bank 550, a filter
block (i.e., a block of filters) may be created having at least
one of the downsampling filters 552, multiple ones of the
biquad filters 554, at least one of the interpolating filters 556,
and at least one of the FIR filters 558.
In some implementations, at least some of the switching
devices of the switch array 540 may be implemented with
binary logic devices enabling the switch array 540, itself, to
be used to implement basic binary math operations to create
summing nodes where pathways along which different pieces
of digital data flow are brought together in a manner in which
those different pieces of digital data are arithmetically
summed, averaged, and/or otherwise combined. In such
implementations, the switch array 540 may be based on a
variant of dynamically programmable array oflogic devices.
Alternatively and/or additionally, a bank of binary logic
devices or other form of arithmetic logic circuitry (not shown)
may also be incorporated into the ANR circuit 2000 with the
inputs and outputs of those binary logic devices and/or other
form of arithmetic logic circuitry also being coupled to the
switch array 540.
In the operation of switching devices of the switch array
540 to adopt a topology by creating pathways for the flow of
data representing sounds, priority may be given to creating a
pathway for the flow of digital data associated with feedbackbased ANR that has as low a latency as possible through the
switching devices. Also, priority may be given in selecting
digital filters and VGAs that have as low a latency as possible
from among those available in the filter bank 550 and the
VGA bank 560, respectively. Further, coefficients and/or
other settings provided to digital filters of the filter bank 550
that are employed in the pathway for digital data associated
with feedback-based ANR may be adjusted in response to
whatever latencies are incurred from the switching devices of
the switch array 540 employed in defining the pathway. Such
measures may be taken in recognition ofthe higher sensitivity
of feedback-based ANR to the latencies of components
employed in performing the function of deriving and/or
acoustically outputting feedback anti-noise sounds.Although
such latencies are also of concern in feedforward- bas edANR,
feedforward-based ANR is generally less sensitive to such
latencies than feedback-based ANR. As a result, a degree of
priority less than that given to feedback-based ANR, but
greater than that given to pass-through audio, may be given to
selecting digital filters and VGAs, and to creating a pathway
for the flow of digital data associated with feedforward-based
ANR.
The processing device 510 is coupled to the switch array
540, as well as to both the storage 520 and the interface 530.

The processing device 510 may be any of a variety of types of
processing device, including and not limited to, a general
purpose central processing unit (CPU), a digital signal processor (DSP), a reduced instruction set computer (RISC)
processor, a microcontroller, or a sequencer. The storage 520
may be based on any of a variety of data storage technologies,
including and not limited to, dynamic random access memory
(DRAM), static random access memory (SRAM), ferromagnetic disc storage, optical disc storage, or any of a variety of
nonvolatile solid state storage technologies. Indeed, the storage 520 may incorporate both volatile and nonvolatile portions. Further, it will be recognized by those skilled in the art
that although the storage 520 is depicted and discussed as if it
were a single component, the storage 520 may be made up of
multiple components, possibly including a combination of
volatile and nonvolatile components. The interface 530 may
support the coupling ofthe ANR circuit 2000 to one or more
digital communications buses, including digital serial buses
by which the storage device 170 (not to be confused with the
storage 520) and/or other devices external to the ANR circuit
2000 (e.g., other processing devices, or other ANR circuits)
may be coupled. Further, the interface 530 may provide one or
more general purpose input/output (GPIO) electrical connections and/or analog electrical connections to support the coupling of manually-operable controls, indicator lights or other
devices, such as a portion of the power source 180 providing
an indication of available power.
In some implementations, the processing device 510
accesses the storage 520 to read a sequence of instructions of
a loading routine 522, that when executed by the processing
device 510, causes the processing device 510 to operate the
interface 530 to access the storage device 170 to retrieve one
or both of the ANR routine 525 and the ANR settings 527, and
to store them in the storage 520. In other implementations,
one or both of the ANR routine 525 and the ANR settings 527
are stored in a nonvolatile portion of the storage 520 such that
they need not be retrieved from the storage device 170, even
if power to the ANR circuit 2000 is lost.
Regardless of whether one or both of the ANR routine 525
and the ANR settings 527 are retrieved from the storage
device 170, or not, the processing device 510 accesses the
storage 520 to read a sequence of instructions of the ANR
routine 525. The processing device 510 then executes that
sequence of instructions, causing the processing device 510
to configure the switching devices of the switch array 540 to
adopt a topology defining pathways for flows of digital data
representing sounds and/or to provide differing clock signals
to one or more digital filters and/or VGAs, as previously
detailed. In some implementations, the processing device 510
is caused to configure the switching devices in a manner
specified by a portion of the ANR settings 527, which the
processing device 510 is also caused to read from the storage
520. Further, the processing device 510 is caused to set filter
coefficients of various digital filters of the filter bank 550,
gain settings of various VGAs of the VGA bank 560, and/or
clock frequencies of the clock signal outputs of the clock bank
570 in a manner specified by a portion of the ANR settings_
527.
In some implementations, the ANR settings 527 specify
multiple sets of filter coefficients, gain settings, clock frequencies and/or configurations ofthe switching devices of the
switch array 540, of which different sets are used in response
to different situations. In other implementations, execution of
sequences of instructions of the ANR routine 525 causes the
processing device 510 to derive different sets of filter coefficients, gain settings, clock frequencies and/or switching
device configurations in response to different situations. By

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way of example, the processing device 510 may be caused to
operate the interface 530 to monitor a signal from the power
source 180 that is indicative of the power available from the
power source 180, and to dynamically switch between different sets of filter coefficients, gain settings, clock frequencies 5
and/or switching device configurations in response to
changes in the amount of available power.
By way ofanother example, the processing device 510 may
be caused to monitor characteristics of sounds represented by
digital data involved in feedback-based ANR, feedforward- 10
basedANR and/or pass-through audio to determine whether
or not it is desirable to alter the degree feedback -based and/or
feedforward-based ANR provided. As wiJJ be familiar to
those skilled in the art, while providing a high degree ofANR
can be very desirable where there is considerable environ- 15
mental noise to be attenuated, there can be other situations
where the provision of a high degree of ANR can actually
create a noisier or otherwise more unpleasant acoustic environment for a user of a personal ANR device than would the
provision ofless ANR. Therefore, the processing device 510 20
may be caused to alter the provision of ANR to adjust the
degree of attenuation and/or the range offrequencies of environmental noise attenuated by the ANR provided in response
to observed characteristics of one or more sounds. Further, as
wiJI also be familiar to those skilled in the art, where a reduc- 25
tion in the degree of attenuation and/or the range of frequencies is desired, it may be possible to simplify the quantity
and/or type of filters used in implementing feedback-based
and/or feedforward-based ANR, and the processing device
510 may be caused to dynamically switch between different 30
sets offilter coefficients, gain settings, clock frequencies and/
or switching device configurations to perform such simplifying, with the added benefit of a reduction in power consumption.
The DAC 910 is provided with digital data from the switch 35
array 540 representing sounds to be acoustically output to an
ear of a user of the personal ANR device 1000, and converts
it to an analog signal representing those sounds. The audio
amplifier 960 receives this analog signal from the DAC 910,
and amplifies it sufficiently to drive the acoustic driver 190 to 40
effect the acoustic output of those sounds.
The compression controller 950 (if present) monitors the
sounds to be acoustically output for an indication of their
amplitude being too high, indications of impending instances
of clipping, actual instances ofclipping, and/or other impend- 45
ing or actual instances of other audio artifacts. The compression controller 150 may either directly monitor digital data
provided to the DAC 910 or the analog signal output by the
audio amplifier 960 (through the ADC 955, if present). In
response to such an indication, the compression controller 50
950may alter gain settings ofoneormoreoftheanalogVGAs
125, 135 and 145 (ifpresent); and/or one or more ofthe VGAs
of the VGA bank 560 placed in a pathway associated with one
or more of the feedback-based ANR, feedforward-based
ANR and pass-through audio functions to adjust amplitude, 55
as wiJI be explained in greater detail. Further, in some implementations, the compression controller 950 may also make
such an adjustment in response to receiving an external control signal. Such an extemal signal may be provided by
another component coupled to the ANR circuit 2000 to pro- 60
vide such an external control signal in response to detecting a
condition such as an exceptionally loud environmental noise
sound that may cause one or both of the feedback-based and
feedforward-based ANR functions to react unpredictably.
FIG. 3b depicts another possible intemal architecture 65
2200b of the ANR circuit 2000 in which a processing device
accesses and executes stored machine-readable sequences of

16
instructions that cause the processing device to manipulate
digital data representing sounds in a manner that can be
dynamically configured during operation oftheANR circuit
2000. Such a use of a processing device enables pathways for
movement of digital data of a topology to be defined through
programming. More specifically, digital filters of varying
quantities and/or types are able to be defined and instantiated
in which each type of digital filter is based on a sequence of
instructions. In employing the internal architecture 2200b,
the ANR circuit 2000 incorporates the ADCs 210, 310 and
410; the processing device 510; the storage 520; the interface
530; a direct memory access (DMA) device 540; and the DAC
910. Various possible variations may further incorporate one
or more ofthe analog VGAs 125, 135 and 145; theADC 955;
and/or the audio amplifier 960. The processing device 510 is
coupled directly or indirectly via one or more buses to the
storage 520; the interface 530; the DMA device 540; the
ADCs 210, 310 and 410; and the DAC 910 to at least enable
the processing device 510 to control their operation. The
processing device 510 may also be similarly coupled to one or
more ofthe analog VGAs 125, 135 and 145 (if present); and
to theADC 955 (if present).
As in the internal architecture 2200a, the processing device
510 may be any ofa variety oftypes ofprocessing device, and
once again, the storage 520 may be based on any of a variety
of data storage technologies and may be made up of multiple
components. Further, the interface 530 may support the coupling of the ANR circuit 2000 to one or more digital communications buses, and may provide one or more general purpose input/output (GPIO) electrical connections and/or
analog electrical connections. The DMA device 540 may be
based on a secondary processing device, discrete digital logic,
a bus mastering sequencer, or any of a variety of other technologies.
Stored within the storage 520 are one or more of a loading
routine 522, an ANR routine 525, ANR settings 527, ANR
data 529, a downsampling filter routine 553, a biquad filter
routine 555, an interpolating filter routine 557, a FIR filter
routine 559, and a VGA routine 561. In some implementations, the processing device 510 accesses the storage 520 to
read a sequence ofinstructions ofthe loading routine 522, that
when executed by the processing device 510, causes the processing device 510 to operate the interface 530 to access the
storage device 170 to retrieve one or more oftheANRroutine
525, the ANR settings 527, the downsampling filter routine
553, the biquad filter routine 555, the interpolating filter routine 557, the FIR routine 559 and the VGA routine 561, and to
store them in the storage 520. In other implementations, one
or more of these are stored in a nonvolatile portion of the
storage 520 such that they need not be retrieved from the
storage device 170.
As was the case in the internal architecture 2200a, theADC
210 receives an analog signal from the feedback microphone
120, the ADC 310 receives an analog signal from the feedforward microphone 130, and theADC 410 receives an analog signal from either the audio source 9400 or the communications microphone 140 (unless the use of one or more of
the ADCs 210, 310 and 410 is obviated through the direct
receipt of digital data). Again, one or more of the ADCs 210,
310 and 410 may receive their associated analog signals
through one or more of the analog VGAs 125, 135 and 145,
respectively. As was also the case in the internal architecture
2200a, the DAC 910 converts digital data representing sounds
to be acoustically output to an ear of a user of the personal
ANR device 1000 into an analog signal, and the audio amplifier 960 amplifies this signal sufficiently to drive the acoustic
driver 190 to effect the acoustic output of those sounds.

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However, unlike the internal architecture 2200a where
digital data representing sounds were routed via an array of
switching devices, such digital data is stored in and retrieved
from the storage 520. In some implementations, the processing device 510 repeatedly accesses the ADCs 210, 310 and
410 to retrieve digital data associated with the analog signals
they receive for storage in the storage 520, and repeatedly
retrieves the digital data associated with the analog signal
output by the DAC 910 from the storage 520 and provides that
digital data to the DAC 910 to enable the creation of that
analog signal. In other implementations, the DMA device 540
(if present) transfers digital data among theADCs 210, 310
and 410; the storage 520 and the DAC 910 independently of
the processing device 510. In still other implementations, the
ADCs 210,310 and410 and/ortheDAC910 incorporate"bus
mastering" capabilities enabling each to write digital data to
and/ or read digital data from the storage 520 independently of
the processing device 510. TheANR data 529 is made up of
the digital data retrieved from the ADCs 210, 310 and 410,
and the digital data provided to the DAC 910 by the processing device 510, the DMA device 540 and/or bus mastering
functionality.
The downsampling filter routine 553, the biquad filter routine 555, the interpolating filter routine 557 and the FIR filter
routine 559 are each made up of a sequence of instructions
that cause the processing device 510 to perform a combination of calculations that define a downsampling filter, a
biquad filter, an interpolating filter and a FIR filter, respectively. Further, among each of the different types of digital
filters may be variants of those digital filters that are optimized for different data transfer rates, including and not limited to, differing bit widths of coefficients or differing quantities of taps. Similarly, the VGA routine 561 is made up of a
sequence of instructions that cause the processing device 510
to perform a combination of calculations that define a VGA.
Although not specifically depicted, a summing node routine
may also be stored in the storage 520 made up of a sequence
of instructions that similarly defines a summing node.
The ANR routine 525 is made up of a sequence of instructions that cause the processing device 510 to create a signal
processing topology having pathways incorporating varying
quantities of the digital filters andVGAs defined by the downsampling filter routine 553, the biquad filter routine 555, the
interpolating filter routine 557, the FIR filter routine 559 and
the VGA routine 561 to support feedback-based ANR, feedforward-based ANR and/or pass-through audio. The ANR
routine 525 also causes the processing device 510 to perform
the calculations defining each ofthe various filters and VGAs
incorporated into that topology. Further, theANR routine 525
either causes the processing device 510 to perform the moving of data among ADCs 210, 310 and 410, the storage 520
and the DAC 910, or causes the processing device 510 to
coordinate the performance of such moving of data either by
the DMA device 540 (if present) or by bus mastering operations performed by the ADCs 210, 310 and 410, and/or the
DAC910.
The ANR settings 527 is made up of data defining topology
characteristics (including selections of digital filters), filter
coefficients, gain settings, clock frequencies, data transfer
rates and/or data sizes. In some implementations, the topology characteristics may also define the characteristics of any
summing nodes to be incorporated into the topology. The
processing device 510 is caused by the ANR routine 525 to
employ such data taken from theANR settings 527 in creating
a signal processing topology (including selecting digital filters), setting the filter coefficients for each digital filter incorporated into the topology, and setting the gains for each VGA

incorporated into the topology. The processing device 510
may be further caused by theANRroutine 525 to employ such
data from the ANR settings 527 in setting clock frequencies
and/or data transfer rates fortheADCs 210, 310 and 410; for
the digital filters incorporated into the topology; for the VGAs
incorporated into the topology; and for the DAC 910.
In some implementations, the ANR settings 527 specify
multiple sets of topology characteristics, filter coefficients,
gain settings, clock frequencies and/or data transfer rates, of
which different sets are used in response to different situations. In other implementations, execution of sequences of
instructions of the ANR routine 525 causes the processing
device 510 to derive different sets of filter coefficients, gain
settings, clock frequencies and/or data transfer rates for a
given signal processing topology in different situations. By
way of example, the processing device 510 may be caused to
operate the interface 530 to monitor a signal from the power
source 180 that is indicative of the power available from the
power source 180, and to employ different sets of filter coefficients, gain settings, clock frequencies and/or data transfer
rates in response to changes in the amount of available power.
By way of another example, the processing device 510 may
be caused to alter the provision ofANR to adjust the degree of
ANR required in response to observed characteristics of one
or more sounds. Where a reduction in the degree of attenuation and/or the range of frequencies of noise sounds attenuated is possible and/or desired, it may be possible to simplify
the quantity and/or type of filters used in implementing feedback-basedand/or feedforward-basedANR, and the processing device 510 may be caused to dynamically switch between
different sets of filter coefficients, gain settings, clock frequencies and/or data transfer rates to perform such simplifying, with the added benefit of a reduction in power consumption.
Therefore, in executing sequences of instructions of the
ANR routine 525, the processing device 510 is caused to
retrieve data from the ANR settings 527 in preparation for
adopting a signal processing topology defining the pathways
to be employed by the processing device 510 in providing
feedback-based ANR, feedforward-based ANR and passthrough audio. The processing device 510 is caused to instantiate multiple instances of digital filters, VGAs and/or summing nodes, employing filter coefficients, gain settings and/or
other data from theANR settings 527. The processing device
510 is then further caused to perform the calculations defining
each of those instances of digital filters, VGAs and summing
nodes; to move digital data among those instances of digital
filters, VGAs and summing nodes; and to at least coordinate
the moving of digital data among the ADCs 210, 310 and 410,
the storage 520 and the DAC 910 in a manner that conforms
to the data retrieved from the ANR settings 527. At a subsequent time, the ANR routine 525 may cause the processing
device 510 to change the signal processing topology, a digital
filter, filter coefficients, gain settings, clock frequencies and/
or data transfer rates during operation of the personal ANR
device 1000. It is largely in this way that the digital circuitry
of the internal architecture 2200b is made dynamically configurable. Also, in this way, varying quantities and types of·
digital filters and/or digital VGAs may be positioned at various points along a pathway of a topology defined for a flow of
digital data to modify sounds represented by that digital data
and/or to derive new digital data representing new sounds, as
will be explained in greater detail.
In some implementations, theANRroutine 525 may cause
the processing device 510 to give priority to operating the
ADC 210 and performing the calculations of the digital filters, VGAs and/or summing nodes positioned along the path-

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way defined for the flow of digital data associated with feedback-based ANR. Such a measure may be taken in
recognition ofthe higher sensitivity offeedback-basedANR
to the latency between the detection of feedback reference
sounds and the acoustic output of feedback anti-noise sounds.
The processing device 510 may be further caused by the
ANR routine 525 to monitor the sounds to be acoustically
output for indications of the amplitude being too high, clipping, indications of clipping about to occur, and/or other
audio artifacts actually occurring or indications of being
about to occur. The processing device 510 may be caused to
either directly monitor digital data provided to the DAC 910
or the analog signal output by the audio amplifier 960
(through the ADC 955) for such indications. In response to
such an indication, the processing device 510 may be caused
to operate one or more of the analog VGAs 125, 135 and 145
to adjust at least one amplitude of an analog signal, and/or
may be caused to operate one or more of the VGAs based on
the VGA routine 561 and positioned within a pathway of a
topology to adjust the amplitude of at least one sound represented by digital data, as will be explained in greater detail.
FIGS. 4a through 4g depict some possible signal processing topologies that may be adopted by the ANR circuit 2000
of the personal ANR device 1000 of FIG. 1. As previously
discussed, some implementations ofthe personalANR device
1000 may employ a variant oftheANR circuit 2000 that is at
least partially programmable such that the ANR circuit 2000
is able to be dynamically configured to adopt different signal
processing topologies during operation of the ANR circuit
2000. Alternatively, other implementations of the personal
ANR device 1000 may incorporate a variant of the ANR
circuit 2000 that is substantially inalterably structured to
adopt one unchanging signal processing topology.
As previously discussed, separate ones of the ANR circuit
2000 are associated with each earpiece 100, and therefore,
implementations of the personal ANR device 1000 having a
pair of the earpieces 100 also incorporate a pair of the ANR
circuits 200 0. However, as those skilled in the art will readily
recognize, other electronic components incorporated into the
personal ANR device 1000 in support of a pair of the ANR
circuits 2000, such as the power source 180, may not be
duplicated. For the sake of simplicity of discussion and understanding, signal processing topologies for only a single ANR
circuit 2000 are presented and discussed in relation to FIGS.
4a-g.
As also previously discussed, different implementations of
the personal ANR device 1000 may provide only one of either
feedback-based ANR or feedforward-based ANR, or may
provide both. Further, different implementations may or may
not additionally provide pass-through audio. Therefore,
although signal processing topologies implementing all three
offeedback-basedANR, feedforward-basedANR and passthrough audio are depicted in FIGS. 4a-g, it is to be understood that variants of each of these signal processing topologies are possible in which only one or the other of these two
forms of ANR is provided, and/or in which pass-through
audio is not provided. In implementations in which the ANR
circuit 2000 is at least partially programmable, which ofthese
two forms of ANR are provided and/or whether or not both
forms of ANR are provided may be dynamically selectable
during operation ofthe ANR circuit 2000.
FIG. 4a depicts a possible signal processing topology
2500a for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500a, the ANR circuit 2000
incorporates at least the DAC 910, the compression controller
950, and the audio amplifier 960. Depending, in part on

whether one or both of feedback-based and feedforwardbased ANR are supported, the ANR circuit 2000 further
incorporates one or more of the ADCs 210, 310, 410 and/or
955; filter blocks 250, 350 and/or 450; and/or summing nodes
270 and/or 290.
Where the provision offeedback-basedANR is supported,
the ADC 210 receives an analog signal from the feedback
microphone 120 representing feedback reference sounds
detected by the feedback microphone 120. The ADC 210
digitizes the analog signal from the feedback microphone
120, and provides feedback reference data corresponding to
the analog signal output by the feedback microphone 120 to
the filter block 250. One or more digital filters within the filter
block250 are employed to modify the data from theADC210
to derive feedback anti-noise data representing feedback antinoise sounds. The filter block 250 provides the feedback
anti-noise data to the VGA 280, possibly through the summing node 270 where feedforward-based ANR is also supported.
Where the provision of feedforward-based ANR is also
supported, the ADC 310 receives an analog signal from the
feedforwardmicrophone 130, digitizes it, and provides feedforward reference data corresponding to the analog signal
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
employed to modify the feedforward reference data received
from the ADC 310 to derive feedforward anti-noise data
representing feedforward anti-noise sounds. The filter block
350 provides the feedforward anti-noise data to the VGA 280,
possibly through the summing node 270 where feedbackbasedANR is also supported.
At the VGA 280, the amplitude of one or both of the
feedback and feedforward anti-noise sounds represented by
the data received by the VGA 280 (either through the summing node 270, or not) may be altered under the control of the
compression controller 950. The VGA 280 outputs its data
(with or without amplitude alteration) to the DAC 910, possibly through the summing nodes 290 where talk-through
audio is also supported.
In some implementations where pass-through audio is supported, the ADC 410 digitizes an analog signal representing
pass-through audio received from the audio source 9400, the
communications microphone 140 or another source and provides the digitized result to the filter block 450. In other
implementations where pass-through audio is supported, the
audio source 9400, the communications microphone 140 or
another source provides digital data representing passthrough audio to the filter block 450 without need of analogto-digital conversion. One or more digital filters within the
filter block 450 are employed to modify the digital data representing the pass-through audio to derive a modified variant
of the pass-through audio data in which the pass-through
audio may be re-equalized and/or enhanced in other ways.
The filter block 450 provides the pass-through audio data to
the summing node 290 where the pass-through audio data is
combined with the data being provided by the VGA 280 to the
DAC910.
The analog signal output by the DAC 910 is provided to th~
audio amplifier 960 to be amplified sufficiently to drive the
acoustic driver 190 to acoustically output one or more of
feedback anti-noise sounds, feedforward anti-noise sounds
and pass-through audio. The compression controller950 controls the gainofthe VGA 280 to enable the amplitude of sound
represented by data output by one or both of the filter blocks
250 and 350 to be reduced in response to indications of
impending instances of clipping, actual occurrences of clipping and/or other undesirable audio artifacts being detected

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provision of the feedforward anti -noise through the pathway
by the compression controller 950. The compression control300 and/or pass-through audio through the pathway 400.
ler 950 may either monitor the data being provided to the
In recognition of the likelihood that the pass-through audio
DAC 910 by the summing node 290, or may monitor the
function may be even more tolerant of a greater latency and a
analog signal output of the audio amplifier 960 through the
5 lower sampling rate than the feedforward-based ANR funcADC955.
tion, the data transfer rate employed in that portion of the
As further depicted in FIG. 4a, the signal processing topolpathway 400 may be still lower than the data transfer rate of
ogy 2500a defines multiple pathways along which digital
that portion of the pathway 300. To support such differences
data associated with feedback-based ANR, feedforwardin transfer rates in one variation, one or both of the summing
based ANR and pass-through audio flow. Where feedbackbased ANR is supported, the flow of feedback reference data 10 nodes 270 and 290 may incorporate sample-and-hold, buffering or other appropriate functionality to enable the combinand feedback anti-noise data among at least theADC 210, the
ing of digital data received by the summing nodes 270 and
filter block 250, the VGA 280 and the DAC 910 defines a
290 at different data transfer rates. This may entail the provifeedback-basedANR pathway 200. Similarly, where feedforsion of two different data transfer clocks to each of the sumward-based ANR is supported, the flow of feedforward reference data and feedforward anti-noise data among at least 15 ming nodes 270 and 290. Alternatively, to support such differences in transfer rates in another variation, one or both of
the ADC 310, the filter block 350, the VGA 280 and the DAC
the filter blocks 350 and 450 may incorporate an upsampling
910 defines a feedforward-basedANR pathway 300. Further,
capability (perhaps through the inclusion of an interpolating
where pass-through audio is supported, the flow of passfilter or other variety of filter incorporating an upsampling
through audio data and modified pass-through audio data
among at least theADC 410, the filter block 450, the summing 20 capability) to increase the data transfer rate at which the filter
blocks 350 and 450 provide digital data to the summing nodes
node 290 and the DAC 910 defines a pass-through audio
270 and 290, respectively, to match the data transfer rate at
pathway 400. Where both feedback-based and feedforwardwhich the filter block 250 provides digital data to the sumbased ANR are supported, the pathways 200 and 300 both
ming node 270, and subsequently, to the sunnning node 290.
further incorporate the summing node 270. Further, where
It may be that in some implementations, multiple power
pass-through audio is also supported, the pathways 200 and/ 25
modes may be supported in which the data transfer rates ofthe
or 300 incorporate the summing node 290.
pathways 300 and 400 are dynamically altered in response to
In some implementations, digital data representing sounds
the availability of power from the power source 180 and/or in
may be clocked through all of the pathways 200, 300 and 400
response to changing ANR requirements. More specifically,
that are present at the same data tra:llsfer rate. Thus, where the
pathways 200 and 300 are combined at the summing node 30 the data transfer rates of one or both of the pathway 3 00 and
400 up to the points where they are combined with the path270, and/or where the pathway 400 is combined with one or
way 200 may be reduced in response to an indication of
both of the pathways 200 and 300 at the summing node 400,
diminishing power being available from the power supply
all digital data is clocked through at a common data transfer
180 and/orinresponse to the processing device 510 detecting
rate, and that common data transfer rate may be set by a
common synchronous data transfer clock. However, as is 35 characteristics in sounds represented by digital data indicating that the degree of attenuation and/or range of frequencies
known to those skilled in the art and as previously discussed,
of noise sounds attenuated by the ANR provided can be
the feedforward-based ANR and pass-through audio funcreduced In making determinations of whether or not such
tions are less sensitive to latencies than the feedback-based
reductions in data transfer rates are possible, the processing
ANR function. Further, the feedforward-based ANR and
pass-through audio functions are more easily implemented 40 device 510 may be caused to evaluate the effects of such
reductions in data transfer rates on quality of sound through
with sufficiently high quality of sound with lower data samone or more of the pathways 200, 300 and 400, and/or the
pling rates than the feedback-basedANR function. Therefore,
quality of feedback-based and/or feed-forward based ANR
in other implementations, portions of the pathways 300 and/
provided.
or 400 may be operated at slower data transfer rates than the
FIG. 4b depicts a possible signal processing topology
pathway 200. Preferably, the data transfer rates of each of the 45
2500b for which the ANR circuit 2000 may be structured
pathways 200, 300 and 400 are selected such that the pathway
and/or progrmed. Where the ANR circuit 2000 adopts the
200 operates with a data transfer rate that is an integer mulsignal processing topology 2500b, the ANR circuit 2000
tiple of the data transfer rates selected for the portions of the
incorporates at least the DAC 910, the audio amplifier 960,
pathways 300 and/or 400 that are operated at slower data
50 theADC210,apairofsummingnodes230and270,andapair
transfer rates.
of filter blocks 250 and 450. The ANR circuit 2000 may
By way of example in an implementation in which all three
further incorporate one or more of the ADC 410, the ADC
of the pathways 200, 300 and 400 are present, the pathway
310, a filter block 350 and a summing node 370.
200 is operated at a data transfer rate selected to provide
The ADC 210 receives and digitizes an analog signal from
sufficiently low latency to enable sufficiently high quality of
feedback-based ANR that the provision ofANR is not unduly 55 the feedback microphone 120 representing feedback reference sounds detected by the feedback microphone 120, and
compromised (e.g., by having anti-noise sounds out-of-phase
provides corresponding feedback reference data to the sumwith the noise sounds they are meant to attenuate, or instances
ming node 230. In some implementations, theADC 410 digi:
of negative noise reduction such that more noise is actually
tizes an analog signal representing pass-through audio
being generated than attenuated, etc.), and/or sufficiently
high quality of sound in the provision of at least the feedback 60 received from the audio source 9400, the communications
microphone 140 or another source and provides the digitized
anti-noise sounds. Meanwhile, the portionofthepathway 300
result to the filter block 450. In other implementations, the
from the ADC 310 to the summing node 270 and the portion
audio source 9400, the communications microphone 140 or
of the pathway 400 from the ADC 410 to the summing node
another source provides digital data representing pass290 are both operated at lower data transfer rates (either the
same lower data transfer rates or different ones) that still also 65 through audio to the filter block 450 without need of analogto-digital conversion. One or more digital filters within the
enable sufficiently high quality offeedforward-basedANR in
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resenting the pass-through audio to derive a modified variant
of the pass-through audio data in which the pass-through
audio may be re-equalized and/or enhanced in other ways.
One or more digital filters within the filter block 450 also
function as a crossover that divides the modified pass-through
audio data into higher and lower frequency sounds, with data
representing the higher frequency sounds being output to the
summing node 270, and data representing the lower frequency sounds being output to the summing node 230. In
various implementations, the crossover frequency employed
in the filter block 450 is dynamically selectable during operation of the ANR circuit 2000, and may be selected to effectively disable the crossover function to cause data representing all frequencies of the modified pass-through audio to be
output to either of the summing nodes 230 or 270. In this way,
the point at which the modified pass-through audio data is
combined with data for the feedbackANR function within the
signal processing topology 2500a can be made selectable.
As just discussed, feedback reference data from the ADC
210 may be combined with data from the filter block 450 for
the pass-through audio function (either the lower frequency
sounds, or all of the modified pass-through audio) at the
summing node 230. The summing node 230 outputs the possibly combined data to the filter block 250. One or more
digital filters within the filter block 250 are employed to
modify the data from summing node 230 to derive modified
data representing at least feedback anti-noise sounds and
possibly further-modified pass-through audio sounds. The
filter block 250 provides the modified data to the summing
node 27 0. The summing node 270 combines the data from the
filter block 450 that possibly represents higher frequency
sounds of the modified pass-through audio with the modified
data from the filter block 250, and provides the result to the
DAC 910 to create an analog signal. The provision of data by
the filter block 450 to the summing node 270 may be through
the summing node 370 where the provision offeedforwardbased ANR is also supported.
Where the crossover frequency employed in the filter block
450 is dynamically selectable, various characteristics of the
filters making up the filter block 450 may also be dynamically
configurable. By way of example, the number and/or type of
digital filters making up the filter block 450 may be dynamically alterable, as well as the coefficients for each of those
digital filters. Such dynamic configurability may be deemed
desirable to correctly accommodate changes among having
no data from the filter block 450 being combined with feedback reference data from the ADC 210, having data from the
filter block 450 representing lower frequency sounds being
combined with feedback reference data from the ADC 210,
and having data representing all of the modified pass-through
audio from the filter block 450 being combined with feedback
reference data from theADC 210.
Where the provision of feedforward-based ANR is also
supported, the ADC 310 receives an analog signal from the
feedforward microphone 130, digitizes it, and provides feedforward reference data corresponding to the analog signal
output by the feedforward microphone 130 to the filter block
350. One or more digital filters within the filter block 350 are
employed to modify the feedforward reference data received
from the ADC 310 to derive feedforward anti-noise data
representing feedforward anti-noise sounds. The filter block
350 provides the feedforward anti-noise data to the summing
node 370 where the feedforward anti-noise data is possibly
combined with data that may be provided by the filter block
450 (either the higher frequency sounds, or all ofthe modified
pass-through audio).

The analog signal output by the DAC 910 is provided to the
audio amplifier 960 to be amplified sufficiently to drive the
acoustic driver 190 to acoustically output one or more of
feedback anti-noise sounds, feedforward anti-noise sounds
and pass-through audio.
As further depicted in FIG. 4b, the signal processing topology 2500b defines its own variations of the pathways 200, 300
and 400 along which digital data associated with feedbackbased ANR, feedforward-based ANR and pass-through
audio, respectively, flow. In a manner not unlike the pathway
200 of the signal processing topology 2500a, the flow of
feedback reference data and feedback anti-noise data among
theADC210, thesummingnodes230and270, the filter block
250 and the DAC 910 defines the feedback -based ANR pathway 200 of the signal processing topology 2500b. Where
feedforward-based ANR is supported, in a manner not unlike
the pathway 300 of the signal processing topology 2500a, the
flow of feedforward reference data and feedforward antinoise data among the ADC 310, the filter block 350, the
summing nodes 270 and 370, and the DAC 910 defines the
feedforward-based ANR pathway 300 of the signal processing topology 2500b. However, in a manner very much unlike
the pathway 400 of the signal processing topology 2500a, the
ability ofthe filter block 450 ofthe signal processing topology
2500b to split the modified pass-through audio data into
higher frequency and lower frequency sounds results in the
pathway 400 of the signal processing topology 2500b being
partially split. More specifically, the flow of digital data from
the ADC 410 to the filter block 450 is split at the filter block
450. One split portion of the pathway 400 continues to the
summing node 230, where it is combined with the pathway
200, before continuing through the filter block 250 and the
summing node 270, and ending at the DAC 910. The other
split portion of the pathway 400 continues to the summing
node 370 (if present), where it is combined with the pathway
300 (if present), before continuing through the summing node
270 and ending at the DAC 910.
Also notunlikethepathways 200,300 and400 ofthe signal
processing topology 2500a, the pathways 200, 300 and 400 of
the signal processing topology 2500b may be operated with
different data transfer rates. However, differences in data
transfer rates between the pathway 400 and both of the pathways 200 and 300 would have to be addressed. Sample-andhold, buffering or other functionality may be incorporated
into each of the summing nodes 230, 270 and/or 370. Alternatively and/or additionally, the filter block 350 may incorporate interpolation or other up sampling capability in providing digital data to the summing node 370, and/or the filter
block 450 may incorporate a similar capability in providing
digital data to each of the summing nodes 230 and 370 (or
270, if the pathway 300 is not present).
FIG. 4c depicts another possible signal processing topology 2500c for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500c, the ANR circuit 2000
incorporates at least the DAC 910, the audio amplifier 960,
theADC210, thesummingnode230, thefilterblocks250and
450, the VGA 280, another summing node 290, and the com- ·
pressor 950. The ANR circuit 2000 may further incorporate
one or more of the ADC 410, theADC 310, the filter block
350, the summing node 270, and the ADC 955. The signal
processing topologies 2500b and 2500c are similar in numerous ways. However, a substantial difference between the signal processing topologies 2500b and 2500c is the addition of
the compressor 950 in the signal processing topology 2500c
to enable the amplitudes of the sounds represented by data
output by both of the filter blocks 250 and 350 to be reduced

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in response to the compressor 950 detecting actual instances
or indications of impending instances of clipping and/or other
undesirable audio artifacts.
The filter block 250 provides its modified data to the VGA
280 where the amplitude ofthe sounds represented by the data
provided to the VGA 280 may be altered under the control of
the compression controller 950. The VGA 280 outputs its data
(with or without amplitude alteration) to the summing node
290, where it may be combined with data that may be output
by the filter block 450 (perhaps the higher frequency sounds
ofthe modified pass-through audio, or perhaps the entirety of
the modified pass-through audio). In turn, the summing node
290 provides its output data to the DAC 910. Where the
provision of feedforward-based ANR is also supported, the
data output by the filter block 250 to the VGA 280 is routed
through the summing node 270, where it is combined with the
data output by the filter block 350 representing feedforward
anti-noise sounds, and this combined data is provided to the
VGA280.
FIG. 4d depicts another possible signal processing topology 2500d for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500d, the ANR circuit 2000
incorporates at least the DAC 910, the compression controller
950, the audio amplifier 960, the ADC 210, the summing
nodes 230 and 290, the filter blocks 250 and 450, the VGA
280, and still other VGAs 445, 455 and 460. The ANR circuit
2000 may further incorporate one or more of the ADCs 310
and/or 410, the filter block 350, the summing node 270, the
ADC 955, and still another VGA 360. The signal processing
topologies 2500c and 2500d are similar in numerous ways.
However, a substantial difference between the signal processing topologies 2500c and 2500d is the addition of the ability
to direct the provision of the higher frequency sounds of the
modified pass-through audio to be combined with other audio
at either or both of two different locations within the signal
processing topology 2500d.
One or more digital filters within the filter block 450 are
employed to modify the digital data representing the passthrough audio to derive a modified variant of the pass-through
audio data and to function as a crossover that divides the
modified pass-through audio data into higher and lower frequency sounds. Data representing the lower frequency
sounds are output to the summing node 230 through the VGA
445. Data representing the higher frequency sounds are output both to the summing node 230 through the VGA 455 and
to the DAC 910 through the VGA 460. The VGAs 445, 455
and 460 are operable both to control the amplitudes of the
lower frequency and higher frequency sounds represented by
the data output by the filter block 450, and to selectively direct
the flow ofthe data representing the higher frequency sounds.
However, as has been previously discussed, the crossover
functionality of the filter block 450 may be employed to
selectively route the entirety of the modified pass-through
audio to one or the other of the summing node 230 and the
DAC910.
Where the provision of feedforward-based ANR is also
supported, the possible provision of higher frequency sounds
(or perhaps the entirety of the modified pass-through audio)
by the filter block 450 through the VGA 460 and to the DAC
910 may be through the summing node 290. The filter block
350 provides the feedforwardanti-noise data to the summing
node 270 through the VGA 360.
FIG. 4e depicts another possible signal processing topology 2500e for which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500e, the ANR circuit 2000

incorporates at least the DAC 910; the audio amplifier 960;
theADCs 210 and310; the summing nodes 230, 270 and 370;
the filter blocks 250, 350 and 450; the compressor 950; and a
pairofVGAs 240 and 340. TheANR circuit 2000 may further
incorporate one or both of the ADCs 410 and 955. The signal
processing topologies 2500b, 2500c and 2500e are similar in
numerous ways. The manner in which the data output by each
of the filter blocks 250, 350 and 450 are combined in the
signal processing topology 2500e is substantially similar to
that of the signal processing topology 2500b. Also, like the
signal processing topology 2500c, the signal processing
topology 2500e incorporates the compression controller 950.
However, a substantial difference between the signal processing topologies 2500c and 2500e is the replacement of the
single VGA 280 in the signal processing topology 2500c for
the separately controllable VGAs 240 and 340 in the signal
processing topology 2500e.
The summing node 230 provides data representing feedback reference sounds possibly combined with data that may
be output by the filter block 450 (perhaps the lower frequency
sounds of the modified pass-through audio, or perhaps the
entirety of the modified pass-through audio) to the filter block
250 through the VGA 240, and the ADC 310 provides data
representing feedforward reference sounds to the filter block
350 through the VGA 340. The data output by the filter block
350 is combined with data that may be output by the filter
block 450 (perhaps the higher frequency sounds of the modified pass-through audio, or perhaps the entirety of the modified pass-through audio) at the summing node 370. In turn, the
summing node 3 70 provides its data to the summing node 270
to be combined with data output by the filter block 250. The
summing node 270, in turn, provides its combined data to the
DAC910.
The compression controller 950 controls the gains of the
VGAs 240 and 340, to enable the amplitude of the sounds
represented by data output by the summing node 230 and the
ADC 310, respectively, to be reduced in response to actual
instances or indications of upcoming instances of clipping
and/or other undesirable audio artifacts being detected by the
compression controller 950. The gains of the VGAs 240 and
340 may be controlled in a coordinated manner, or may be
controlled entirely independently of each other.
FIG. 4f depicts another possible signal processing topology 2500jfor which the ANR circuit 2000 may be structured
and/or programmed. Where the ANR circuit 2000 adopts the
signal processing topology 2500f, the ANR circuit 2000
incorporates at least the DAC 910; the audio amplifier 960;
theADCs 210 and310; the summing nodes 230,270 and370;
the filter blocks 250, 350 and 450; the compressor 950; and
the VGAs 125 and 135. The ANR circuit 2000 may further
incorporate one or both of the ADCs 410 and 955. The signal
processing topologies 2500e and 2500fare similar in numerous ways. However, a substantial difference between the signal processing topologies 2500e and 2500fis the replacement
of the pair of VGAs 240 and 340 in the signal processing
topology 2500e for the VGAs 125 and 135 in the signal
processing topology 2500f
The VGAs 125 and 135 positioned at the analog inputs to
theADCs 210 and310, respectively, are analog VGAs, unlike
the VGAs 240 and 340 of the signal processing topology
2500e. This enables the compression controller 950 to
respond to actual occurrences and/or indications of soon-tooccur instances of clipping and/or other audio artifacts in
driving the acoustic driver 190 by reducing the amplitude of
one or both of the analog signals representing feedback and
feedforward reference sounds. Tbis may be deemed desirable
where it is possible for the analog signals provided to the

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ADCs 210 and 310 to be at too great an amplitude such that
signal. This provision ofthis combined data by the VGA 280
may be through the summing node 290 where the provision of
clipping at the point of driving the acoustic driver 190 might
be more readily caused to occur. The provision of the ability
pass-through audio is also supported.
Where the provision of pass-through audio is supported,
to reduce the amplitude of these analog signals (and perhaps
also including the analog signal provided to the ADC 410 via 5 the audio source 9400 may provide an analog signal reprethe VGA 145 depicted elsewhere) may be deemed desirable
senting pass-through audio to be acoustically output to a user,
and the ADC 410 digitizes the analog signal and provides
to enable balancing of amplitudes between these analog sigpass-throughaudiodatacorrespondingtotheanalogsignalto
nals, and/or to limit the numeric values of the digital data
the filter block 450. Alternatively, where the audio source
produced by one or more of the ADCs 210, 310 and 410 to
lesser magnitudes to reduce storage and/or transmission 10 9400 provides digital data representing pass-through audio,
bandwidth requirements.
such digital data may be provided directly to the filter block
FIG. 4g depicts another possible signal processing topology 2500g for which the ANR circuit 2000 may be pro450.0neormoredigitalfilterswithinthefilterblock450may
be employed to modifY the digital data representing the passgrammed or otherwise structured. Where the ANR circuit
2000 adopts the signal processing topology 2500g, the ANR 15 through audio to derive a modified variant of the pass-through
circuit 2000 incorporates at least the compression controller
audio data that may be re-equalized and/or enhanced in other
950, theDAC910, theaudioamplifier960, theADCs210and
ways. The filter block 450 provides the modified pass310, a pair ofVGAs 220 and320, the summing nodes 230 and
through audio data to the VGA460, and either with or without
270, the filter blocks 250 and 350, another pair ofVGAs 355
altering the amplitude of the pass-through audio sounds repand360, and the VGA280. TheANRcircuit2000mayfurther 20 resented by the modified pass-through audio data, the VGA
460 provides the modified pass-through audio data to the
incorporate one or more of the ADC 410, the filter block 450,
DAC 910 through the summing node 290.
still another VGA 460, the summing node 290, and the ADC
955.
The compression controller 950 controls the gain of the
The ADC 210 receives an analog signal from the feedback
VGA 280 to enable the amplitude of whatever combined form
microphone 120 and digitizes it, before providing corre- 25 of feedback and feedforward anti-noise sounds are received
sponding feedback reference data to the VGA 220. The VGA
by the VGA 280 to be reduced under the control of the
220 outputs the feedback reference data, possibly after modicompression controller 950 in response to actual occurrences
:tying its amplitude, to the summing node 230. Similarly, the
and/or indications of impending instances of clipping and/or
ADC 310 receives an analog signal from the feedforward
other audio artifacts.
FIGS. 5a through 5e depict some possible filter block
microphone 130 and digitizes it, before providing corre- 30
topologies that may be employed in creating one or more
sponding feedforward reference data to the VGA 320. The
VGA 320 outputs the feedforward reference data, possibly
blocks of filters (such as filter blocks 250,350 and450) within
signal processing topologies adopted by the ANR circuit
after modifYing its amplitude, to the filter block 350. One or
more digital filters within the filter block 350 are employed to
2000 (such as the signal processing topologies 2500a-g). It
modifY the feedforward reference data to derive feedforward 35 should be noted that the designation of a multitude of digital
anti-noise data representing feedforward anti-noise sounds,
filters as a "filter block" is an arbitrary construct meant to
simplifY the earlier presentation of signal processing topoloand the filter block 350 provides the feedforward anti-noise
data to both of the VGAs 355 and 360. In various implemengies. In truth, the selection and positioning of one or more
tations, the gains of the VGAs 355 and 360 are dynamically
digital filters at any point along any of the pathways (such as
selectable and can be operated in a coordinated manner like a 40 the pathways 200, 300 and 400) of any signal processing
three-way switch to enable the feedforward anti-noise data to
topology may be accomplished in a manner identical to the
be selectively provided to either of the summing nodes 230
selection and positioning of VGAs and summing nodes.
and 270. Thus, where the feedforward anti-noise data is comTherefore, it is entirely possible for various digital filters to be
bined with data related to feedback ANR within the signal
positioned along a pathway for the movement of data in a
processing topology 2500g is made selectable.
45 manner in which those digital filters are interspersed among
Therefore, depending on the gains selected for the VGAs
VGAs and/or summing nodes such that no distinguishable
355 and 360, the feedforward anti-noise data from the filter
block of filters is created. Or, as will be illustrated, it is
block 350 may be combined with the feedback reference data
entirely possible for a filter block to incorporate a summing
from the ADC 210 at the summing node 230, or may be
node or other component as part ofthe manner in which the
combined with feedback anti-noise data derived by the filter 50 filters of a filter block are coupled as part of the filter block
topology of a filter block.
block 250 from the feedback reference data at the summing
However, as previously discussed, multiple lower-order
node 270. Ifthe feedforward anti-noise data is combined with
the feedback reference data at the summing node 23 0, then
digital filters may be combined in various ways to perform the
the filter block 250 derives data representing a combination of
equivalent function of one or more higher-order digital filters.
feedbackanti-noisesoundsandfurther-modifiedfeedforward 55 Thus, although the creation of distinct filter blocks is not
anti-noise sounds, and this data is provided to the VGA 280
necessary in defining a pathway having multiple digital tilthrough the summing node 270 at which no combining ofdata
ters, it can be desirable in numerous situations. Further, the
creation of a block of filters at a single point along a pathway
occurs. Alternatively, if the feedforward anti-noise data is
combined with the feedback anti-noise data at the summing
can more easily enable alterations in the characteristics of
node 270, then the feedback anti-noise data will have been 60 filtering performed in that pathway. By way of example,
derived by the filter block 250 from the feedback reference
multiple lower-order digital filters connected with no other
data received through the summing node 230 at which no
components interposed between them can be dynamically
configured to cooperate to perform any of a variety of highercombining of data occurs, and the data resulting from the
combining at the summing node 270 is provided to the VGA
order filter functions by simply changing their coefficients
280. With or without an alteration in amplitude, the VGA 280 65 and/or changing the manner in which they are interconnected.
Also, in some implementations, such close interconnection of
provides whichever form of combined data is received from
the summing node 270 to the DAC .910 to create an analog
digital filters may ease the task of dynamically configuring a

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30

pathway to add or remove digital filters with a minimum of
changes to the interconnections that define that pathway.
It should be noted that the selections of types of filters,
quantities of filters, interconnections of filters and filter block
topologies depicted in each of FIGS. Sa through Se are meant
to serve as examples to facilitate understanding, and should
not be taken as limiting the scope of what is described or the
scope of what is claimed herein.
FIG. Sa depicts a possible filter block topology 3SOOa for
which the ANR circuit 2000 may be structured and/or programmed to define a filter block, such as one of the filter
blocks 2SO, 3SO and 4SO. The filter block topology 3SOOa is
made up of a serial chain of digital filters with a downsampling filter 6S2 at its input; biquad filters 6S4, 6SS and 656;
and a FIR filter 6S8 at its output.
As more explicitly depicted in FIG. Sa, in some implementations, the ANR circuit 2000 employs the internal architecture 2200a such that the ANR circuit 2000 incorporates the
filter bank SSO incorporating multitudes of the downsampling
filters SS2, the biquad filters SS4, and the FIR filters SS8. One
or more of each of the downsampling filters SS2, biquad filters
SS4 and FIR filters SS8 may be interconnected in any of a
number of ways via the switch array S40, including in a way
that defines the filter block topology 3SOOa. More specifically, the downsampling filter 6S2 is one ofthe downsampling
filters SS2; the biquad filters 6S4, 6SS and 6S6 are each one of
the biquad filters SS4; and the FIR filter 6S8 is one of the FIR
filters SS8.
Alternatively, and as also more explicitly depicted in FIG.
Sa, in other implementations, the ANR circuit 2000 employs
the internal architecture 2200b such that the ANR circuit
2000 incorporates a storage S20 in which is stored the downsampling filter routine SS3, the biquad filter routine SSS and
the FIR filter routine SS9. Varying quantities of downsampling, biquad and/or FIR filters may be instantiated within
available storage locations of the storage S20 with any of a
variety of interconnections defined between them, including
quantities of filters and interconnections that define the filter
block topology 3SOOa. More specifically, the downsampling
filter 6S2 is an instance of the downsampling filter routine
SS3; the biquad filters 6S4, 6SS and 6S6 are each instances of
the biquad filter routine SSS; and the FIR filter 6S8 is an
instance of the FIR filter routine SS9.
As previously discussed, power conservation and/or other
benefits may be realized by employing different data transfer
rates along different pathways of digital data representing
sounds in a signal processing topology. In support of converting between different data transfer rates, including where one
pathway operating at one data transfer rate is coupled to
another pathway operating at another data transfer rate, different data transfer clocks may be provided to different ones
of the digital filters within a filter block, and/or one or more
digital filters within a filter block may be provided with multiple data transfer clocks.
By way of example, FIG. Sa depicts a possible combination of different data transfer rates that may be employed
within the filter block topology 3SOOa to support digital data
being received at one data transfer rate, digital data being
transferred among these digital filters at another data transfer
rate, and digital data being output at still another data transfer
rate. More specifically, the downsampling filter 6S2 receives
digital data representing a sound at a data transfer rate 672,
and at least downsamples that digital data to a lower data
transfer rate 67S. The lower data transfer rate 67S is employed
in transferring digital data among the downsampling filter
6S2, the biquad filters 6S4-6S6, and the FIR filter 6S8. The
FIR filter 6S8 at least upsamples the digital data that it

receives from the lower data transfer rate 67S to a higher data
transfer rate 6.78 as that digital data is output by the filter block
to which the digital filters in the filter block topology 3SOOa
belong. Many other possible examples of the use of more than
one data transfer rate within a filter block and the possible
corresponding need to employ multiple data transfer clocks
within a filter block will be clear to those skilled in the art.
FIG. Sb depicts a possible filter block topology 3SOOb that
is substantially similar to the filter block topology 3SOOa, but
in which the FIR filter 6S8 of the filter block topology 3SOOa
has been replaced with an interpolating filter 6S7. Where the
internal architecture 2200a is employed, such a change from
the filter block topology 3SOOa to the filter block topology
3SOOb entails at least altering the configuration of the switch
array S40 to exchange one of the FIR filters SS8 with one of
the interpolating filters SS6. Where the internal architecture
2200b is employed, such a change entails at least replacing
the instantiation of the FIR filter routine SS9 that provides the
FIR filter 6S8 with an instantiation of the interpolating filter
routine SS7 to provide the interpolating filter 6S7
FIG. Sc depicts a possible filter block topology 3SOOc that
is made up of the same digital filters as the filter block topology 3SOOb, but in which the interconnections between these
digital filters have been reconfigured into a branching topology to provide two outputs, whereas the filter block topology
3SOOb had only one. Where the internal architecture 2200a is
employed, such a change from the filter block topology 3SOOb
to the filter block topology 3SOOc entails at least altering the
configuration of the switch array S40 to disconnect the input
to the biquad filter 6S6 from the output of the biquad filter
6SS, and to connect that input to the output of the downsampling filter 6S2, instead. Where the internal architecture
2200b is employed, such a change entails at least altering the
instantiation of biquad filter routine SSS that provides the
biquad filter 6S6 to receive its input from the instantiation of
the downsampling filter routine SS3 that provides the downsampling filter 6S2. The filter block topology 3SOOc may be
employed where it is desired that a filter block be capable of
providing two different outputs in which data representing
audio provided at the input is altered in different ways to
create two different modified versions of that data, such as in
the case of the filter block 4SO in each of the signal processing
topologies 2SOOb:f.
FIG. Sd depicts another possible filter block topology
3SOOd that is substantially similar to the filter block topology
3SOOa, but in which the biquad filters 6SS and 6S6 have been
removed to shorten the chain of digital filters from the quantity of five in the filter block topology 3SOOa to a quantity of
three.
FIG. Se depicts another possible filter block topology
3SOOe that is made up of the same digital filters as the filter
block topology 3SOOb, but in which the interconnections
between these digital filters have been reconfigured to put the
biquad filters 6S4, 6SS and 6S6 in a parallel configuration,
whereas these same filters were in a serial chain configuration
in the filter block topology 3SOOb. As depicted, the output of
the downsampling filter 6S2 is coupled to the inputs of all
three of the biquadfilters 6S4, 6SS and 656, and the outputs of
all three of these biquad filters are coupled to the input of the
interpolating filter 6S7 through an additionally incorporated
sUlllming node 6S9.
Taken together, the FIGS. Sa through Se depict the manner
in which a given filter block topology of a filter block is
dynamically configurable to so as to allow the types of filters,
quantities of filters and/or interconnections of digital filters to
be altered during the operation of a filter block. However, as
those skilled in the art will readily recognize, such changes in

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types, quantities and interconnections of digital filters are
likely to require corresponding changes in filter coefficients
and/or other settings to be made to achieve the higher-order
filter function sought to be achieved with such changes. As
wiii be discussed in greater detail, to avoid or at least mitigate 5
the creation of audible distortions or other undesired audio
artifacts arising from making such changes during the operation of the personal ANR device, such changes in interconnections, quantities of components (including digital filters),
types of components, filter coefficients and/or VGA gain 10
values are ideally buffered so as to enable their being made in
a manner coordinated in time with one or more data transfer
rates.
The dynamic configurability of both of the internal architectures 2200a and 2200b, as exemplified throughout the 15
preceding discussion of dynamically configurable signal processing topologies and dynamically configurable filter block
topologies, enables numerous approaches to conserving
power and to reducing audible artifacts caused by the introduction of microphone self noise, quantization errors and 20
other influences arising from components employed in the
personal ANR device 1000. Indeed, there can be a synergy
between achieving both goals, since at least some measures
taken to reduce audible artifacts generated by the components
ofthe personal ANR device 1000 can also result in reductions 25
in power consumption. Reductions in power consumption
can be of considerable importance given that the personal
ANR device 1000 is preferably powered from a battery or
other portable source of electric power that is likely to be
somewhat limited in ability to provide electric power.
30
In either of the internal architectures 2200a and 2200b, the
processing device 510 may be caused by execution of a
sequence of instructions of the ANR routine 525 to monitor
the availability of power from the power source 180. Alternatively and/or additionally, the processing device 510 may 35
be caused to monitor characteristics of one or more sounds
(e.g., feedback reference and/or anti-noise sounds, feedforward reference and/or anti-noise sounds, and/or pass-through
audio sounds) and alter the degree of ANR provided in
response to the characteristics observed. As those :familiar 40
with ANR will readily recognize, it is often the case that
providing an increased degree of ANR often requires the
implementation of a more complex transfer function, which
often requires a greater number of filters and/or more complex types of filters to implement, and this in turn, often leads 45
to greater power consumption. Analogously, a lesser degree
ofANR often requires the implementation of a simpler transfer function, which often requires fewer and/or simpler filters,
which in turn, often leads to less power consumption.
Further, there can arise situations, such as an environment so
with relatively low environmental noise levels or with environmental noise sounds occurring within a relatively narrow
range of frequencies, where the provision of a greater degree
of ANR can actually result in the components used in providing the ANR generating noise sounds greater than the attenu- 55
ated environmental noise sounds. Still further, and as will be
familiar to those skilled in the art of feedback-based ANR,
under some circumstances, providing a considerable degree
offeedback-basedANR can lead to instability as undesirable
60
audible feedback noises are produced.
In response to either an indication of diminishing availability of electric power or an indication that a lesser degree of
ANR is needed (or is possibly more desirable), the processing
device 510 may disable one or more functions (including one
or both of feedback-based and feedforward-based ANR), 65
lower data transfer rates of one or more pathways, disable
branches within pathways, lower data transfer rates between

32
digital filters within a filter block, replace digital filters that
consume more power with digital filters that consume less
power, reduce the complexity of a transfer function employed
in providingANR, reduce the overall quantity of digital filters
within a filter block, and/or reduce the gain to which one or
more sounds are subjected by reducing VGA gain settings
and/or altering filter coefficients. However, in taking one or
more of these or other similar actions, the processing device
510 may be further caused by theANR routine 525 to estimate
a degree of reduction in the provision of ANR that balances
one or both of the goals of reducing power consumption and
avoiding the provision of too great a degree ofANR with one
or both of the goals of maintaining a predetermined desired
degree of quality of sound and quality of ANR provided to a
user of the personal ANR device 1000. A minimum data
transfer rate, a maximum signal-to-noise ratio or other measure may be used as the predetermined degree of quality or
ANR and/or sound.
As an example, and referring back to the signal processing
topology 2500a of FIG. 4a in which the pathways 200, 300
and 400 are explicitly depicted, a reduction in the degree of
ANR provided and/or in the consumption of power may be
realized through turning off one or more of the feedbackbasedANR, feedforward-basedANR and pass-through audio
functions. Tbis would result in at least some of the components along one or more of the pathways 200, 300 and 400
either being operated to enter a low power state in which
operations involving digital data would cease within those
components, or being substantially disconnected from the
power source 180. A reduction in power consumption and/or
degree of ANR provided may also be realized through lowering the data transfer rate(s) of at least portions of one or
more of the pathways 200, 300 and 400, as previously discussed in relation to FIG. 4a.
As another example, and referring back to the signal processing topology 2500b of FIG. 4b in which the pathways
200, 300 and 400 are also explicitly depicted, a reduction in
power consumption and/or in the complexity oftransferfunctions employed may be realized through turning off the flow
of data through one of the branches ofthe split in the pathway
400. More specifically, and as previously discussed in relation
to FIG. 4b, the crossover frequency employed by the digital
filters within the filter block 450 to separate the modified
pass-through audio into higher frequency and lower frequency sounds may be selected to cause the entirety of the
modified pass-through audio to be directed towards only one
of the branches of the pathway 400. Tbis would result in
discontinuing of the transfer of modified pass-through audio
data through one or the other of the summing nodes 230 and
370, thereby enabling a reduction in power consumption and/
or in the introduction of noise sounds from components by
allowing the combining function of one or the other ofthese
summing nodes to be disabled or at least to not be utilized.
Similarly, and referring back to the signal processing topology 2500d of FIG. 4d (despite the lack of explicit marking of
its pathways), either the crossover frequency employed by the
filter block 450 or the gain settings of the VGAs 445, 455 and
460 may be selected to direct the entirety of the modified
pass-through audio data down a single one of the three possible pathway branches into which each of these VGAs lead.
Thus, a reduction in power consumption and/or in the introduction of noise sounds would be enabled by allowing the
combining function of one or the other of the summing nodes
230 and 290 to be disabled or at least not be utilized. Still
further, one or more of the VGAs 445, 455 and 460 through
which modified pass-through audio data is not being transferred may be disabled.

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As still another example, and referring back to the filter
block topology 3500a of FIG. Sa in which the allocation of
three data transfer rates 672, 675 and 678 are explicitly
depicted, a reduction in the degree ofANR provided and/or in
power consumption may be realized through lowering one or 5
more of these data transfer rates. More specifically, within a
filter block adopting the filter block topology 3500a, the data
transfer rate 675 at which digital data is transferred among the
digital filters 652, 654-656 and 658 may be reduced. Such a
change in a data transfer rate may also be accompanied by 10
exchanging one or more of the digital filters for variations of
the same type of digital filter that are better optimized for
lower bandwidth calculations. As will be familiar to those
skilled in the art of digital signal processing, the level of
calculation precision required to maintain a desired predeter- 15
mined degree of quality of sound and/or quality of ANR in
digital processing changes as sampling rate changes. Therefore, as the data transfer rate 675 is reduced, one or more of
the biquad filters 654-656 which may have been optimized to
maintain a desired degree of quality of sound and/or desired 20
degree of quality ofANR at the original data transfer rate may
be replaced with other variants of biquad filter that are optimized to maintain substantially the same quality of sound
and/or ANR at the new lower data transfer rate with a reduced
level of calculation precision that also reduces power con- 25
sumption. This may entail the provision of different variants
of one or more of the different types of digital filter that
employ coefficient values of differing bit widths and/or incorporate differing quantities of taps.
As still other examples, and referring back to the filter 30
block topologies 3500c and 3500d of FIGS. Sc and Sd,
respectively, as well as to the filter block topology 3500a, a
reduction in the degree of ANR provided and/or in power
consumption may be realized through reducing the overall
quantity of digital filters employed in a filter block. More 35
specifically, the overall quantity of five digital filters in the
serial chain of the filter block topology 3500a may be reduced
to the overall quantity of three digital filters in the shorter
serial chain of the filter block topology 3500d. As those
skilled in the art would readily recognize, such a change in the 40
overall quantity of digital filters would likely need to be
accompanied by a change in the coefficients provided to the
one or more of the digital filters that remain, since it is likely
that the transfer function(s) performed by the original five
digital filters would have to be altered or replaced by transfer 45
function( s) that are able to be performed with the three digital
filters that remain. Also more specifically, the overall quantity
of five digital filters in the branching topology of the filter
block topology 3500c may be reduced to an overall quantity
of three digital filters by removing or otherwise deactivating 50
the filters of one ofthe branches (e.g., the biquad filter 656 and
the interpolating filter 657 of one branch that provides one of
the two outputs). This may be done in concert with selecting
a crossover frequency for a filter block providing a crossover
function to effectively direct all frequencies of a sound rep- 55
resented by digital data to only one of the two outputs, and/or
in concert with operating one or more VGAs external to a
filter block to remove or otherwise cease the transfer of digital
data through a branch of a signal processing topology.
Reductions in data transfer rates may be carried out in 60
various ways in either of the internal architectures 2200a and
2200b. By way of example in the internal architecture 2200a,
various ones of the data transfer clocks provided by the clock '
bank 570 may be directed through the switch array 540 to
differing ones ofthe digital filters, VGAs and summing nodes 65
of a signal processing topology and/or filter block topology to
enable the use of multiple data transfer rates and/or conver-

34
sions between different data transfer rates by one or more of
those components. By way of example in the internal architecture 2200b, the processing device 510 may be caused to
execute the sequences of instructions of the various instantiations of digital filters, VGAs and summing nodes of a
signal processing topology and/or filter block topology at
intervals of differing lengths of time. Thus, the sequences of
instructions for one instantiation of a given component are
executed at more frequent intervals to support a higher data
transfer rate than the sequences of instructions for another
instantiation ofthe same component where a lower data transfer rate is supported.
As yet another example, and referring back to any of the
earlier-depicted signal processing topologies and/or filter
block topologies, a reduction in the degree ofANR provided
and/or in power consumption may be realized through the
reduction of the gain to which one or more sounds associated
with the provision of ANR (e.g., feedback reference and/or
anti-noise sounds, or feedforward reference and/or anti -noise
sounds). Where a VGA is incorporated into at least one of a
feedback -basedANR pathway and a feedforward-basedANR
pathway, the gain setting of that VGA may be reduced. Alternatively and/or additionally, and depending on the transfer
function implemented by a given digital filter, one or more
coefficients of that digital filter may be altered to reduce the
gain imparted to whatever sounds are represented by the
digital data output by that digital filter. As will be familiar to
those skilled in the art, reducing a gain in a pathway can
reduce the perceptibility of noise sounds generated by components. In a situation where there is relatively little in the
way of environmental noise sounds, noise sounds generated
by components can become more prevalent, and thus, reducing the noise sounds generated by the components can
become more important than generating anti-noise sounds to
attenuate what little in the way of environmental noise sounds
may be present. In some implementations, such reduction(s)
in gain in response to relatively low environmental noise
sound levels may enable the use of!ower cost microphones.
In some implementations, performing such a reduction in
gain at some point along a feedback-basedANR pathway may
prove more useful than along a feedforward-basedANR pathway, since environmental noise sounds tend to be more
attenuated by the PNR provided by the personal ANR device
before ever reaching the feedback microphone 120. As a
result of the feedback microphone 120 tending to be provided
with weaker variants of environmental noise sounds than the
feedforwardmicrophone130, thefeedback-basedANRfunction may be more easily susceptible to a situation in which
noise sounds introduced by components become more prevalent than environmental noise sounds at times when there is
relatively little in the way of environmental noise sounds. A
VGA may be incorporated into a feedback-basedANR pathway to perform this function by normally employing a gain
value of 1 which would then be reduced to Vz or to some other
preselected lower value in response to the processing device
510 and/or another processing device external to the ANR
circuit 2000 and to which the ANR circuit 2000 is coupled
determining that environmental noise levels are low enough
that noise sounds generated by components in the feedbackbased ANR pathway are likely to be significant enough that
such a gain reduction is more advantageous than the production of feedback anti-noise sounds.
The monitoring of characteristics of environmental noise
sounds as part of determining whether or not changes inANR
settings are to be made may entail any of a number of
approaches to measuring the strength, frequencies and/or
other characteristics of the environmental noise sounds. In

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some implementations, a simple sound pressure level (SPL)
or other signal energy measurement without weighting may
be taken of environmental noise sounds as detected by the
feedback microphone 120 and/or the feedforward microphone 130 within a preselected range of frequencies. Alter- 5
natively, the frequencies within the preselected range of frequencies of a SPL or other signal energy measurement may
subjected to the widely known and used ''A-weighted" frequency weighting curve developed to reflect the relative sensitivities of the average human ear to different audible fre- 10
quencies.
FIGS. 6a through 6c depict aspects and possible implementations of triple-buffering both to enable synchronized
ANR setting changes and to enable a failsafe response to an 15
occurrence and/or to indications of a likely upcoming occurrence of an out-of-bound condition, including and not limited
to, clipping and/or excessive amplitude of acoustically output
sounds, production of a sound within a specific range of
frequencies that is associated with a malfunction, instability 20
of at least feedback-basedANR, or other condition that may
generate undesired or uncomfortable acoustic output. Each of
these variations of triple-buffering incorporate at least a trio
ofbuffers 620a, 620b and 620c. In each depicted variation of
triple-buffering, two of the buffers 620a and 620b are alter- 25
nately employed during normal operation of the ANR circuit
2000 to synchronously update desired ANR settings "on the
fly," including and not limited to, topology interconnections,
data clock settings, data width settings, VGA gain settings,
and filter coefficient settings. Also, in each depicted variation 30
of triple-buffering, the third buffer 620c maintains a set of
ANR settings deemed to be "conservative" or "failsafe" setc
tings that may be resorted to bringtheANR circuit 2000 back
into stable operation and/or back to safe acoustic output levels
35
in response to an out-of-bound condition being detected.
As will be familiar to those skilled in the art of controlling
digital signal processing fur audio signals, it is often necessary to coordinate the updating of various audio processing
settings to occur during intervals between the processing of
pieces of audio data, and it is often necessary to cause the 40
updating of at least some of those settings to be made during
the same interval. Failing to do so can result in the incomplete
programming of filter coefficients, an incomplete or malformed definition of a transfer function, or other mismatched
configuration issue that can result in undesirable sounds 45
being created and ultimately acoustically output, including
and not limited to, sudden popping or booming noises that can
surprise or frighten a listener, sudden increases in volume that
are unpleasant and can be harmful to a listener, or howling
feedback sounds in the caseofupdating feedback-basedANR 50
settings that can also be harmful.
In some implementations, the buffers 620a-c of any of
FIGS. 6a-c are dedicated hardware-implemented registers,
the contents of which are able to be clocked into registers
within the VGAs, the digital filters, the summing nodes, the 55
clocks of the clock bank 570 (if present), switch array 540 (if
present), the DMA device 541 (if present) and/or other components. In other implementations, the buffers 620a-c of
FIGS. 6a-c are assigned locations within the storage 520, the
contents of which are able to be retrieved by the processing 60
device 510 and written by the processing device 510 into
other locations within the storage 520 associated with instantiations of the VGAs, digital filters, and summing nodes,
and/or written by the processing device 510 into registers
within the clocks of the clock bank 570 (ifpresent), the switch 65
array540 (ifpresent), theDMAdevice 541 (ifpresent) and/or
other components.

36
FIG. 6a depicts the triple-buffering of VGA settings,
including gain values, employing variants of the buffers
620a-c that each store differing ones ofVGA settings 626.An
example of a use of such triple-buffering ofVGA gain values
may be the compression controller 950 operating one or more
VGAs to reduce the amplitude of sounds represented by
digital data in response to detecting occurrences and/or indications of impending occurrences of clipping and/or other
audible artifacts in the acoustic output of the acoustic driver
190. In some implementations, the compression controller
950 stores new VGA settings into a selected one ofthe buffers
620a and 620b. At a subsequent time that is synchronized to
the flow of pieces of digital data through one or more of the
VGAs, the settings stored in the selected one of the buffers
620a and 620b are provided to those VGAs, thereby avoiding
the generation of audible artifacts. As those skilled in the art
will readily recognize, the compression controller 950 may
repeatedly update the gain settings ofVGAs over a period of
time to "ramp down" the amplitude of one or more sounds to
a desired level of amplitude, rather than to immediately
reduce the amplitude to that desired level. In such a situation,
the compression controller 950 would alternate between storing updated gain settings to the buffer 620a and storing
updated gain settings to the buffer 620b, thereby enabling the
decoupling ofthe times at which each ofthe buffers 620a and
620b are each written to by the compression controller 950
and the times at which each of the buffers provide their stored
VGA settings to the VGAs. However, a set of more conservatively selected VGA settings is stored in the buffer 620c,
and these failsafe settings may be provided to the VGAs in
response to an out-of-bound condition being detected. Such
provision of the VGA settings stored in the buffer 620c overrides the provision of any VGA settings stored in either of the
buffers 620a and 620b.
FIG. 6b depicts the triple-buffering of filter settings,
including filter coefficients, employing variants ofthe buffers
620a-c that each store differing ones of filter settings 625. An
example of a use of such triple-buffering of filter coefficients
maybe adjusting the range offrequencies and/orthedegree of
attenuation of noise sounds that are reduced in the feedbackbased ANR provided by the personal ANR device 1000. In
some implementations, processing device 510 is caused by
the ANR routine 525 to store new filter coefficients into a
selected one of the buffers 620a and 620b. At a subsequent
time that is synchronized to the flow of pieces of digital data
through one or more ofthe digital filters, the settings stored in
the selected one of the buffers 620a and 620b are provided to
those digital filters, thereby avoiding the generation of
·audible artifacts. Another example of a use of such triplebuffering of filter coefficients may be adjusting the crossover
frequency employed by the digital filters within the filter
block 450 in some of the above signal processing topologies
to divide the sounds of the modified pass-through audio into
lower and higher frequency sounds. At a time synchronized to
at least the flow of pieces of digital data associated with
pass-through audio through the digital filters of the filter
block 450, filter settings stored in one or the other of the .
buffers 620a and 620b are provided to at least some of the
digital filters.
FIG. 6c depicts the triple-buffering of either all or a selectable subset of clock, VGA, filter and topology settings,
employing variants of the buffers 620a-c that each store differing ones of topology settings 622, filter settings 625, VGA
settings 626 and clock settings 627. An example of a use of
triple-buffering of all of these settings may be changing from
one signal processing topology to another in response to a
user of the personal ANR device 1000 operating a control to

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37
activate a "talk-through" feature in which the ANR provided
by the personal ANR device 1000 is altered to enable the user
to more easily hear the voice of another person without having to remove the personal ANR device 1000 or completely
turnoff the ANR function. The processing device 510 may be
caused to store the settings required to specifY a new signal
processing topology in which voice sounds are more readily
able to pass to the acoustic driver 190 from the feedforward
microphone 130, and the various settings of the VGAs, digital
filters, data clocks and/or other components of the new signal
processing topology within one or the other of the buffers
620a and 620b. Then, at a time synchronized to the flow of at
least some pieces of digital data representing sounds through
at least one component (e.g., anADC, a VGA, a digital filter,
a summing node, or a DAC), the settings are used to create the
interconnections for the new signal processing topology (by
being provided to the switch array 540, if present) and are
provided to the components that are to be used in the new
signal processing topology.
However, some variants of the triple-buffering depicted in
FIG. 6c may further incorporate a mask 640 providing the
ability to determine which settings are actually updated as
either of the buffers 620a and 620b provide their stored contents to one or more components. In some embodiments, bit
locations within the mask are selectively set to either 1 or 0 to
selectively enable the contents of different ones of the settings
corresponding to each of the bit locations to be provided to
one or more components when the contents of one or the other
of the buffers 620a and 620b are to provide updated settings
to the components. The granularity of the mask 640 may be
such that each individual setting may be selectively enabled
for updating, or may be such that the entirety of each of the
topology settings 622, the filter settings 625, the VGA setting
626 and the clock setting 627 are able to be selected for
updating through the topology settings mask 642, the filter
settings mask 645, the VGA settings mask 646 and the clock
settings mask 647, respectively.
Other implementations are within the scope of the following claims and other claims to which the applicant may be
entitled.
The invention claimed is:
1. A method of operating a dynamically configurableANR
circuit to provide ANR in an earpiece of a personal ANR
device, the method comprising:
incorporating a firstADC of the ANR circuit, a first plurality of digital filters of a quantity specified by a first set of
ANR settings, and a DAC ofthe ANR circuit into a first
pathway;
incorporating a secondADC oftheANR circuit, a second
plurality of digital filters of a quantity specified by the
first set of ANR settings, and the DAC into a second
pathway;
selecting a type of digital filter specified by the first set of
ANR settings for each digital filter ofthe first and second
pluralities of digital filters from among a plurality of
types of digital filter supported by the ANR circuit;
adopting a signal processing topology specified by the first
set of ANR settings by configuring interconnections
among at least the first and second ADCs, the first and
second pluralities of digital filters and the DAC so that
digital data representing sounds flows through the first
pathway from the first ADC to the DAC through at least
the first plurality of digital filters; digital data representing sounds flows through the second pathway from the
second ADC to the DAC through at least the second
plurality of digital filters; and the first and second pathways are combined at a first location along the first

5

10

15

20

25

30

35

40

45

50

55

60

65

pathway and at a second location along the second pathway such that the digital data from both the first and
second pathways are combined before flowing to the
DAC;
configuring each digital filter of the first and second pluralities of digital filters with filter coefficients specified
by the first set of ANR settings;
setting a data transfer rate at which digital data flows
through at least a portion of at least one of the first and
second pathways as specified by the first ANR settings;
operating the first and second ADCs, the first and second
pluralities of digital filters and the DAC to provide ANR
in the earpiece; and
changing an ANR setting specified by the first set of ANR
settings to an ANR setting specified by a second set of
ANR settings in synchronization with a transfer of digital data along at least a portion of at least one ofthe first
and second pathways.
2. The method of claim 1, further comprising:
incorporating a third ADC of the ANR circuit, a third
plurality of digital filters of a quantity specified by a first
set of ANR settings, and the DAC into a third pathway;
selecting a type of digital filter specified by the first set of
ANR settings for each digital filter of the third plurality
of digital filters from among the plurality of types of
digital filter supported by the ANR circuit;
adopting a signal processing topology specified by the first
set of ANR settings further comprises configuring interconnections among a third ADC, the third plurality of
digital filters and the DAC so that digital data representing sounds flows through the third pathway from the
thirdADC to the DAC through at least the third plurality
of digital filters; and the third pathway is combined with
one of the first and second pathways at a third location
along the third pathway and at a fourth location along the
one of the first and second pathways such that the digital
data from the third pathway and the one of the first and
second pathways are combined before flowing to the
DAC;
configuring each digital filter ofthe third plurality of digital
filters with filter coefficients specified by the first set of
ANR settings; and
operating the third ADC and the third plurality of digital
filters, in conjunction with operating the first and second
ADCs, the first and second pluralities of digital filters
and the DAC to provide ANR in the earpiece.
3. The method of claim 1, further comprising:
monitoring an amount of power available from a power
source; and
wherein changing an ANR setting specified by the first set
of ANR settings to an ANR setting specified by the
second set ofANR settings occurs in response to a reduction in the amount of power available from the power
source, and comprises changing at least one of an interconnection of the signal processing topology defined by
the firstANR settings, a selection of a digital filter specified by the first ANR settings, a filter coefficient specified by the first ANR settings, and a data transfer rate
specified by the first ANR settings.
4. The method of claim 1, further comprising:
monitoring a characteristic of a sound represented by digital data; and
wherein changing anANR setting specified by the first set
of ANR settings to an ANR setting specified by the
second set of ANR settings occurs in response to a
change in the characteristic, and comprises changing at
least one of an interconnection of the signal processing

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topology defined by the firstANR settings, a selection of
a digital filter specified by the firstANR settings, a filter
coefficient specified by the firstANR settings, and a data
transfer rate specified by the first ANR settings.
5. The method of claim 4, wherein changing an ANR 5
setting specified by the first set of ANR settings to an ANR
setting specified by the second set of ANR settings reduces a
degree ofANR provided by the configurableANR circuit and
reduces consumption of power by the configurable ANR circuit from a power supply coupled to the configurable ANR 10
circuit.
6. The method of claim 5, further comprising selecting at
least one ANR setting of the second set of ANR settings to
maintain one of a desired quality of sound output by the
configurable ANR circuit and a desired quality of ANR pro- 15
vided by the configurable ANR circuit.
7. The method of claim 1, further comprising:
awaiting receipt of the second set ofANR settings from an
external processing device coupled to the ANR circuit;
20
and
wherein changing anANR setting specified by the first set
of ANR settings to an ANR setting specified by the
second set ofANR settings occurs in response to receiving the second set of ANR settings from the external
25
processing device.
8. The method of claim 1, wherein adopting a signal processing topology specified by the first set of ANR settings
further comprises:
configuring interconnections among the firstADC, the first
plurality of digital filters, the DAC and a VGA to locate 30
the VGA in the first pathway;
configuring the VGA with a gain setting specified by the
first set of ANR settings;
operating the VGA in conjunction with operating the first
and second ADCs, the first and second pluralities of 35
digital filters and the DAC to provide ANR in the earpiece; and
wherein changing an ANR setting specified by the first set
of ANR settings to an ANR setting specified by the
second set of ANR settings comprises configuring the 40
VGA with a gain setting specified by the second set of
ANR settings.
9. The method of claim 8, wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set of ANR settings occurs in 45
response to detecting an instance of clipping of at least feedbackANR anti-noise sounds.
10. The method of claim 1, wherein:
the first set ofANR settings specifies a third location along
the first pathway and a fourth location along the second 50
pathway at which the first and second pathways are
combined;
the first set of ANR settings specifies a split in the second
pathway that creates a first branch in the second pathway
that is combined with the first pathway at the first loca- 55
tion along the first pathway and the second location
along second pathway, and creates a second branch in
the second pathway that is combined with the first pathway at the third location along the first pathway and the
fourth location along the second pathway; and
60
adopting a signal processing topology specified by the first
set ofANR settings further comprises configuring interconnections among the first and second ADCs, the first
and second pluralities of filters and the DAC to create the
first and second branches of the second pathway.
65
11. The method of claim 10, wherein changing an ANR
setting specified by the first set of ANR settings to an ANR

40
setting specified by the second set ofANR settings comprises
changing at least one of the interconnections among the first
and secondADCs, the first and second pluralities of filters and
the DAC to change the second pathway to remove the second
branch, thereby adopting another signal processing topology
that lacks the split in the second pathway such that the first
and second pathways are combined only at the first location
along the first pathway and the second location along the
second pathway.
12. The method of claim 1, wherein setting the data transfer
rate at which digital data flows through at least a portion of the
first pathway comprises setting a first data transfer rate at
which digital data flows through the entirety of both the first
and second pathways.
13. The method of claim 12, wherein changing an ANR
setting specified by the first set of ANR settings to an ANR
setting specified by the second set ofANR settings comprises
changing the data transfer rate of a portion of the second
pathway to a second data transfer rate that is lower than the
first data transfer rate to reduce the rate at which digital data
flows through the portion of the second pathway relative to
the rate at which digital data flows through the first pathway.
14. An apparatus comprising an ANR circuit, the ANR
circuit comprising:
a firstADC;
a second ADC;
aDAC;
a processing device; and
a storage in which is stored a sequence of instructions that
when executed by the processing device, causes the
processing device to:
incorporate the first ADC, a first plurality of digital
filters of a quantity specified by a first set of ANR
settings, and the DAC into a first pathway;
incorporate the secondADC, a second plurality of digital filters of a quantity specified by the first set ofANR
settings, and the DAC into a second pathway;
select a type of digital filter specified by the first set of
ANR settings for each digital filter of the first and
second pluralities of digital filters from among a plurality of types of digital filter supported by the ANR
circuit;
adopt a signal processing topology specified by the first
set of ANR settings by configuring interconnections
among at least the first and secondADCs, the first and
second pluralities of digital filters and the DAC so that
digital data representing sounds flows through the
first pathway from the first ADC to the DAC through
at least the first plurality of digital filters; digital data
representing sounds flows through the second pathway from the secondADC to the DAC through at least
the second plurality of digital filters; and the first and
second pathways are combined at a first location
along the first pathway and at a second location along
the second pathway such that the digital data from
both the first and second pathways are combined
before flowing to the DAC;
configure each digital filter of the first and second pluralities of digital filters with filter coefficients specifled by the first set of ANR settings;
set a data transfer rate at which digital data flows through
at least a portion of at least one of the first and second
pathways as specified by the first ANR settings;
cause the first and second ADCs, the first and second
pluralities of digital filters and the DAC to be operated
to provide ANR in the earpiece; and

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42

change anANR setting specified by the first set ofANR
settings to anANR setting specified by a second set of
ANR settings in synchronization with a transfer of
digital data along at least a portion of at least one of
the first and second pathways.
15. The apparatus of claim 14, wherein:
a plurality of filter routines that defines a plurality of types
of digital filter is stored in the storage;
each filter routine of the plurality of filter routines comprises a sequence of instructions that when executed by
the processing device causes the processing device to
perform filter calculations of the type of dioital filter
and
"'"
'
the processing device is further caused to instantiate each
digital filter of the first and second pluralities of digital
filters based on filter routines of the plurality of filter
routines that defines the type of digital filter specified by
the first set of ANR settings.
1~. The apparatus of claim 15, wherein the processing
device directly transfers digital data among the first and secondADCs, each of the digital filters of the first and second
plm:'lities of digital filters instantiated by the processing
device, and the DAC.
17. The apparatus of claim 1S, wherein the processing
device operates a DMA device to transfer digital data among
at least a subset of the first and second ADCs each of the
?igital ~lters of the first and second pluralities or'digital filters
mstantlated by the processing device, and the DAC.
18. The apparatus of claim 14, wherein the ANR circuit
~er comprises an interface to enable an amount of power
avmlable from a power source coupled to the ANR circuit to
be monitored, and wherein the processing device is further
caused to:
monitor the amount of power available from the power
source;and
change an ANR setting specified by the first set of ANR
settings to an ANR setting specified by the second set of
ANR settings in response to a reduction in the amount of
power available from the power source, wherein the
change comprises a change of at least one of an interconnection ofthe. signal processing topology defined by
the firstANR settmgs, a selection of a digital filter specified by the firstANR settings, a filter coefficient specified by the first ANR settings, and a data transfer rate
specified by the first ANR settings.
19. The apparatus of claim 14, wherein the processing
device is further caused to:
monitor a characteristic of a sound represented by digital
data; and
change an ANR setting specified by the first set of ANR
settings to an ANR setting specified by the second set of
ANR settings in response to a change in the characteristic, wherein the change comprises a change of at least
one of an interconnection of the sigiial processing topol-

ogy defined by the first ANR settings, a selection of a
digital_filter specified by the first ANR settings, a filter
coefficrent specified by the firstANR settings, and a data
transfer rate specified by the first ANR settings.
20. Th: appara~s of claim 19, wherein the change of an
ANR setting specified by the first set of ANR settings to an
ANR setting specified by the second set of ANR settings
r:du~es a degree of ANR provided by the configurable ANR
ctrcuit and reduces consumption of power by the configurable
ANR circuit from a power supply coupled to the configurable
ANR circuit.
21. The apparatus of claim 20, wherein the processing
device is further caused to select at least one ANR setting of
the second set of ANR settings to maintain one of a desired
quality of sound output by the configurable ANR circuit and
a _des~ed quality of ANR provided by the configurable ANR

5

10

15

ClfCUlt.

20

25

30

35

40

4

5

50

22. The apparatus of claim 14, further comprising:
an external processing device external to the ANR circuit·
wherein the ANR circuit further comprises an interfac;
coupling the ANR circuit to the external processing
device; and
wherein the processing device of the ANR circuit is further
caused to:
await receipt of the second set of ANR settings from the
external processing device; and
change anANR setting specified by the first set ofANR
settings to an ANR setting specified by the second set
of ANR settings in response to the second set of ANR
settings being received from the external processing
device through the interface.
23. The apparatus of claim 14, wherein the processing
device is further caused to:
configure interconnections among the first ADC the first
plurality of digital filters, the DAC and a VGA;
configure the VGA with a gain setting specified by the first
set of ANR settings;
cause the VGA to be operated in conjunction with the first
~~ second ADCs, the first and second pluralities of
digital filters and the DAC to provide ANR in the earpiece; and
wherein the_process~ng device being caused to change an
ANR setting specified by the first set of ANR settings to
an ANR setting specified by the second set of ANR
settings comprises the processing device being caused to
configure the VGA with a gain setting specified by the
second set of ANR settings.
2~. ~e apparatus of claim 23, wherein the processing
device IS caused to change an ANR setting specified by the
first set of ANR settings to an ANR setting specified by the
second set of ANR settings in response to detecting an
instance of clipping of at least feedback ANR anti-noise
sounds.

* * * * *

Copy provided by USPTO from the PIRS Image Database on 07/01/2014