Apple Inc. v. Samsung Electronics Co. Ltd. et al

Filing 925

Administrative Motion to File Under Seal Apple's Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460 filed by Apple Inc.(a California corporation). (Attachments: #1 Declaration of Erica Tierney in Support of Apple's Administrative Motion to File Documents Under Seal, #2 Declaration of Mark D. Selwyn in Support of Apple's Administrative Motion to File Documents Under Seal, #3 Proposed Order Granting Apple Inc.'s Administrative Motion to File Documents Under Seal, #4 Plaintiff and Counterclaim-Defendant Apple Inc.'s Notice of Motion and Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460, #5 Declaration of Mark D. Selwyn in Support of Apple's Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460, #6 Exhibit 1, #7 Exhibit 2, #8 Exhibit 3, #9 Exhibit 4, #10 Exhibit 5, #11 Exhibit 6, #12 Exhibit 7, #13 Exhibit 8, #14 Exhibit 9, #15 Exhibit 10, #16 Exhibit 11, #17 Exhibit 12, #18 Exhibit 13, #19 Exhibit 14, #20 Exhibit 15, #21 Exhibit 16, #22 Exhibit 17, #23 Exhibit 18, #24 Exhibit 19, #25 Exhibit 20, #26 Exhibit 21, #27 Exhibit 22, #28 Exhibit 23, #29 Exhibit 24, #30 Exhibit 25, #31 Exhibit 26, #32 [Proposed] Order Granting Apple Inc.'s Motion for Partial Summary Judgment)(Selwyn, Mark) (Filed on 5/17/2012) Modified on 5/21/2012 attachment #1 and 2 sealed pursuant to General Order No. 62 (dhm, COURT STAFF).

EXHIBIT 20

Attorney Docket No.: 678-509 (P9463)
PATENT AND TRADEMARK OFFICE BEFORE THE
BOARD OF PATENT APPEALS AND INTERFERENCES
APPLICANT(S): Jae-Yoel KIM, et al.

GROUP ART UNIT: 2136

APPLICATION NO.: 09/611,518

EXAMINER: Colin, Carl G.

FILING DATE: July 7, 2000

DATED:¯ September 10, 2007

FOR: APPARATUS AND METHOD FOR GENERATING SCRAMBLING
CODE IN UMTS MOBILE COMMUNICATION SYSTEM
Mail Stop Appeal Brief-Patents
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
APPELLANTS’ BRIEF ON APPEAL

REAL PARTY IN INTEREST
The real party in interest is Samsung Electronics Co, Ltd~ the assignee of the subject
application, having an office at 416, Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do, Republic
of Korea.

RELATED APPEALS AND INTERFERENCES
To the best of Appellants~ l~owledge and belief, there are no currently pending related
appeals, interferences or judicial proceedings.

CERTIFICATE OF MAILING UNDER 37 C.F.R. § ! .8
I hereby certify that this correspondence is being deposited with the United States Postal Service as first class
mail, postpaid in an envelope, addressed to the: Conumssioner for Patents, Alex~indria, VA 22313-1450, Mail Stop

Appeal Brief-Patents on September 10, 2007.
Dated: September 10, 2007
Musella
09/t3/~.007 H])EST~I O00000E3 0%1151~
Ot FC:I~O;~
500.00 OP

APLNDC-WH-A 0000018016

STATUS OF CLAINIS
The original application filed on July 7, 2000 contained Claims 1-30. In a Response filed
June 28, 2004, Claim 26 was amended. In a Response filed January 10, 2005, Claims I and 21 were
amended, Claims 2-20 and 22-30 were cancelled, and Claims 31-53 were newly added. In a
Response filed September 30, 2005, Claims 1, 21, 40-46, 48 and 51 were amended. In a Response
filed April 28, 2006, Claims 48-53 were cancelled, and Claims 54-70 were newly added. In a
Response filed December 1 I, 2006, Claim 54 was amended.
Thus, Claims 1, 21,31-47 and 54-70 are pending in the Appeal. Claims 1,21, 54, 59 and 65
are in independent form.
For the purposes of this appeal, Claims I and 31-37 stand or fall t~gether; Claims 21 and 3847 stand or fall together; Claims 54-58 stand or fall together; Claims 59-64 stand or fall together;
and, Claims 65-70 stand or fail together.

STATUS OF AMENDMENTS :
To date, all of the amendments to the claims have been entered. Thus, the Appendix to this
Appeal Brief includes Claims 1,21,31-47 and 54-70, of which the status of Claims 1,21, 31-47 and
54-70 are indicated as "Previously Presented", and the status of Claims 2-20, 22-30 and 48-53 are
indicated as "Cancelled".

SUMMARY OF CLAIMED SUBJECT MATTER
The invention as recited in Claim 1 relates to a method for generating ~t primary scrambling
code. The method includes generating a first m-sequence from a first m-sequence generator
including first shift registers having first shiR register values ai, wherein i = 0 to c-I and where c is

APLNDC-WH-A 0000018017

the total number of the registers. (Specification at page 19, line 18 to page 20, line 23, FIG. 10).~. The
method further includes generating a second m-sequence from a second m-sequence generator
including second shift registers having values hi, wherein j = 0 to e-t, and where c is the total number
of the registers. (Specification at page 19, line 18 to page 20, line 23, FIG. 10). The method still
further includes masking the first shift register values a~ with a first set of mask values Ki, wherein i
= 0 to c-1 to generate a third m-sequence. (Specification at page 20, lines 14-23, FIG. 10). The
method yet further includes adding the first m-sequence with the second m-sequence to generate a
primary scrambling code. (Specification at page 20, lines 24-26, FIG. 10). The method still yet
further includes adding the third m-sequence and the second m-sequence to generate a secondary
scrambling code. (Specification at page 20, line 26 to page 21, line 19, FIG. 10). Finally, in the
method the masking step shifts the first m-sequence cyclically by L chips to generate an Lth
secondary scrambling code associated with the primary scrambling code. (Specification at page 20,
lines 9-23 and page 10, line 28 to page 1 l, line 15, Equation (1)).
The invention as recited in Claim 21 relates to a scrambling code generator. The scrambling
code generator includes a first m-sequence generator to generate a fi~’st m-sequence by using a
plurality of first registers with first shift register values a~, wherein i = 0 to c-1 and where c is the
total number of the first registers. (Specification at page 19, line 18 to page 20, line 23, FIG. 10). The
scrambling code generator further includes a second m-sequence generator to generate a second msequence by using a plurality of second registers with second shift register values bj, wherein j = 0 to
c- 1 and where c is the total number of second registers. (Spegification at page 19, line 18 to page 20,
line 23, FIG. 10). The scrambling code generator still further includes a masking section to mask the
first shift, register values ai with a first set of mask values Ki to generate a third m-sequence, wherein
i = 0 to c-1 to generate a third m-sequence. (Specification at page 20, lines’ 14-23, F~G. 10). "l’he
scrambling code generator yet further includes a first adder to add the first m-sequence and the
second m-sequence to generate a primary scrambling code. (Specification at page 20, lines 24-26,
FIG. 10). The scrambling code generator still yet further includes a second adder to add the third m-

~ Although a citation for each feature of the claims is provided herein, Appel|a~ts note that support may be found
elsewhere in the written description.

APLNDC-WH-A 0000018018

sequence and the second m-sequence to generate a secondary scrambling code. (Specification at page
20, line 26 to page 21, line 19, FIG. 10). Finally, in the scrambling code generator the masking
section shifts the first m-sequence eyclieallyby L chips to generate an Lt~ secondary scrambling code
associated with the prima~y scrambling code. (Specification at page 20, lines 9-23 and page ~0, line
28 to page 11, line 15, Equation (1)).
The invention as recited in Claim 54 relates to a method for generating scrambling codes in
mobile communication system having a scrambling code generator. The method includes generating
a ((K- 1)*M+K)t~ goId code as a K~ primary scrambling code, where K is a natural number and M is
a total number of secondary scrambling codes per one primary scrambling code. (Specification at
page 18, line 25 to page 19, line 18, FIG. 9). The method further includes generating ((KI)*M+K+I)th through (K*M+K)th gold codes as secondary scrambling codes associated with the Kt~
primary scrambling code. (Specification at page 18, line 25 to page 19, line 18, FIG. 9). Finally, in
the method an Lt~ Gold code is generated by adding an (L-l)-times shifted first m-sequence and a
second m-sequence. (Specification at page 11, lines 6-15).
The invention as recited in Claim 59 relates to an apparatus fo~" ge6erating scrambling codes
in mobile communication system having a scrambling code generator. The apparatus includes a first
m-sequence generator to generate a first m-sequence. (Specification at page 19, line 18 to page 20,
line 23, FIG. 10). The apparatus further includes a second m-sequencegenerator to generate a second
m-sequence. (Specification at page 19, line 18 to page 20, line 23, FIG. 10). The apparatus still
further includes at least one adder for generating a ((K-[)*M+K)th Gold code as a Kth primary
scrambling code by adding a ((K-1)*M+K-1)-times shifted first m-sequence and the second msequence. (Specification at page 18, line 25 to page 19, line l 8, and page 11, lines 6-15). Finally, in
the apparatus K is a natural number and M is a total number of seconda~ s~rambling codes per one
primary scrambling code. (Specification at page 18, line 25 to page 19, line 18).
The invention as recited in Claim 65 relates to a method for generating scrambling codes in
mobile communication system having a scrambling code generator. The method includes generating

APLNDC-WH-A 0000018019

a first m-sequence. (Specification at page 19,.line 18 to page 20, line 23, FIG. 10). The method
further includes generating a second m-sequence. (Specification at page 19, line 18 to page 20, line
23, FIG. 10). The method still fui’ther includes generating a ((K-1)*M+K)th Gold code as aKth
primary scrambling code by adding a ((K- I)*M+K- 1)-times shifted first m-sequence and the second
m-sequence. (Specification at page 18, line 25 to page 19, line 18, and page 11, lines 6-15). Finally,
in the method K is a natural number and M is a total number of secondary scrambling codes per one
primary scrambling code. (Specification at page 18, line 25 to page 19, line 18).

GROUNDS FOR REJECTION TO BE REVIEWED ON APPEAL
Whether Claims 1, 21, 31-47 and 54-70 are unpatentable based on a provisional rejection
under the judicially created doctrine of obviousness-type double patenting as being unpatentable over
Claims 1-32 of copending U.S. patent application serial number 11/003,558.2
Whether Claims 1, 21, 31-~.7 and 54-70 are unpatentable under 35"U.S.. § 103(a) over U.S.
6,339,646 (Dahlman et al.) in view of WO 99/12284 (Dahlman) and U.S. 6,141,374 (Bums).

ARGUMENT
The Examiner provisionally rejected Claims 1, 21, 31-47 and 54-7~ ~inder the judicially
created doctrine of obviousness-type double patenting as being unpatentable over Claims 1-32 of
copending application 11/003,558. The Examiner rejected Claims 1, 21; 31-47 and 54-70 under 35
U.S.C. § 103(a) as being unpatentable over Dahlman et al. in view of Dahlman and Bums.
1. The provisional reiection of Claims 1, 21, 31-47 and 54-70 under" the judicially created doctrine of
obviousness-type double patenting only raises a potential obviousness-type double patenting problem
and thus is not ripe for resolution
Claims 1, 21, 31-47 and 54-70 were provisionally rejected under the judicially created
z U.S. patent application serial number 11/003,558 is a continuation (CON) application cl’aiming the benefit of the
present application, i.e.U.S. 111003,558 is a later filed application.

APLNDC-WH-A 0000018020

doctrine of obviousness-type double patenting as being unpatentable over Claims 1-32 of
copending U.S. Application Serial No. 11/003,558.3 Since the rejection’ is a provisional rejection
and since there remain outstanding art rejections under §103, Appellants respectfully reserve the
right to address this issue if and when all of the remaining art rejections are overcome. See
M.P.E.P. §804.I.B.4
2. Independent Claim 1 is patentable over Dahlman et al. in view of Dahlman and Bums
Independent Claim 1 was said to be unpatentable over Dahlman et al. in view of Dahlman
and Bums.s
Claim 1 recites a method for generating a primary scrambling code. The method includes
generating a first m-sequence from a first m-sequence generator including first shift registers having
first shift register values al, wherein i = 0 to c-1 and where c is the total number of the registers. The
method further includes generating a Second m-sequence from a second m-sequence generator
including second shift registers having values bj, wherein j = 0 to c-1, and where c is the total number
of the registers. The method still further includes masking the first shif~ registervalues ai with a first
set 0fmask values Ki, wherein i = 0 to c-1 to generate a third m-sequence. The m~thod yet further
includes adding the first m-sequence with the second m-sequence to generate a primary scrambling
code. The method still yet further includes adding the third m-sequence and the second m-sequence
to generate a secondary scrambling code. Finally, in the method the masking step shifts the first msequence cyclically by L chips to generate an Lth secondary scrambiing code associated with the
primary scrambling code.
Dahlman et al. discloses slotted mode code usage in a cellular communication system.6
Dahlman discloses a method for assigning spreading codes.7 "
Bums discloses a method and apparatus for generating multiple matched-filter pseudo-

~ See Office Action dated March 7, 2007 at pp 4-5.
4 M.P.E.P. §804.I.B states that the merits of a provisional rejection can be addressed by both the applicant and the
examiner without waiting for the first patent to issue.
~ See Office Action dated March 7, 2007 at pp 6-8.
6 See Dahl.man et al. at title and abstract.
7 See Dahlman at title and abstract.

APLNDC-WH-A 0000018021

random noise vectors in a code divisional multiple access demodulator.8
2A. Claim l teaches that the L~h seeondar~ scrambling code associated with the primary scrambling
code results from adding the second m-sequence and L-times shifted first m-sequence
Claim 1 relates to a method of generating scrambling codes where an Lt~ secondary
scrambling code associated with a prim .a~ scrambling code results from adding a second msequence and an L-times shifted first m-sequence. A clear understanding of Claim 1 can be
characterized in the following statements: 1) In the second adding step a secondary scrambling code
is the result of adding the second m-sequence and the third m-sequence; 2) In the masking step the
third m-sequence is the result of masking the first shift register. The first shift register is the shift
register used to generate that first m-sequence. The masking step produces the third m-sequence; 3)
In the wherein clause the Lth secondary scrambling code is eventually generated when the masking
step cyclically shifts the first m-sequence by L chips. The masking step produces the third msequence, the third m-sequence is the first m-sequence cyclically shifted by L chips, i.e. the Lth third
m-sequence; and 4) Therefore, an Lth secondary scrambling code is generated by adding the second
m-sequence to the Lt~ third m-sequence, the L~ third m-sequence being generated by cyclically
shifting the first m-sequence by L chips during the masking step.
Claim 1 relates to generating related scrambling codes. The scraml61ing codes are generated
from three (3) m-sequences: a first m-sequence, a second m-~equence’, and a third m-sequence. The
third m-sequence is generated using the first m-sequence, and are therefore related to each other.
Two specific scrambling codes are generated from the 3 m-sequences: a primary scrambling code
and a secondary scrambling code. Adding the first and second m-sequences generates the primary
scrambling code. Adding the second and third m-sequences generates the secondary scrambling
code. Since the third m-sequence is a cyclic shift of the first m-sequence,’there is an implicit relation
between the primary scrambling code and the secondary scrambling code.
The masking step processes as follows: the first m-sequence is masked to generate the third
m-sequence; the first m-sequence is cyclically shifted by the masking step to generate the third msequence; if the cyclical shift is 1, then a 1-times shifted first m-sequence is generated as the third ms See Burns at title and abstract.

APLNDC-WH-A 0000018022

sequence; if the cyclical shift is 2, then a 2-times shifted first m-sequence is generatedas the third msequence; and, if the cyclical shift is L, then an L-times shifted first m-sequence is generated as the
third m-sequence. "L-times shifted first m-sequence" is another way of saying a third m-sequence
generated from shifting the first m-sequence L times.
The third m-sequence is used to generate the secondary scrambling code. Therefore, if the
third m-sequence is the 1-times shifted first m-sequence, then a Ist secondary scrambling code is
generated; if the third m-sequence is the 2-times shifted first m-sequence, then a 2nd secondary
scrambling code is generated; and, if the third m-sequence is the L-times shifted first m-sequence,
then an Lth secondary scrambling code is generated.
Therefore, the Lth secondary scrambling code results from adding the second m-sequence and
L-times shifted first m-sequence.
It is well known that Gold codes have no specific order. Likewise, in order to use Gold codes
having no priority as primary and secondary scrambling codes, the currently used primary scrambling
code and the corresponding secondary scrambling codes need to be identified to a base station and a
mobile station. The claims of the present application drastically simplify this process, since if a
primary scrambling code and the corresponding secondary scrambling codes are generated from only
two predetermined m-sequences, the corresponding secondary scrambling codes as well as the
primary scrambling code to be used in the base station can be simply genei’ated by notifying the base
station and the mobile station of only the primary scrambling code.
2B. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose masking the first shift
register values with a first set of mask values to generate a third m-sequence, wherein the maskin~
shifts the first m-sequence cyclically by L chips, neither reference, nor an9 dombination thereof, can
be used to render obvious Claim 1
Independent Claim 1 was said to be unpatentable over Dahlmari et al. in view of Dahlman
and Bums?
Claim I recites, in part, "masking the first shift register values with a first set of mask values
to generate a third m-sequence, wherein the masking shifts the first m-sequence cyclically by L
See Office Action dated March 7, 2007, at page 6.

APLNDC-WH-A 0000018023

chips." None of the cited references teaches or discloses a masking process to generate a third msequence by cyclically shifting a first m-sequence.
The Examiner alleges that Dahlman et al. and Bums teach these features. 10
The Examiner cites Burns as allegedly disclosing generating code sequences and masking to
produce secondary sequences. The Examiner states that it would have been obvious to add the
secondary sequence, i.e. the third m-sequence, with a second m-sequence to produce a secondary
scrambling code. While Bums does teach a single masking circuit 303, this masking circuit is used to
generate matched filter vectors, not to produce a secondary sequence from a first m-sequence. ~
Additionally, Bums utilizes masking to generate a plurality of PN codes having different
offsets. ~2 Bums performs masking to a generated local PN code, while Claim 1 uses masking to shift
a first m-sequence among two different m-sequences (i.e., a first m-sequence and a second msequence) to eventually generate a secondary scrambling code, which is different than in Bums.
Bums discloses a concept of a masking process.13 More specifically, Bums discloses a
method for managing a scrambling code in 1S-95 or CDMA 2000. t4 In Bums, all base stations use an
identical PN code (or a scrambling code), but a unique shift offset for each base station is applied to
the PN code.t~ Accordingly, Bums generates a local PN code identically u’sedby all base stations,
and then performs masking for applying a unique offset to the local PN code for e~ch base station.
However, in Claim l, the masking is applied to an m-sequence, not to the generated PN code
(scrambling code), which is distinguishable from Bums.
Claim 1 recites that the first m-sequence is masked to produce a third m-sequence.
Neither Bums nor Dahlman et al. teach or disclose masking a first m-s~luence to generate a third
m-sequence. Dahlman does not cure this defect.
Therefore, neither Dahlman et al., Dahlman nor Burns, or any combination thereof, teaches of
discloses masking the first shift register values with a first set of mask values togenerate a third msequence, wherein the masking shifts the first m-sequence cyclically by L chips.
SeeOffice Action dated March 7, 2007 at pages 6-8.
SeeBums at col. 8, |ines 2-14.
See Burns at col. 8, lines 2-14.
See Burns at col. 3, lines 4-20.
See Bunts at col. 1, lines 10-15.
See Burns at col. 8, lines 45-61, FIG. 4.

APLNDC-WH-A 0000018024

Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim 1 of the present application, of masking the first shif~
register values with a first set of mask values to generate a third m-sequence, wherein the
masking shifts the first m-sequence cyclically by L chips, Claim 1 cannot be rendered
unpatentable over Dahlman et al., Dahlman nor Burns.
Based on at least the foregoing, the rejection of independent Claim 1 under §103(a) must be
reversed.
2C. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose adding the third msequence and the second m-sequence to generate a secondary scrambling code, neither reference, nor
any combination thereof, can be used to render obvious Claim 1
Independent Claim 1 was said to be unpatentable over Dahlman’ et al. in view of Dahlman
and Bums.~6
Claim 1 recites, in part, "adding the third m-sequence and the second m-sequence to
generate a secondary scrambling code." Claim 1 plainly recites the adding of two m-sequences to
generate a scrambling code.
The Examiner alleges that Bums teaches these features.~7 Specifically, the Examiner
alteges: t8
...and further discloses adding the masking sequence with another
sequence (column 3, line 40 through column 4, line5)...Bums suggests shifts are
multiplied to produce new values then the combined masks are then added to
produce new state values (column 8, lines 45-6l).
In fact, Bums does not "suggest" that which the Examiner believes. Bums actually states at col. 3,
line 40 - col 4, line 5:
The IS-95 system may augment the PN code sequence by inserting an extra
value in the PN code sequence so that the PN code sequence is a multiple of 2.
Additional logic (not shown in FIG. 1) inserts the extra value into each sequence
following 14 consecutive l’s or O’s. The extra value renders a 2t~ Chip period PN
See Office Action dated March 7, 2007 at page 6.
See Office Action dated March 7, 2007 at pages 7-8.
See Office Action dated March 7, 2007 at the bottom of page 7 and the middle of pa~e 8..

10

APLNDC-WH-A 0000018025

sequence. Also, as is known in the art, a periodic bit sequence with a first code phase
maybe combined with another sequence to form the same periodic bit sequence with
a second code phase. This process is known as masking. Consequently, a delayed, or
offset, version of the sequence may be generated by modulo-2 addition of appropriate
state bits of the shift register 102 with a selected mask. Additional logic for
correcting the masked sequences may also be required if the PN code sequence is
augmented.
And, Bums at col. 8, lines 45-6l, states:
Shift register 402 is loaded with a reference state as described with respect to
FIG. 2. Then, for each clock cycle, the values S=St,:~I of the shift register stages are
multiplied by polynomial coefficients gl,:~l via gain amplifiers 404 and combined in
modulo-2 adder 410 to provide new value so. This is a cyclic process. The value so in
modulo-2 adder 410 is then applied to the first element of the shift register 402 and
the last element s~ is discarded. For each state of the shift register 402, a new state
may be provided which corresponds to a value of the PN sequence shifted by an
offset delay. Combining a state ofshitt register 102 with a corresponding mask value
stored in mask register 412 generates this new state. The mask values M---rain.l:0] are
combined with the state of shift register 402 by combiners 414. The combined mask
and register stage values are then modulo-2 added by adder 416 to provide the new
state value oi of the offset sequence Oi,:~1.
.This first section of Bums is describing the apparatus illustrated in FIG. l ,and this second
section of Burns is describing the apparatus illustrated in FIG. 4. Thus, the outputs of the shift
registers of Bums are modulo-2 added to produce a single value. The apparatus of Bums does not
add two (2) m-sequences. The single value of Bums is not and cannot be equated with adding the
third m-sequence and the second m-sequence to generate a secondary scrambling code as recited in
Claim 1.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any com.binati0n thereof, teaches of
discloses adding the third m-sequence and the second m-sequence to generate a secondary
scrambling code.
Since neither Dahlman et al., Dahlman nor Bums, either alone of in combination, teaches
or discloses at least this recitation of Claim l of the present application, of adding the third msequence and the second m-sequence to generate a secondary scrambling code, Claim 1 cannot
be rendered unpatentab]e over Dahlman et aI., Dahlman nor Bums.

APLNDC-WH-A 0000018026

Based on at least the foregoing, the rejection of independent Claim 1 under § 103(a) must be
reversed.
¯ 2D. Independent Claim 1 is not rendered obvious by Dahlman et al. in view of Dahlman and Bums
The Examiner has failed to show that each and every element of Claim 1, and in as complete
detail as is contained therein, are taught in or suggested by the prior art. The Examiner has failed to
make out a prima facia case for an obviousness rejection, and thus Claim 1 is allowable.
3. Dependent Claims 31-37 are also patentable
Dependent Claim 31-37 were said to be unpatentable. Without conceding the patentability
per se of dependent Claims 31-37, these claims are likewise believed to be allowable at least by
virtue of their dependence on Claim 1.
4. Independent Claim 21 is patentable over Dahlman et al. in view of Dahlman and Bums
Independent Claim 21 was said to be unpatentable over Dahlman et al. in view of Dahlman
and Btlrlls119
Claim 21 recites a scrambling code generator. The scramblingcode generator includes a first
m-sequence generator to generate a first m-sequence by using a plurality of first re~isters with first
shift register values ai, wherein i = 0 to c-I and where c is the total number of the first registers. The
scrambling code generator further includes a second m-sequence generator to generate a second msequence by using a plurality of second registers with second shift register values bj, whereinj = 0 to
c-1 and where c is the total number of second registers. The scrambling code generator still further
includes a masking section to mask the first shift register values ai with a first set of mask values K~
to generate a third m-sequence, wherein i = 0 to c- 1 to generate a third m-sequence. The scrambling
code generator yet further includes a first adder to add the first m-sequence and the second msequence to generate a primary scrambling code. The scrambling code generator still yet further
includes a second adder to add the third m-sequence and the seco~ad ~-sequence to generate a
secondary scrambling code. Finally, in the scrambling code generator the masking section shifts the
See Office Action dated March 7, 2007 at page 6, and pages 8-10.

12

APLNDC-WH-A 0000018027

first m-sequence cyclically by L chips to generate an Lth secondary scrambling code associated with
the primary scrambling code.
Dahlman et al. discloses slotted mode code usage in a cellular communication system.2°
Dahlman discloses a method for assigning spreading codes.2~
Bums discloses a method and apparatus for generating multiple matched-filter pseudorandom noise vectors in a code divisional multiple access demodulator.2~
4A. Claim 21 teaches that the Lth secondary scrambling code associated with the primary scrambling
code results from adding the second m-sequence and L-times shifted first m-sequence
Claim 21 relates to a scrambling code generator where an Lt~ secondary scrambling code
associated with a primary scrambling code results from adding a second m-sequence and an L-times
shifted first m-sequence.
As stated above in section 2A, neither Dahlman et al., Dahlman or Burns teach or disclose a
scrambling code generator where an Lt~ secondary scrambling code associated with a primary
scrambling code results from adding a second m-sequence and an L-times shifted first m-sequence.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any c0mbination thereof, teaches of
discloses a scrambling code generator where an Lt~ secondary scrambling code associated with a
primary scrambling code results from adding a second m-sequence and an L-times shifted first msequence.
since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim.21 of the present applicatioh, of a scrambling code
generator where an Lth secondary scrambling code associated with a primary scrambling code
results from adding a second m-Sequence and an L-times shified first m-sequence, Claim 21
cannot be rendered unpatentable over Dahlman et al., Dahlman nor Burrls~
Based on at least the foregoing, the rejection of independent Claim 21 under § 103(a) must be
reversed.

Se~ Dahlman et al, at title and abs’a’aet.
See Dahlman at title and abstract.

13

APLNDC-WH-A 0000018028

4B. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose a masking section to mask
the first shift register values with a first set of mask values to generate a third m-sequence, wherein
the masking shifts the first m-sequence cyclically by L chips, neither reference, nor any combination
thereof, can be used to render obvious Claim 21
Claim 21 recites to a scrambling code generator having a masking section to mask the first
shift register values with a first set of mask values to generate a third m-sequence, wherein the
masking shifts the first m-sequence cyclically by L chips.
As stated above in section 2B, neither Dahlman et al., Dahlman or Bums teach or disclose a
scrambling code generator having a masking section to mask the first shift register values with a first
set of mask values to generate a third m-sequence, wherein the masking shifts the first m-sequence
cyclically by L chips.
Therefore, neither Dahlman et ai., Dahlman nor Bums, or any combination thereof, teaches of
discloses a scrambling code generator having a masking section to mask the first shift register values
with a first set of mask values to generate a third m-sequence, whereiri the masking shifts the first msequence cyclically by L chips.
Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim 21 of the present application, of a scrambling code
generator having a masking section to mask the first shift register values with a fi~st set of mask
values to generate a third m-sequence, wherein the masking shifts the first m-sequence cyclically
by L chips, Claim 21 cannot be rendered unpatentable over Dahlman et ~.1., Dahlman nor Bums.
Based on at least the foregoing, the rejection of independent Claim 2 ~ under §103(a) must be
re~,ersed.
4C. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose an adder for adding the
third m-sequence and the second m-sequence to generate a secondary"s~rambling code, neither
reference, nor any combination thereof, can be used to render obvious Claim 21
Claim 21 recites to a scrambling code generator having an adder for adding the third msequence and the second m-sequence to generate a secondary scrambling code.
See Bums at title and abstract.
14

APLNDC-WH-A 0000018029

As stated above in section 2C, neither Dahlman eta]., Dahlman or Bums teach or disclose a
scranabling code generator having an adder for adding the third m-sequence and the second msequence to generate a secondary scrambling code.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any combination thereof,
teaches of discloses a scrambling code generator having an adder for adding the third m-sequence
and the second m-sequence to generate a secondary scrambling code.
Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim 21 of the present application, of a scrambling code
generator having an adder for adding the third m-sequence and the second m-sequence to
generate a secondary scrambling code, Claim 21 cannot be rendered unpatentable over Dahlman
et al., Dahlman nor Burns.
Based on at least the foregoing, the rejection of independent Claim 21 under § 103(a) must be
reversed.
4D. Independent Claim 21 is not rendered obvious b~’Dahlman et al. in view o’fDahlman and Bums
The Examiner has failed to show that each and every element of Claim 2 l, and in as complete
detail as is contained therein, are taught in or suggested by the prior art. The Examiner has failed to
make out a prima facia case for an obviousness rejection, and thus Claim 21 is allowable.
5. Dependent Claims 38-47 are also patentable
""
Dependent Claim 38-47 were said to be unpatentable. Without conceding the patentability
per se of dependent Claims 38-47, these claims are likewise believed to be allowable at least by
virtue of their dependence on Claim 21.
6. Independent Claim 54 is patentable over Dahlman et al. in view of Dahlman and Bums
Independent Claim 54 was said to be unpatentable over Dahlman et al. in view of Dahlman
and Bums.23
Claim 54 recites a method for generating scrambling codes in mobile communication system
See Office Action dated March 7, 2007 at page 6, and pages 12-14,

15

APLNDC-WH-A 0000018030

having a scrambling code generator. The method includes generating a ((K- I)*M+K)th gold code as a
Kt~ primary scrambling code, where K is a natural number and M is a total number of secondary
scrambling codes per one primary scrambling code. The method further includes generating ((KI)*M+K+ 1)th through (K*M+K)th gold codes as secondary scrambling codes associated with the Kth
primary scrambling code. Finally, in the method an Lth Gold code is generated by adding an (L-1)times shifted first m-sequence and a second m-sequence.
Claim 54 relates to method for efficiently dividing the set of Gold sequences into a primary
scrambling code set and a secondary scrambling code set to reduce the number of mask functions
stored in the memory.
Dahlman et al. discloses slotted mode code usage in a cellular communication system.24
Dahlman discloses a method for assigning spreading codes.25
Bums discloses a method and apparatus for generating multiple matched-filter pseudorandom noise vectors in a code divisional multiple access demodulator.26
6A. Claim 54 recites that the L-th Gold code is generated by adding the (L-1)-times shifted first m
sequence and the second m-sequence
Claim 54 recites that the L-th Gold code is generated by adding the (L-1)-times shifted first m
sequence and the second m-sequence.
Based on arguments similar to those set forth above in section 2A, neither Dahlman et al.,
Dahlman or Bums teach or disclose that an L-th Gold code is generated by adding the (L- 1)-times
shifted first m sequence and the second m-sequence.
Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches or
discloses at least this recitation of Claim 54 of the present application, bf generating an L-th Gold
code by adding the (L-1)-times shifled first m sequence and the second m-sequence, Claim 54 cannot
be rendered unpatentable over Dahlman et al., Dahlman nor Bums.
Based on at least the foregoing, the rejection of independent Claim 54 under § 103(a) must be
reversed.
See Dahlman et al. at title and abstract.
See Dahlman at title and abs~act.

16

APLNDC-WH-A 0000018031

6B. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose generating a
1 }*M+K)-th gold code as a K-th primary scrambling code, where K is a natural number and M is a
total number of secondary scrambling codes per one primate scrambling code, neither referencel nor
any combination thereof, can be used to render obvious Claim 54
Claim 54 recites generating a ((K- 1)*M+K)-th gold code as a K-th primary scrambling code,
where K is a natural number and M is a total aumber of secondary scrambling codes per one primary
scrambling code. Thus in Claim 54 a K-th primary scrambling code is generated. A specific gold
code is used as the K-th primary scrambling code. The specific gold code is the ((K-1)*M+K)-th
gold code. The K-th primary scrambling code is directly related to the total number of secondary
scrambling codes per one primary scrambling code.
The Examiner alleges that generating a ((K-I)*M+K)-th gold code as a K-th primary
scrambling code of Claim 54 is disclosed by Dahlman et al.27 The Examiner cites Dahlman et al. at
col 4, lines 34-57, and Claims 13-23 as disclosing this feature.
Nowhere in Dahlman et al., either the written description or the claims, is there disclosed that
a K-th primary scrambling code is directly related to the total number o fsecondary scrambling codes
per one primary scrambling code. Dahlman et al. teaches:28
""
The scrambling codes typically used in the existing systems are built from, for
example, Gold codes, which ensures that the output sequences from the shift regSster
are different for different starting values. Assuming that the normal mode
transmission scrambling code, Cj, is generated using a certain starting value, then the
scrambling codes to be used for slotted transmissions, Cj.~ and Cj.z, can be generated
by loading the shift register with a slightly modified value. For example,.iftwo bits in
the starting value for the normal mode transmission scrambling code, Cj, are "00", the
associated slotted mode scrambling codes, Cj.~ and Cj,2, can be generated by changing
those two bits in the scrambling code generator shift register to "01" and "11",
respectively. As an alternative to loading the shift register with a slightly modified
value in order to generate the scrambling codes to be used for slotted transmissions,
the same scrambling code as for a normal transmission eould be used, but with a
different code phase.

See Burns at title and abstract.
See Office.Action dated March 7, 2007 at bottom of page 12 to the top of page 13..
See Dahlman et al. at col. 4, lines 40-57.

17

APLNDC-WH-A 0000018032

Thus in Dahlman et al., the relation between a primary scrambling code and a secondary scrambling
code is a loading of a shift register with a slightly modified value,z9 Dahlman and Bums do not cure
these defects.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any combination thereof,
teaches of discloses generating a ((K-l)*M+K)-th gold code as a K-th primary scrambling code,
where K is a natural number and M is a total number of secondm’y scrambling codes per one
primary scrambling code.
Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim 54 of the present application, of generating a ((Kl)*M+K)-th goldeode as a K-th primary scrambling code, where K is a natural number and M is
a total number of secondary scrambling codes per one primary scrambling code, Claim 54 cannot
be rendered unpatentable over Dahlman et al., Dahlman nor Bums.
Based on at least the foregoing, the rejection of independent Claim 54 under § 103(a) must be
reversed.
6C. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose generating from ((KI)*M+K+I )-th to (K*M+K)-th Gold codes as secondary scrambling codes associated with the K-th
primary scrambling code, neither reference, nor any combination thereof, can be used to render
obvious Claim 54
Claim 54 recites generating from ((K-1)*M+K+I)-th to (K*M+K)-th Gold codes as
secondary scrambling codes associated with the K-th primary scrambling code.
Thus in Claim 54 the secondary scrambling codes are generated. Specific gold codes are used
as the secondary scrambling codes. The specific gold codes are the ((K-I)*M+~ 1)-th to (K*M+K)th Gold codes. The secondary scrambling codes are directly related to the total numl~er of secondary
scrambling codes per one primary scrambling code.
The Examiner again alleges that generating from ((K-I)*M+K+I)-th to (K*M+K)-th Gold
codes as secondary scrambling codes associated with the K-th primary scrambling code of Claim 54

See Dahh’nan el al. at col. 4, lines 45-47.

APLNDC-WH-A 0000018033

is disclosed by Dahlman et al.3° The Examiner uses the same citation for the pervious feature to
allegedly reject these features, namely the Examiner cites Dahlman et al. at col 4, tines 34-57, and
Claims i3-23 as disclosing this feature.
Nowhere in Dahlman.et al., either the written description or the claims, is there disclosed that
secondary scrambling codes are directly related to the total number of secondary scrambling codes
per one primary scrambling code. Dahlman et al. teaches?~
The scrambling codes typically used in the existing systems are built fi’om, for
example, Gold codes, which ensures that the output sequences from the shift register
are different for different starting values. Assuming that the normal mode
transmission scrambling code, Cj, is generated using a certain starting value, then the
scrambling codes to be Used for slotted transmissions, Cj.~ and C j.2, can be generated
by loading the shift register with a slightly modified value. For example, if two bits in
the starting value for the normal mode transmission scrambling code, Cj, are "00", the
associated slotted mode scrambling codes, Cj.~ and Cj~2, can be generated by changing
those two bits in the scrambling code generator shift register to "01" and "11",
respectively. As an alternative to loading the shift register with a slightly modified
value in order to generate the scrambling codes to be used for slotted transmissions,
the same scrambling code as for a normal transmission could be used, but with a
different code phase.
Thus again in Dahlmanet al., the relation betxveen a primary scrambling code and a secondary
scrambling code is a loading of a shift register with a slightly modified value,n Dahlman and Bums
do not cure these defects.
Therefore, neither Dahlmanet al., Dahlman nor Bums, or any combination thereof,
teaches of discloses generating from ((K-1)*M+K+I)-th to (K*M+K)-th Gold codes as
secondary scrambling codes associated with the K-th primary scrambling code.
Since neither Dahlman et al., Dahlman nor Bums, either alone o[.in combination, teaches
or discloses at least this recitation of Claim 54 of the present application; of generating from ((K1)*M+K+l)-th to (K*M+K)-th Gold codes as secondary scrambling code~ associated with the Kth primary scrambling code, Claim 54 earmot be rendered unpatentable.over Dahlman et al.,
Dahlman nol: Bums.
See Office Action dated March 7, 2007 at bottom of page 12 to the top of page i3.
See Dahlman et al. at col. 4, lines 40~57.
See Dahlman et al. at col. 4, lines 45-47.

19

APLNDC-WH-A 0000018034

Based on at least the foregoing, the rejection of independent Claim 54 under § 103(a) must be
reversed.
6D. Independent Claim 54 is not rendered obvious by Dahlman et al. in view of Dahlman and Bums
The Examiner has failed to show that each and every element of Claim 54, and in as complete
detail as is contained therein, are taught in or suggested by the prior art. The Examiner has failed to
make out a prima facia case for an obviousness rejection, and thus Claim 54 is allowable.
7. Dependent Claims 55-58 are also patentable
Dependent Claim 55-58 were said to be unpatentable. Without conceding the patentability
per se of" dependent Claims 55-58, these claims are likewise believed to be allowable at least by
virtue of their dependence on Claim 54.
8. Independent Claim 59 is patentable over Dahlman et al. in view of Dahlman and Bums
Independent Claim 59 was said to be unpatentable over Dahlman et al. in view of Dahlman
and Burns.s3
Claim 59 recites an apparatus for generating scrambling codes in mobile communication
system having a scrambling code generator. The apparatus includes a firs! m-sequence generator to
generate a first m-sequence. The apparatus further includes a second m-sequence generator to
generate a second m-sequence. The apparatus still further includes at least one adde~ for generating a
((K-I)*M+K)th Gold code as a Kt~ primary scrambling code by adding a ((K-1)*M+K-l)-times
shifted first m-sequence and the second m-sequence. Finally, in the apparatus K is a natural number
and M is a total number of secondary scrambling codes per one primary scrambling code.
Dahlman et al. discloses slotted mode code usage in a cellular communication system.~
Dahlman discloses a method for assigning spreading codes?s
Bums discloses a method and apparatus for generating multiple matched-filter pseudo-

See Office Action dated March 7, 2007 at page 6 and pages 15-17.
See Dahlman et al. at tide and abstract.
See Dahlman at title and abstract.

20

APLNDC-WH-A 0000018035

random noise vectors in a code divisional multiple access demodulator..36
8A. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose at least one adder for
generating a ((K-1)*M+K)t~ Gold code as a Kt~ primary scrambling code by adding a ((K- I)*M+K1)-times shifted first m-sequence and the second m-sequence, wherein K is a natural number and M
is a total number o f secondary scrambling codes per one primary scrambling code, neither reference,
nor any combination thereof, can be used to render obvious Claim 59
Claim 59 recites at least one adder for generating a ((K-I)*M+K)th Gold code as a Kth
primary scrambling code by adding a ((K-1)*M+K-1)-times shifted first m-sequence and the second
m-sequence, wherein K is a natural number and M is a total number of secondary scrambling codes
per one primary scrambling code.
Thus in Claim 59 a K-th primary scrambling code is generated. A specific gold code is used
as the K-th primary scrambling code. The specific gold code is the ((K- 1 )*M+K)-th gold code. The
((K-1)*M+K)th gold code is generated by adding a ((K-1)*M+K-l)-times shifted first m-sequence
and the second m-sequence. The K-th primary scrambling code is directly related to the total number
of secondary scrambling codes per one primary scrambling code.
The Examiner alleges that generating a ((K-1)*M+K)-th gold code as a K-th primary
scrambling code of Claim 59 is disclosed by Dahlman et al?7
As stated above in section 2C, neither Dahlman et al., Dahlman or Bums teach or disclose an
adder for adding two m-sequences to generate a scrambling code, namely, at least one adder for
generating a ((K-I)*M+K)th Gold code as a K~ primary scrambling code by adding a ((K- I)*M+Kl)-times shifted first m-sequence and the second m-sequence. .
Also, Claim 59 recites that the time shifting of the first m-sequence is related to ((K1)*M+K-1). Thus the time shift of the first m-sequence is directly related to the total number of
secondary scrambling codes per one primary scrambling code.
Dahlman et al. states that the relation between a primary scrambling code and a secondary

See Bums at title and abstract
See Office Action dated March 7, 2007 at pages 15-17,

21

APLNDC-WH-A 0000018036

scrambling code is a loading of a shift register with a slightly modified value.3s Dahlman and Bums
do not cure these defects.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any combination thereof,
teaches of discloses at least one adder for generating a ((K-I)*M+K)t~ Gold code as a Kt~ primary
scrambling code by adding a ((K-1)*M+K-1)-times shifted first m-sequence and the second msequence, wherein K is a natural number and M is a total number of secondary scrambling codes
per one primary scrambling code.
Since neither Dahlman et al., Dahlman nor Bums, either alone or in combination, teaches
or discloses at least this recitation of Claim 59 of the present application, of at least one adder for
generating a ((K-1)*M+K)th Gold code as a Kth primary scrambling code by adding a ((K1)*M+K-1)-times shifted first m-sequence and the second m-sequence, wherein K is a natural
number and M is a total number of secondary scrambling codes per one primary scrambling
code, Claim 59 cannot be rendered unpatentable over Dahlman et al., Dahlman nor Bums.
Based on at least the foregoing, the rejection of independent Claim 59 under § 103(a) must be
reversed.
8B. Independent Claim 59 is not rendered obvious by Dahlman et al. in view of Dahlman and Bums
The Examiner has failed to show that each and every element of Claim 59, and in as complete
detail.a~ is contained therein, are taught in or suggested by the prior art. The Examiner has failed to
make out a prima facia case for an obviousness rejection, and thus Claim 59 is allowable.
9. Dependent Claims 60-64 are also patentable
Dependent Claim 60-64 were said to be unpatentable. Without conceding the patentability
per se of dependent Claims 60-64, these claims are likewise believed to be allowable at least by
virtue of their dependence on Claim 59.
10. Independent Claim 65 is patentable over Dahlman et al. in view of Dahlman and Bums
Independent Claim 65 was said to be unpatentable over Dahlman et al. in view of Dahlman
See Dahlrnan et al. at col. 4, lines 45-47.

22

APLNDC-WH-A 0000018037

and Bums?9
Claim 65 recites a method for generating scrambling codes in mobile communication system
having a scrambling code generator. The method includes generating a first m-sequence¯ The method
further includes generating a second m-sequence. The method still further includes generating a ((K1)*M+K)th Gold code as a K~h primary scrambling code by adding a ((K-1)*M+K- 1 )-times shined
first m-sequence and the second m-sequence. Finatly, in the method K is a rtaturat number and M is a
total number of secondary scrambling codes per one primary scrambling code.
Dahlman et al. discloses slotted mode code usage in a cellular communication system.4°
Dahlman discloses a method for assigning spreading codes.4~
Burns discloses a method and apparatus for generating multiple matched-filter pseudorandom noise vectors in a code divisional multiple access demodulator.42
10A. Since neither Dahlman et al. nor Dahlman nor Bums teach or disclose generating a ((K1)*M+K)th Gold code as a K.t~ primary scrambling ~ode by adding a ((K-1)*M+K- l)-times shifted
first m-sequence and the second m-sequence, wherein K is a natural numl~er and M is a total number
of secondary scrambling codes per one primary scrambling code, neither reference, nor any
combination thereof, can be used to render obvious Claim 65
Claim 65 recites generating a ((K- 1)*M+K)th Gold code as a K’h primary scrambling code by
adding a ((K-1)*M+K-l)-times shifted first m-sequence and the second m-sequence, wherein K is a
natural number and M is a total number of secondary scrambling cod6s p~r one primary scrambling
code.
As stated above in section 8A, neither Dahlman et al., Dahlman or Bums teach or disclose
generating a ((K- 1)*M+K)th Gold code as a Kth primary scrambling code by adding a ((K-1)*M+K1)-times shifted first m-sequence and the second m-sequence, wherein K is a natural number and M
is a total number of secondary scrambling codes per one primary scrambling code.
Therefore, neither Dahlman et al., Dahlman nor Bums, or any combination thereof,
See Office Action dated March 7, 2007 at page 6 and pages 18-20.
See Dahlman et al. at title and abstract.
See Dahlman at title and abstract.
See Burns at title and abstract,

23

APLNDC-WH-A 0000018038

teaches of discloses generating a ((K-1)*M+K)th Gold code as a Kth primary scrambling code by
adding a ((K-1)*M+K-1)-times shifted first m-sequence and the second m-sequence, wherein K
is a natural number and M is a total number of secondary scrambling codes per one primary
scrambling code.
Since neither Dahlman et at., Dahlman nor Bums, either alone or in combination, teaches
or discloses generating a ((K-1)*M+K)~ Gold code as a Ktl~ primary scrambling code by adding a
((K-1)*M+K-l)-times shifted first m-sequence and the second m-sequence, wherein K is a
natural number and M is a total number of secondary scrambling codes per one primary
scrambling code, Claim 65 carm0t be rendered unpatentable over Dahlman et al., Dahlman nor
Bums.
Based on at least the foregoing, the rejection of independent Claim 65 under § 103(a) must be
reversed.
10B. Independent Claim 65 is not rendered obvious by Dahlman et al. in view of Dahlman and Bums
The Examiner has failed to show that each and every element 6f Claim 65, and in as complete
detail as is contained therein, are taught in or suggested by the prior art. The Examiner has failed to
make out a prima facia case for an obviousness rejection, and thus Claim 65 is allowable.
11. Dependent Claims 66-70 are also patentable
Dependent Claim 66-70 were said to be unpatentable. Without conceding the patentability
per se of dependent Claims 66-70, these claims are likewise believed to be allowable at least by
virtue of their dependence on Claim 65.

CONCLUSION
As the Examiner has failed to make out a prima facie case for an obviousness rejection, the
rejection of Claims 1, 21, 31-47 and 54-70 must be reversed.
It is well settled that in order for a rejection under 35 U.S.C. §163(a) to be appropriate, the
claimed invention must be shown to be obvious in view of the prior art as a whole. A claim may be
24

APLNDC-WH-A 0000018039

found to be obvious if it is first shown that all of the recitations of a claim are taught in the prior art
or are suggested by the prior art. In re Royka, 490 F.2d 981,985, 180 U.S.P.Q. 580, 583 (C.C.P.A.
1974), cited in M.P.E.P. §2143.03.
The Examiner has failed to show that all of the recitations of Claims 1,21, 31-47 and 54-70
are taught or suggested by the art of record, or the combination thereof. Accordingly, the Examiner
has failed to make out a prima faeie ease for an obviousness rejection.
Independent Claims 1,21,54, 59 and 65 are not rendered unpatentable by either Dahlman et
ai., Dahlman or Bums, or any combination thereof. Therefore, the rejections ot~Claims 1,21,54, 59
and 65 must be reversed.
Dated: September 10, 2007
B~
Paul J.
Reg. No.:
Attorney for Applicant(s)/Appeti~nt(s)
THE FARRELL LAW FIRM, P.C..
333 Earle Ovington Blvd., Suite 701
Uniondale, New York 11553
[phone] (tel)
[phone] (fax)

25

APLNDC-WH-A 0000018040

CLAIMS APPENDIX

1. (Previously Presented) A method for generating a primary scrambling code, the method
comprising the steps of:
generating a f~rst m-sequence from ~ first m-sequence generator including first shift registers
having first shift register values ai, wherein i = 0 to c-I and where c is the total number of the
registers;
generating a second m-sequence from a second m-sequence generator including second shift
registers having values bj, wherein j = 0 to c-l, and where e is the total number of the registers;
masking the first shift register values ai with a first set of mask values Ki, wherein i = 0 to c-1
to generate a third m-sequence;
adding the first m-sequence with the second m-sequence to generate a primary scrambling
code; and
adding the third m-sequence and the second m-sequence to generate a secondary scrambling
code;
wherein, the masking step shifts the first m-sequence cyclically by L chips to generate an Lth
secondary scrambling code associated with the primary scrambling code.
2-20. (Cancelled)
21. (Previously Presented) A scrambling code generator, comprising:
a first m-sequence generator to generate a first m-sequence by using a plurality of first
registers with first shift register values ai, wherein i = 0 to c-I and where’c is the total number of the
first registers;
a second m-sequence generator to generate a second m-sequence by using a plurality of
second registers with second shift register values bj, wherein j = 0 to c-’l and where c is the total
number of second registers;
a masking section to mask the first shift register values ai with a first set of mask values Ki to
generate a third m-sequence, wherein i = 0 to c-1 to generate a third m-se~luence;
26

APLNDC-WH-A 0000018041

a first adder to add the first m-sequence and the second m-sequence to generate a primary
scrambling code; and
a second adder to add the third m-sequence and the second m-sequence to generate a
secondary scrambling code,
wherein the masking section shifts the first m-sequence cyclically by L chips to generate an
’h secondary scrambling code associated with the primary scrambling code.
L
22-30. (Cancelled)
3h (Previously Presented) The method of claim I, wherein the primary scrambling code is
one ofa pIurality primary scrambling codes and a Kth primary scrambling code is a ((K-I)*M+K)t~
gold code, where M is a total number of secondary scrambling codes per primary scrambling code
and l<K<512~
32. (Previously Presented) The method of claim 1, wherein the secondary scrambling codes
associated with a K.tl~ primary scrambling code are from ((K-I)*M+K+I)~ to (K*M+K)~ gold codes,
where M is a total number of secondary scrambling codes per primary scrambling code and
1<K<512.
33. (Previously Presented) The method of claim 1, .wherein I<L<M, where M is a total
number of secondary scrambling codes per primary scrambling code.
34. (Previously Presented) The method of claim 1, wherein the masking step is expressed by

~ (~, × ~,).
35. (Previously Presented) The method of claim 1, further comprising:
masking the first shift register values ai with a second set of mask values Ki to generate a
fourth m-sequence, wherein j = 0 to c-l; and
adding the fourth m-sequence and the second m-sequence to generate an Nth secondary
27

APLNDC-WH-A 0000018042

scrambling code associated with the primary scrambling code;
wherein, the masking step shifts the first m-sequence cyclically by N chips to generate an N~
secondary scrambling code.
36. (Previously Presented) The method of claim 35, wherein I<N<M, where M is a total
number of secondary scrambling codes per primary scrambling code.
37. (Previously Presented) The method of claim 1, further comprising the step of delaying at
least one of the primary scrambling code and secondary scrambling code to produce a Q-channel
component, wherein the primary scrambling code and secondary scrambling code are I-channel
components.
38. (Previously Presented) The scrambling code generator of claim 21, wherein the primary
scrambling code is one of a plurality of primary sc~’ambling codes and a Kt~ primary scrambling code
is a ((K- 1)*M+K)th gold code, where M is a total number of secondary scrambling codes per primary
scrambling code and I<K<512.
39. (Previously.Presented) The scrambling code generator ofclhim 38, wherein the secondary
scrambling codes associated with the Kth primary scrambling code are ((K-1)*M+K+I)th to
(K*M+K)t~ gold codes.
40. (Previously Presented) The scrambling code generator of claim 21, further comprising:
a second masking section to mask the first shift register values ai~ with a second set of mask
values Kj, wherein j = 0 to c-l, to generate a fourth m-sequence; and
a third adder to add the fourth m-sequence and the second m-sequence to generate an N-th
secondary scrambling code associated with the primary scrambling code’, ’
wherein the second masking section shifts the first m-sequence cyclically by N chips to
generate the Nt~ secondary scrambling code.
’

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41. (Previously Presented) The scrambling code generator of claim 21, wherein the masking
section shifts the first m-sequence cyclically by masking the first shift register values a~ in accordance
with E (K, x a, ).

42. (Previously Presented) The scrambling code generator of claim 21, wherein the first msequence generator cyclically shifts the first shift register values and the second m-sequence
generator cyclically shifts the second shift register values.
43. (Previously Presented) The scrambling code generator of claim 21, wherein the first msequence generator adds predetermined shift register values of the first shi ft registers based on a first
generating polynomial of the first m-sequence, fight shifts the first shift register values ai of the first
shift registers, and replaces the first register value a,:, with the result of the addition of the
predetermined register values.
44. (Previously Presented) The scrambling code generator of claim 21, wherein the first msequence generator adds a first shift; register value a0 with a first shift register a7 to form a next first
shift register a~.l.
45. (Previously Presented) The scrambling code generator of claim 21, wherein the second msequence generator adds predetermined shift register values of the second shift registers based on a
second generating polynomial of the second m-sequence, right shifts the second shift register values
bj of the second shift registers, and replaces the second register value bLt with the result of the
addition of the predetermined register values.
46. (Previously Presented) The scrambling code generator of claim 21, wherein the second msequence generator adds a second shift register value b0 with a second shift register value b5, bT, and
a second shift register value bt0 to form a next second shift register value bc-t.
47. (Previously Presented) The apparatus of claim 21, further comprising a means for
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delaying at least one of the primary scrambling code and the secondary scrambling code to produce
Q-channel component, wherein the primary scrambling code and the secondary scrambling code are
I-channel components.
48 - 53. (Cancelled)
54. (Previously Presented) A method for generating scrambling codes in mobile
communication system having a scrambling code generator, the method comprising steps of:
generating a ((K- I)*M+K/~ gold code as a Kth primary scrambling code, where K is a natural
number and M is a total number of secondary scrambling codes per one primary scrambling code;
and
generating ((K-1 )*M+K+I )~ through (K*M+K)th gold codes as secondary scrambling codes
associated with the Kth primary scrambling code,
wherein an Ltl~ Gold code is generated by adding an (L-l)-times shifted first m-sequence and
a second m-sequence.
55. (Previously Presented) The method as claimed in claim 54, wherein K is a primary
scrambling code number and 1 ~ K< 512.

56. (Previously Presented) The method as claimed in claim 55, wherein the first m-sequence
is generated from a first shift register memory having a plurality of first shift !’egisters with firstshift
register values ai, wherein i = 0 to c- 1 and where c is the total number of the first, registers and the (L1)-times shifted first m-sequence is generated by masking the first shill register values ai with mask
values K,., where i = 0 to c-l.
57. (Previously Presented) The method as claimed in claim 56, wherein the masking is
performed according to: ~(K~ x a,).

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58. (Previously Presented) The method as claimed in claim 54, wherein the generated primary
scrambling code and secondary scrambling code are I-channel components and the method further
comprises delaying at least one of the primary scrambling code and secondary scrambling code to
produce Q-channel components.
59. (Previously Presented) An apparatus for generating scrambling codes in mobile
communication system having a scrambling code generator, comprising:
a first m-sequenc~ generator to generate a first m-sequencE;
a second m-sequence generator to generate a second m-sequence; and
at least one adder for generating a ((K-I)*M+K)th Gold code as a Kth primary scrambling
code by adding a ((K-1)*M+K-1)-times shifted first m-sequence and the second m-sequence,
wherein K is a natural number and M is a total number of secondary scrambling codes per
one primary scrambling code.
60. (Previously Presented) The apparatus of claim 59, wherein the secondary scrambling
codes of the Ka~ primary scrambling codes are the ((K- 1)*M+K+ 1)t~ through (K*M+K)~ Gold codes.
61. (Previously Presented) The apparatus as claimed in claim 60, wherein K is a primary
scrambling code number and 1~ K< 512.

62. (Previously Presented) The apparatus as claimed in claim 59, wherein the first m. sequence generator comprises a plurality of first ~egisters with first shift register values ai, wherein i
= 0 to c-1 and where e is the total number of the first shift registersl and the scrambling code
generato.r further comprising at least one masking section for generating the n-times shifted first msequence by masking the first shift register values ai with mask values K,., where i = 0 to c-1.
63. (Previously Presented) The apparatus as claimed in claim 62, wherein the masking is
performed according to: E (K,× a,).

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64. (Previously Presented) The apparatus as claimed in claim 59, wherein the primary
scrambling code and secondary scrambling code are I-channel components and the apparatus further
comprises a means for delaying at least one of the primary scrambling codes and secondary
scrambling code to produce Q-channel components.
65. (Previously Presented) A method for generating scrambling codes in mobile
communication system having a scrambling code generator, comprising the steps of:
generating a first m-sequence;
generating a second m-sequence; and
generating a ((K-1)*M+K)th Gold code as a Kth primary scrambling code by adding a ((K1)*M+K-1)-times shifted first m-sequence and the second m-sequence,.
wherein K is a natural number and M is a total number of secondary scrambling codes per
one prim, ary scrambling code.
66. (Previously Presented) The method as claimed in claim 65, further comprising generating
((K-1 )*M+K+ l)th to (K*M+K)th Go ld codes as secondary scrambling codes corresponding to the K~
primary scrambling code.
67. (Previously Presented) The method as claimed in claiN 651 wherein K is a primary
scrambling code number and 1~ KN 512.

68. (Previously Presented) The method as claimed in claim 65, wherein the first m-sequence
is generated from a first shift register memory having a plurality of ftrs, t shift registers with first shift
register values ai, wherein i = 0 to c- 1 and where c is the total number of the first registers and the ntimes shifted first m-sequence is generated by masking the first shift register values ai with mask
values K~, where i = 0 to c-l.

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69. (Previously Presented) The method as claimed in claim 68, wherein the masking is
performed according to: ~(K, x

70. (Previously Presented) The method as claimed in claim 65, wherein each scrambling code
is used as an I-channel component and a Q-charmel component, corresponding to the I-channel
component, is generated by delaying the I-channel component for a predetermined time.

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EVIDENCE APPENDIX
There is no evidence submitted pursuant to 37 C.F.R. 1. 130, 1.131, 1.132 or entered by the
Examiner and relied upon by Appellant.

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RELATED PROCEEDINGS APPENDIX

There are no known decisions rendered by a court or the Board in any proceeding identified
pursuant to paragraph (c)(~.)(ii) of 37 C.F.K. 41.37.

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