Apple Inc. v. Samsung Electronics Co. Ltd. et al

Filing 925

Administrative Motion to File Under Seal Apple's Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460 filed by Apple Inc.(a California corporation). (Attachments: #1 Declaration of Erica Tierney in Support of Apple's Administrative Motion to File Documents Under Seal, #2 Declaration of Mark D. Selwyn in Support of Apple's Administrative Motion to File Documents Under Seal, #3 Proposed Order Granting Apple Inc.'s Administrative Motion to File Documents Under Seal, #4 Plaintiff and Counterclaim-Defendant Apple Inc.'s Notice of Motion and Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460, #5 Declaration of Mark D. Selwyn in Support of Apple's Motion for Summary Judgment of Non-Infringement of U.S. Patent Number 7,362,867 and Invalidity of U.S. Patent Numbers 7,456,893 and 7,577,460, #6 Exhibit 1, #7 Exhibit 2, #8 Exhibit 3, #9 Exhibit 4, #10 Exhibit 5, #11 Exhibit 6, #12 Exhibit 7, #13 Exhibit 8, #14 Exhibit 9, #15 Exhibit 10, #16 Exhibit 11, #17 Exhibit 12, #18 Exhibit 13, #19 Exhibit 14, #20 Exhibit 15, #21 Exhibit 16, #22 Exhibit 17, #23 Exhibit 18, #24 Exhibit 19, #25 Exhibit 20, #26 Exhibit 21, #27 Exhibit 22, #28 Exhibit 23, #29 Exhibit 24, #30 Exhibit 25, #31 Exhibit 26, #32 [Proposed] Order Granting Apple Inc.'s Motion for Partial Summary Judgment)(Selwyn, Mark) (Filed on 5/17/2012) Modified on 5/21/2012 attachment #1 and 2 sealed pursuant to General Order No. 62 (dhm, COURT STAFF).

EXHIBIT 1

US007362867B1

(12) United States Patent

(10) Patent No.: US 7,362,867 B1
(45) Date of Patent:
Apr. 22, 2008

Kim et al.
(54)

APPARATUS AND METHOD FOR
GENERATING SCRAMBLING CODE IN
UMTS MOBILE COMMUNICATION SYSTEM

(75)

Inventors: Jae-Yoel Kim, Kunpo-shi (KR);
Hee-Won Kang, Seoul (KR)

(73)

Assignee: Samsung Electronics Co., Ltd (KR)

(*)

Notice:

6,496,474 B1 *
6,526,091 B1 *
6,542,478 B1 *
6,560,212 B1 *

12/2002
2/2003
4/2003
5/2003

Nagatani et al .............
Nystrom et al .............
Park ...........................
Prasad et al ................

370/208
375/142
370/308
370/335

(Continued)
FOREIGN PATENT DOCUMENTS
EP

Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 668 days.

0 963 070

12/1999

(Continued)
OTHER PUBLICATIONS

(21)

Appl. No.: 09/611,518

European Search Report for EP Appln. No. 00942496.1 dated May
23, 2002.

(22)

Filed:

Primary Examiner Kambiz Zand
Assistant Examiner~arl Colin
(74) Attorney, Agent, or Firm The Farrell Law Firm, PC

(30)

Jul. 7, 2000
Foreign Application Priority Data

Jul. 7,1999

(KR) ............................... 1999-27279

(57)

ABSTRACT

(51) Int. CI.

(52)
(58)

(56)

HO4K 1/00
(2006.01)
U.S. Cl ........................... 380/275; 380/33; 380/34;
380/47 380/268; 380/273; 375/150; 375/152
Field of Classification Search ................ 370/335,
370/342 380/239, 209, 255, 11 15,219 221,
380/268 275, 33, 34, 47, 140, 273; 375/155,
375/200, 150, 152
See application file for complete search history.
References Cited

U.S. PATENT DOCUMENTS
3,818,442 A *
6/1974
4,320,513 A
3/1982
4,707,839 A *
11/1987
5,771,288 A *
6/1998
6,108,369 A *
8/2000
6,141,374 A *
10/2000
6,339,646 B1 *
1/2002
6,459,722 B2* 10/2002

Solomon ....................
Lampert
Andren et al ...............
Dent et al ...................
Ovesjo et al ...............
Burns .........................
Dahlman et al ............
Sriram et al ................

714/781
375/150
380/270
375/146
375/152
380/273
375/130

A scrambling code generating apparatus of a downlink
transmitter in a UMTS mobile communication system,
which uses one primary scrambling code for separation of
base stations and multiple secondary scrambling codes for
channel separation. The apparatus includes a first m-sequence generator for generating a first m-sequence and a
second m-sequence generator for generating a second m-sequence. A first summer adds the first and second m-sequences to generate the primary scrambling code. A plurality
of first masking sections each shift the first m-sequence, and
a plurality of second masking sections corresponding to the
respective first masking sections each shifts the second
m-sequence. A plurality of second summers each adds one
of the first shifted m-sequences with the second m-sequence
corresponding to the first m-sequence. The output of the
second summers thus generates the multiple secondary
scrambling codes.
36 Claims, 11 Drawing Sheets

APLNDC-WH-A 0000018113

US 7,362,867 B1
Page 2
U.S. PATENT DOCUMENTS
6,574,205 B1 *
6/2003
6,728,305 B2* 4/2004
6,728,411 B2* 4/2004

Sato ...........................
Ogawa et al ...............
Bottou et al ................

370/335
375/148
382/240

FOREIGN PATENT DOCUMENTS
JP
59-047833
3/1984
WO
WO 9912284 A1 * 3/1999
WO
WO 99/26369
5/1999
¯ cited by examiner

APLNDC-WH-A 0000018114

U.S. Patent

Apr. 22, 2008

Sheet 1 of 11

US 7,362,867 B1

lOO
SCRAMBLING CODE
GROUP GENERATOR
110
1,30
5CRAMBL£R

CODE 1

DPDCH

COOE 2
¯!

¯
¯

104

118

SCRAM-,
BLER

135,

119

FIG. 1

APLNDC-WH-A 0000018115

U.S. Patent

Apr. 22, 2008

,

US 7,362,867 B1

Sheet 2 of 11

20t

INFORMATION
DELAY ~._. 203

201

k

CONTROL 2~OLD 5EOU£N~ C ENERATOR [ ’ ~_.~
INFORMATION
201
CONTROL
(NFORMA~

t

~ ,

-

¯

DELAY ~-203

,m

FIG.

APLNDC-WH-A 0000018116

U.S. Patent

Apr. 22, 2008

Sheet 3 of 11

US 7,362,867 B1

/
[ SCRAMBLING CODEI
~ROUP GENERATOR
320

330

322
324

335

i~

DESCRAMBL£R

DPDCH~

FIG. 3

APLNDC-WH-A 0000018117

U.S. Patent

Apr. 22, 2008

Sheet 4 of 11

US 7,362,867 B1

401
INFORMATION
4,01
INFORMATION

L_~ OELAY 403 ~
L

,

~ 403 ;

FIG. 4

APLNDC-WH-A 0000018118

U.S. Patent

T

Apr. 22, 2008

Sheet 5 of 11

US 7,362,867 B1

500--,.~ .

FIG. 5

APLNDC-WH-A 0000018119

U.S. Patent

Apr. 22, 2008

Sheet 6 of 11

US 7,362,867 B1

21~262144 CHIPS
PRIMARY
E:RAMBLING CODE

l-ST SECONDARY
~CRAMBLING CODE

5.-1H SECONDARY
SCRAMBLING CCOE
~---3B400 CHIPS.-.~,

FIG.

APLNDC-WH-A 0000018120

SECTICN

" Z(k’,

750

744

700

DELAY

DELAY

705

724
I
I

|
¯

I
"76O

DELAY
722

FIG.

U.S. Patent

Apr. 22, 2008

Sheet 8 of 11

US 7,362,867 B1

I

APLNDC-WH-A 0000018122

FIG. 9
_,~8400 [;HIPS _

II

N-1H SET OF SEC~DARY
SCRAMBUNG CODE

U.S. Patent

Apr. 22, 2008

Sheet 10 of 11

US 7,362,867 BI

I
I

APLNDC-WH-A 0000018124

U.S. Patent

Apr. 22, 2008

Sheet 11 of 11

US 7,362,867 B1

APLNDC-WH-A 0000018125

US 7,362,867 B1
1

2

APPARATUS AND METHOD FOR
GENERATING SCRAMBLING CODE IN
UMTS MOBILE COMMUNICATION SYSTEM

ones. Namely, the number of the primary scrambling codes
used must be large enough, e.g., 512 lest that the mobile
station should concurrently detect signals of base stations
sharing the same primary scrambling codes. Thus the individual adjacent base stations use distinct primary scrambling
PRIORITY
codes among the 512 primary scrambling codes. When there
This application claims priority to an application entitled exists no more orthogonal code with a primary scrambling
"Apparatus and Method for Generating Scrambling Code in
code to be allocated for channel separation, the individual
UMTS Mobile Communication System" filed in the Korean base station uses secondary scrambling code selected from
Industrial Property Office on Jul. 7, 1999 and assigned Serial 10its multiple secondary scrambling code groups correspondNo. 99-27279, the contents of which are hereby incorporated ing to the primary scrambling codes used.
by reference.
An exemplary unit using the multiple scrambling codes is
a downlink in the UMTS system. It should be noted that for
BACKGROUND OF THE INVENTION
the purpose of illustration, the term "scrambling code" is
15 interchangeable with the term "gold code" or "gold
1. Field of the Invention
sequence" indicating the same code as the scrambling code.
The present invention relates generally to an apparatus
FIG. 1 is a schematic diagram showing the structure of a
and method for generating scrambling codes in a mobile downlink transmitter in the UMTS mobile communication
communication system, and more particularly, to an appasystem.
ratus and method for generating a plural scrambling code 2o Referring to FIG. 1, upon receiving a dedicated physical
using masking codes.
control channel DPCCH and dedicated physical data chan2. Description of the Related Art
nels DPDCH1, . . . , and DPDCH,v, which are previously
A code division multiple access mobile communication
channel-coded and interleaved, demultiplexers 11)I)-11)4
system (hereinafter, referred to as "CDMA system") uses
(corresponding in number to the number of physical data
scrambling codes for the purpose of separating base stations. 25 channels N plus one for the DPCCH) divide the dedicated
The European W-CDMA system, UMTS (Universal Mobile
physical control channel DPCCH and the dedicated physical
Telecommunication System) generates multiple scrambling
data channels DPDCH1, . . . , and DPDCHN into I (Incodes classified into a plural scrambling code group of a
phase) and Q (Quadrature) channels. The I and Q channels
predetermined length. As a method for increasing capacity
separately output from the demultiplexer 101 are fed into
in addition to separation of base stations, which is the 30 multipliers 110 and 111, respectively. The multipliers 110
objective of using the scrambling codes in the CDMA
and 111 multiply the I and Q channels by an orthogonal code
system, orthogonal codes for multiple scrambling code
1 for channel separation, respectively, and send the output to
groups are used to separate channels. That is, when all
a scrambler 121). Similarly, the I and Q channels separately
orthogonal codes for channel separation are used up for a
output from the demultiplexers 11)2 through 11)4 are subscrambling code group, the mobile communication system 35 jected to the same operation as described above and fed into
may utilize a second scrambling code group to increase the
N scramblers 124 through 128, respectively. Then, a scramnumber of available communication links. The UMTS
bling code group generator 100 generates secondary scrammobile communication system uses a gold sequence with a
bling codes corresponding to the scramblers 121), 124
length of 21’-1 as scrambling codes in order to have through 128 and outputs them to the corresponding scrammultiple scrambling codes (one primary scrambling code 4o blers. Here, the scramblers 121), 124 through 128 multiply
and multiple secondary scrambling code in one base station)
the output signals of the corresponding multipliers by the
constituted by multiple scrambling code groups. The gold
output signals of the scrambling code group generator 100 in
sequence with a length of 21’-1 includes a group of 2~*-1
a complex mode, to output the real parts of the scrambled
distinct gold codes. The gold sequences of the same group
signals to a summer 131) and the imaginary parts of the
have a good correlation characteristic with one another. 45 scrambled signals to a summer 138. The summer 131) sums
Here, the gold sequence with a length of 2~*-1 is divided
up the real parts of the scrambled signals from the scraminto 38400 chips and repeatedly used for scrambling.
blers 120, 124 through 128, while the summer 138 sumps up
Each base station in the UMTS mobile communication
the imaginary parts.
systems has a unique scrambling code called "primary
FIG. 2 is a schematic block diagram of the scrambling
scrambling code" that is used to allow terminals to differ- 5o code group generator 100 shown in FIG. 1, which concurentiate each base station from other base stations in the
rently generates multiple scrambling code groups. Although
system. Also the each unique scrambling code used for
it is the fact that only primary scrambling codes are to be
spreading (scrambling) downlink channel signals of each used for common control channels and data channels, secbase stations is referred to as "primary scrambling code",
ondary scrambling codes may be used in place of the
and one of the scrambling code group used for scrambling 55 primar,v scrambling codes to increase the number of availdownlink data channels in case that an orthogonal codes is
able communication links. For example, if base station A
not available using the primary scrambling code is called uses primary scrambling code B with available orthogonal
"secondary scrambling code". The base station user its
codes C-H and all of the orthogonal codes C-H have been
unique primary scrambling codes for spreading(scrambling)
assigned to various channels, there are no more available
common control channel signals transmitted to all mobile 60 orthogonal codes that can be assigned to new channels if a
stations with corresponding orthogonal code, for spreading
new terminal wants to communicate with base station A. In
(scrambling) data channel signals transmitted to currently
that case, instead of using primary scrambling code A,
communicating mobile stations with corresponding orthogosecondary scrambling code Z can be used in place of
nal codes which are assigned to each of the data channel
primar,v scrambling code A for the new channels, and
signals for downlink channel separation. The base station 65 orthogonal codes C-H can then be assigned to the new
has its unique primary scrambling codes in order for a
channels because the new channels use secondary scrammobile station to discriminate the base station from adjacent
bling code Z instead of primary scrambling code A. Thus,

APLNDC-WH-A 0000018126

US 7,362,867 B1

3

4

the new channels can be differentiated from the original
FIG. 5 is a schematic diagram illustrating the structure of
channels that used the m-sequence codes C-H because the
the gold sequence generators shown in FIGS. 2 and 4.
new channels use secondary scrambling code Z instead of
Referring to FIG. 5, a gold sequence is normally generprimary code A. Thus the base station has to be capable of
ated through binary adding to two distinct m-sequences. A
5 shift register that generates the upper m-sequence is implegenerating multiple scrambling code groups.
Referring to FIG. 2, the normal scrambling code group
mented with a generator polynomial defined as f(x)-x18+
generator 100 includes a plurality of gold sequence generax7+l, and a shift register generating the lower m-sequence
f(X)~X18+xlO+x7+x3 + l"
is implemented with a generator polynomial defined as
tors 201 and a plurality of delays 203 corresponding to the
gold sequence generators 201. Upon receiving control information about the scrambling codes for multiple channels 10 In the present UMTS standard specification, there is no
from an upper layer, the gold sequence generators 201
description for scrambling code numbering and its generagenerate scrambling codes, i.e., gold sequence codes based tion. Therefore, in the light of the UMTS standard specifion the control information and output the generated scramcation the receiver and the transmitter require many scrambling codes to have an I-channel component. The delays 203
bling code generators described above to generate multiple
delay the scrambling codes with the I-channel component 15 scrambling codes and thus uses distinct generators for the
for a predetermined number of chips and generate delayed
individual scrambling codes, which leads to an increase in
scrambling codes having a Q-channel component.
the hardware complexity. Furthermore, when using gold
FIG. 3 is a schematic diagram showing the structure of a
sequences as the scrambling codes, the hardware complexity
downlink receiver in the UMTS mobile communication
may be dependent on the way the scrambling codes are
system. For downlink common control channels, the 20 divided into primary and secondary scrambling codes and
dependent on how the scrambling codes are numbered.
receiver has to descramble the downlink common control
signals which have been scrambled with the primary scramSUMMARY OF THE INVENTION
bling codes. Simultaneously, for downlink data channels, the
receiver also has to descramble the signal scrambled with
the secondary scrambling code when the downlink data 25 It is, therefore, an object of the present invention to
provide an apparatus and method for generating scrambling
channel uses secondary scrambling code. Thus the receiver
codes grouped in units of a predetermined length using mask
must have a capacity of generating multiple scrambling
functions, thereby minimizing hardware complexity.
codes.
Referring to FIG. 3, upon receiving signals from the
It is another object of the present invention to provide an
transmitter as shown in FIGS. 1 and 2, the I- and Q-channel 30 apparatus and method for generating scrambling codes
including a primary scrambling code and associated secondcomponents of the received signals are fed into descramblers
ary scrambling codes to be used in place of the primary
310 and 315, respectively. A scrambling code group genscrambling code to increase the number of available comerator 300 concurrently generates scrambling codes corremunication links. The scrambling codes are generated by
sponding to the respective channels and outputs them to the
descramblers 310 and 315. Then, the descramblers 3111 and 35 using mask functions. It is further another object of the
315 multiply the receives signals I+jQ by the conjugates of
present invention to provide an apparatus and method generating a primary scrambling code and associated secondary
the scrambling codes received from the scrambling code
scrambling codes. In an embodiment of the present invengroup generator 300 to descramble the received signals, and
tion, a first shift register is used to generate a first m
then output the I- and Q-channel components of the
descrambled signals to corresponding multipliers 320, 322, 4o sequence and a second shift register is used to generate a
324 and 326. Here, orthogonal codes assigned to the respecsecond m sequence. The first m sequence is added with the
second m sequence to generate a primary scrambling code.
tive channels are despread at the multipliers 320, 322, 324
and 326 and output to corresponding demultiplexers 3311 and
To generate the associated second scrambling codes, the bits
350. The demultiplexers 330 and 350 demultiplex the
of the first shift register are entered into N masking sections
despread I- and Q-channel components, respectively.
45 which use masking functions to cyclically shift the first m
FIG. 4 is a schematic block diagram of the scrambling
sequence. The outputs of each of the masking sections are
added with the second m sequence to generate N secondary
code group generator 31111 shown in FIG. 3, which concurscrambling codes. It is further another object of the present
rently generates multiple scrambling code groups. Although
invention to provide an scrambling codes numbering scheme
the scrambling code group generator 300 is to use primary
scrambling codes for common control channels in fact, it can 5o for simple generation of the scrambling codes by one
scrambling code generator.
also use secondary scrambling codes for channels used
depending on the users, such as data channels, in case of a
To achieve the above objects of the present invention,
lack of available orthogonal codes. Thus the mobile station
there is provided a method for generating one primary
has to be capable of generating multiple scrambling code scrambling code assigned to a base station and multiple
groups.
55 secondary scrambling codes with two m-sequence generaReferring to FIG. 4, the scrambling code group generator
tors each having plurality of concatenated shift registers, the
300 of the receiver includes a plurality of gold sequence
method including the steps of: generating a first m-sequence_by first m-sequence generator having a given generation
generators 401 and a plurality of delays 403 corresponding
to the gold sequence generators 401. Upon receiving control
polynomial_and a second m-sequence by second m-seinformation about the scrambling codes for multiple chan- 6o quence generator having a given generation polynomial
nels from an upper layer, the gold sequence generators 401
different from the first m-sequence generation polynomial;
generate gold sequence codes corresponding to the control
adding the output of the first m-sequence generator and the
information and output the generated gold sequence codes to
output of the second m-sequence generator to generate first
have an I-channel component. The delays 403 delay the gold
primary scrambling code for generating primary scrambling
sequence codes with the I-channel component for a prede- 65 code; receiving all values of a first m-sequence registers;
termined number of chips to generate the gold sequence
multiplying the first m-sequence register values with a mask
codes of a Q-channel component.
value which is determining secondary scrambling code and

APLNDC-WH-A 0000018127

US 7,362,867 B1
5
summing the multiplied values at every clock signal; and
a UMTS mobile communication system in accordance with
generating i-th secondary scrambling code by adding the
the first embodiment of the present invention;
summed value and second m-sequence generator’s output.
FIG. 9 is a diagram showing the structure of a scrambling
code in accordance with a second embodiment of the present
In another aspect of the present invention, there is provided an apparatus for generating multiple scrambling codes
invention;
FIG. 10 is a detailed diagram showing the structure of a
in a CDMA mobile communication system, which generates
scrambling code group generator of a downlink transmitter
one primary scrambling code assigned to a base station and
in a UMTS mobile communication system in accordance
multiple secondary scrambling codes, the apparatus includwith the second embodiment of the present invention; and
ing: a first m-sequence generator having plurality of serial
concatenated shift register for generating a first m-sequence; 10 FIG. 11 is a detailed diagram showing the structure of a
scrambling code group generator of a downlink receiver in
a second m-sequence generator having plurality of serial
a UMTS mobile communication system in accordance with
concatenated shift register for generating a second m-sethe second embodiment of the present invention;
quence; a first summer for adding the first and second
m-sequences to generate the primary scrambling code; at
DETAILED DESCRIPTION OF THE
least a masking sections for receiving each of the first 15
PREFERRED EMBODIMENT
m-sequence generator’s register values (ai), multiplying the
register values and mask values (ki) which is determining
A preferred embodiment of the present invention will be
secondary scrambling code by shifting the first m-sequence
and summing the multiplied values (aixki); adding the described below with reference to the accompanying drawsecond m-sequence with the summed values to generate the 2o ings. In the following description, well-known functions or
constructions are not described in detail since they would
secondary scrambling code. In further another aspect of the
obscure the invention in unnecessary detail.
present invention, there is provided a scrambling code
A gold code used herein as a scrambling code is generated
generating apparatus of a downlink transmitter in a UMTS
mobile communication system, which uses one primary through binary adding of two distinct m-sequences. Assumscrambling code for separation of base stations and multiple 25 ing that the two m-sequences each having a length L are
defined as ml(t) and m2(t), respectively, a set of gold codes
secondary scrambling codes for channel separation, the
may comprise L distinct gold sequences with good correlaapparatus including: a first m-sequence generator for gention characteristic with one another. The set of gold codes
erating a first m-sequence; a second m-sequence generator
can be expressed by Equation 1.
for generating a second m-sequence; a first summer ~br
adding the first and second m-sequences to generate the 30 Equation 1
G <m1 (t+’~)+m2(t)10-<’~-<L-1 > where, t is a time variable
primary scrambling code; a plurality of masking sections,
number and’~ is shift value. As understood from Equation 1,
each of the first masking sections for shifting the first
the set of gold codes is a set of all sequences that comprises
m-sequence; and a plurality of second summers, each of the
the sun1 of the m-sequence ml(t) cyclically shifted "~ times
second summers for adding one of the shifted first m-sequences with the second m-sequence, the output of the 35 and the m-sequence m2(t). Thus, for the purpose of the
present invention, the sum of the m-sequence ml(t) cyclisecond summers generating the multiple secondary scramcally shifted "~ time and the m-sequence m2(t) will be
bling codes.
designated as a gold code g~. That is, g~(t) ml(t+’l:)+m2(t).
If the period of the gold code is 21*-1, then the individual
BRIEF DESCRIPTION OF THE DRAWINGS
4o m-sequences constituting the gold code also have a period of
21*-1. Thus the m-sequence ml(t) can be cyclically shifted
The above and other objects, features and advantages of
the present invention will become more apparent from the a maximum of 21*-1 times and the number of elements in
the set of the gold codas is equal to 21*-1, which is the
following detailed description when taken in conjunction
maximum value of the cyclic shift.
with the accompanying drawings in which:
FIG. 1 is a schematic diagram showing the structure of a 45 The set of gold codes used in the embodiments of the
known downlink transmitter in a general UMTS mobile present invention has 21*-1 gold codes as elements each of
which comprises an m-sequence ml(t) having a generator
commua~ication system;
defined as f(x)~xla+x7+l and an m-sequence
FIG. 2 is a schematic block diagram of a known scram- polynomial generator polynomial defined as f(x)~xla+xl°+
m2(t) with a
bling code group generator shown in FIG. 1;
7+x5+1.
FIG. 3 is a schematic block diagram showing the structure 50 X Another m-sequence ml(t cyclically shifted "~ times can
of a known downlink receiver in the general UMTS mobile be obtained by applying)mask functions to the memory
communication system;
values of a shift register generating the original m-sequence.
FIG. 4 is a schematic block diagram of a known scramThe embodiments of the present invention provide a
bling code group generator shown in FIG. 3;
55 generator for concurrently generating multiple gold
FIG. 5 is a detailed diagram showing the structure of a sequences using the mask functions, and a method for
known scrambling gold group generator in the general
efficiently dividing the set of gold sequences into a primary
UMTS mobile communication system;
scrambling code set and a secondary scrambling code set to
FIG. 6 is a diagram showing the structure of a scrambling reduce the number of mask functions stored in the memory.
code in accordance with a first embodiment of the present 6o First Embodiment
invention;
FIG. 6 is a diagram showing the structure of primary and
FIG. 7 is a detailed diagram showing the structure of a secondary scrambling codes in accordance with a first
scrambling code group generator of a downlink transmitter
embodiment of the present invention.
in a UMTS mobile communication system in accordance
First, when a gold sequence is selected from 21’-1 length
with the first embodiment of the present invention;
65 gold sequences, the first 38400 chips are used as a primary
FIG. 8 is a detailed diagram showing the structure of a scrambling code, the second 38400 chips a first secondary
scrambling code group generator of a downlink receiver in
scrambling code corresponding to the primary scrambling

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US 7,362,867 B1
7

8

code, the third 38400 chips a second secondary scrambling
The second m-sequence generator 760 generates a second
code corresponding to the primary scrambling code, the
m-sequence using the register memory 705 and the adder
735 which is binary adder that adds the binary values from
fourth 38400 chips a third secondary scrambling code corthe registers 0, 5, 7 and 10 of the register memory 705 and
responding the primary scrambling code, the fifth 38400
chips a fourth secondary scrambling code corresponding to 5 outputs the sum into the register 17. The register 0 of the
register memory 705 sequentially outputs binary values that
the primary scrambling code, the sixth 38400 chips a fifth
form the second m-sequence during every period of the
secondary scrambling code corresponding to the primary
input clock. The masking sections 714 to 716 store each
scrambling code. Here, when 512 primary scrambling codes
mask code values (s~i to sN,.) for generating cyclical shifts of
are used, there are five groups of secondary scrambling
10 the second m-sequence by a predetermined number of chips.
codes corresponding to the 512 primary scrambling codes.
The cyclical shifts are achieved by multiplying the mask
Specifically, 218-1 (the length of scrambling codes) divided
code values by the register value "b," of the second shift
by 38400 is equal to six (scrambling code groups). Out of six
register memory 705. The resulting values are provided to
m-sequence code groups, the first scrambling code group is
the adders 742 to 744, respectively. Each of the m-sequence
used as primary scrambling codes and the remaining five 15 generators 750 and 760 generates an m-sequence according
scrambling code groups are used as secondary scrambling to the corresponding generator polynomial.
codes. In tlfis structure, if a cell (base station) uses its own
The adder 740 adds the 0-th register values_(i.e., the last
primary scrambling code and secondary scrambling codes
bits) of the first and second shift register memories 700 and
selected out of its own secondary scrambling codes group,
705 to generate a scrambling code, which becomes the
then the selected secondary scrambling codes belonging to
2o primary scrambling code. The adders 742 to 744 add one bit
the secondary scrambling code group corresponding to the
generated from each of the masking sections 710 to 712
primary scrambling code will be used for downlink channel
connected to the first shift register memory 700 to one bit
scrambling codes when orthogonal codes are not available generated from the masking sections 714 to 716 correspondwith the primary scrambling code. As shown in FIG. 6, once
ing to the masking sections 710 to 712, respectively. In other
a primary scrambling code is selected, the secondary scram- 25 words, the output from the first masking section 710 from
bling codes corresponding to the primary scrambling code
the first group is added with the output from the first
are also part of a gold code which also includes the primary
masking section 714 from the second group and so on, until
scrambling code. Here, the secondary scrambling codes are
the output from the N-th masking section 712 from the first
generated through application of mask functions to the
group is added with the output from the N-th masking
primary scrambling codes. This method is adapted to a 3o section 716 from the second group. Thus, each of the
scrambling code group generator of a transmitter as illusmasking sections 710-712 in the first group has a corretrated in FIG. 7, which concurrently generates one primary
sponding masking section in the masking section s 714-716
scrambling code and multiple secondary scrambling codes.
of the second group. The outputs from the corresponding
Referring to FIG. 7, the scrambling code group generator
masking sections are added together in the adders 742-744,
701 comprises a first m-sequence generator 750 including: 35 respectively. That is, the individual masking sections have a
an upper shift register memory (hereinafter, referred to as
conjugate on a one-to-one basis with respect to the first and
"first shift register memory") 700 (with registers 0 to 17) and
second shift register memories 700 and 705. For example,
an adder 730, a second m-sequence generator 760 including;
the first masking section 710 of the first shift register
a lower shift register memory (hereinafter, referred to as
memory 700 corresponds to the first masking section 714 of
"second shift register memory") 705 (with registers 0 to 17) 4o the second shift register memory 705, the N-th masking
and an adder 735, a plurality of masking sections 710 to 712,
section 712 corresponding to the N-th masking section 716,
714 to 716, a plurality of adders 742 to 744 and 740, and a
and so on. Between the two conjugate masking sections (i.e.,
plurality of delays 722 to 724 and 720. The first shift register
first masking sections 710 and 714, or N-th masking sections
memory 700 stores a predetermined register initial value
712 and 716) is connected the adder 742 to 744 that add the
"ao" and the second shift register memory 705 stores a 45 two bits output from the masking sections in response to the
predetermined register initial value "bo". The values stored
input block. Here, the output signals of the summers 742 to
in each of the registers in the memory’ 700 and the memory
744 have an l-channel component.
705 may change during every period of an input clock (not
The delay 722 to 724 and 720 delay the I-channel signals
shown). The register memory 700 and 705 store 18 bit (or
for a predetermined mm~ber of chips to generate respective
symbol) binary values "ai" and "bi", respectively (i 0 to c-1 5o Q-channel signals.
where c~the total number of registers in the register memoNow, a description will be given to an operation of the
ries 700 and 705).
present invention as constructed above.
The first m-sequence generator 750 generates a first
Once an initial value for the primary scrambling code is
m-sequence using the register memory 700 and the adder
applied to the first and second shift register memories 700
730 which is a binary, adder that adds the binary values from 55 and 705 each having 18 registers for cyclically shifting the
the registers 0 and 7 of the register memory 700 and outputs
register value "a," or "b,", the 0-th register values of the first
the sum into the register 17. The register 0 of the register
and second shift register memories 700 and 705 are fed into
memory 700 sequentially outputs binary values that form the
the adder 740 and the 18 register values "a~" of the first shift
first m-sequence during every period of the input clock. The
register memory 700 are fed into the first to N-th masking
masking sections 710 to 712 store mask code values (kl~ to 6o sections 710 to 712 in order to generate cyclically shifted
kN,.) for generating cyclical shifts of the first m-sequence by
sequences of the first shift registers. Meanwhile, the 18
a predetermined number of chips. The cyclical shifts are
register values "hi" of the second shift register memory 705
achieved by multiplying the mask code values by the
are fed into the first to N-th masking sections 714 to 716 in
register value "a~" of the first shift register memory 700, as
order to generate cyclically shifted sequences of the first
expressed by the following equation: Z(kZ~xa~) (L 1 to N). 65 shift registers. Then, the first masking section 710 masks the
The resulting values are provided to the adders 742 to 744,
input values from the first (upper) shift register memory 700
respectively.
(all 18 bits from 18 registers in the shift register memory

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700) with a mask function kli (i.e., Y(klixa~)) and outputs the outputs the masked values to an summer 815 for generating
masked values to the summer 744 for generating the first the secondary scrambling code. Then, the adder 810 adds the
secondary scrambling code. The masking is concurrently
output bits from the 0-th registers of the first and second shift
processing in every masking sections 710-712. The N-th
register memories 800 and 805 to generate I-channel primasking section 712 masks the input values from the first 5 mary scrambling code signals. These I-channel primary
(upper) shift registers with a mask function k~ (i.e., Z(k~x scrambling code signals are immediately delayed for a
a~)) and outputs the masked values to the summer 742 for
predetermined number of chips at a delay 830 to generate
Q-channel primary scrmnbling code signals. The adder 815
generating the N-th secondary scrambling code. The N-th
masking section 716 masks the input values from the second
adds the output bits from the masking sections 820 and 825
(lower) shift registers with a mask function s~ (i.e., Z(s~,.x10 to generate I-channel primary scrambling code signals,
ai)) and outputs the masked values to the summer 744 for
which are immediately delayed at a delay 835. Then, the 0-th
generating the N-th secondary scrambling code. The first
and seventh register values of the first shift registers are
masking section 714 masks the input values from the added at the adder 800, and the added value is output to the
register memory 705 with a mask function s~ (i.e., Y(s~xa~)) seventeenth register, as the left-sided values are shifted to
and outputs the resulting values to the adder 742 for gen- 15 the right side by one. The 0-th, fifth, seventh and tenth
erating the first secondary scrambling code. Each of the
register values of the second shift registers are added at the
masking sections 710-712 masks the input values from the adder 805, and the added value is output to seventeenth
first shift register memory 700 and outputs the masked value
register, as the left-sided values are shifted to the right side
to the respective adders 742-744. Then, the adder 740 adds
by one. This procedure is repeated to generate multiple
the output bits from the 0-th registers of the first and second 2o scrambling codes.
shift register memories 700 and 705. These generated output
The scrambling code generator of the first embodiment
signals are immediately delayed at the delay 720. The adder needs plurality of distinct mask functions stored in the
744 adds the output bits from the N-th masking sections 712
masking sections in order to generate each secondary scramand 716 to generate I-channel signals, which are immedi- bling code, i.e., it uses 2N mask functions to generate N
ately fed into the delay 724. The delay 722 delays the 25 scrambling codes. Accordingly, the structure of primary and
I-channel signals output from the adder 742 for a predetersecondary scrambling codes shown in FIG. 6 enables implemined number of chips to generate Q-channel scrambling
mentation of the scrambling code generator of the transsignals. The adder 742 adds the output bits from the first
ceiver structure shown in FIG. 7 or 8, which further includes
masking sections 710 and 714 to generate I-channel signals.
only 2N mask functions with a quite little hardware cornThese I-channel signals are immediately delayed for a 30 plexity to generate multiple scrambling codes.
predetermined number of chips at the delay 722. Then, the
Second Embodiment
0-th and seventh register values of the first shift register
FIG. 9 is a diagram showing the structure of primary and
memory 700 are added at the summer 730 and the added secondary scrambling codes in accordance with a second
value is inputted to the seventeenth register, as the left-sided
embodiment of the present invention. While the first
values are shifted to the right side by one and the utmost 35 embodiment masks both m-sequences m~(t) and nl2(t) to
left-sided register is newly filled with the output value of the
generate scrambling codes, the second embodiment involves
summer 730. The 0-th, fifth, seventh, and tenth register cyclic shift of the m-sequence m2(t) only other than m, (1) to
values of the second shift register memory 705 are added at
generate scrambling sequences. That is, this embodiment is
well expressed by Equation 1.
the adder 735, the added value is inputted into the seventeenth register, as the left-sided values are shifted to the right 4o
Referring to FIG. 9, when M secondary scrambling codes
side by one and the utmost left-sided register (i.e., the
correspond to one primary scrambling code, the first (M+2)seventeenth register) with the output value of the summer
th, (2M+3)-th ..... ((K-1)*M+K)-th ..... and (511M+
735. This procedure is repeated to generate multiple scram512)-th gold codes are used as primary scrambling codes.
bling codes.
The secondary scrambling codes corresponding to the ((KFIG. 8 is a diagram showing a scrambling code generator45 1)*M+K)-th gold code used as the (K)-th primary scramof a receiver for concurrently generating one primary scram- bling code are composed of M gold codes, i.e., ((K-1)*M+
bling code and one secondary scrambling code. The receiver
(K+I)), ((K-1)*M+(K+2)) .... and (K*M+K)-th gold
has only to use scrambling codes for a common control
codes. Here, with 512 primary scrambling codes used, each
channel and a data channel assigned thereto and thus needs
of the secondary scrambling code sets corresponding to the
one primary scrambling code and one secondary scrambling 5o 512 primary scrambling codes is composed of M secondary
code.
scrambling codes. In this structure, if a cell uses one of the
Referring to FIG. 8, once an initial value for the primary primary scrambling codes then secondary, scrambling codes
scrambling code is applied to a first shift register 840 having
belonging to the secondary scrambling code group corre18 upper shift registers and a second shift register memory
sponding to the primary scrambling code will be used when
845 with 18 lower shifter register, the 0-th register values of55 the secondary scrambling codes need to be used. As shown
the first and second shift register memories 840 and 845 are
in FIG. 9, once a primary scrambling code is selected, the
fed into an adder 810. The output of the adder 810 is a
secondary scrambling codes corresponding to the primary
primary scrambling code. The 18 register values %[’ of the scrambling code are generated by the adding cyclically
first shift register memory 840 are fed into a masking section shifted first m-sequences and the second m-sequence. Here,
820. Meanwhile, the 18 register values %[’ of the second 60 the secondary scrambling codes are generated through applishift register memory 845 are fed into a masking section cation of mask functions to the sequences in the first shift
825. Then, the masking section 820 masks the input values
register memory. This method is adapted to a scrambling
from the first shift register with a mask function k~ (i.e., code generator of a transmitter as illustrated in FIG. 10,
Z(kixai)) and outputs the masked values to an adder 815 for
which concurrently generates one primary scrambling code
generating the first secondary scrambling code. The masking 65 and multiple secondary scrambling codes.
section 825 masks the input values from the second (lower)
Referring to FIG. 10, the first m-sequence generator 1050
shift register with a mask function s~ (i.e., Z(s~xa~)) and comprises a first shift register memory 1040 (with registers

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0 to 17) and an adder 1010 for adding the outputs of the
The binary sequence corresponding to x~3+xg+x2 is
000010001000000100 which is the mask code needed to
registers 0 and 7. The second m-sequence generator 1060
cyclically shift the m-sequence 31 times.
comprises a second register memory 1045 (with registers 0
The delays 1022 to 1024 and 1020 delay the I-channel
to 17) and an adder 1015 for adding the outputs of the
registers 0, 5, 7 and 10. The scrambling code generator 5 signals for a predetermined number of chips to generate
Q-channel scrambling code signals.
shown in FIG. 10 comprises the two m-sequence generators
As described above, the second embodiment of the
1050 and 1060, a plurality of masking sections 1000 to 1005,
present invention generate scrambling code groups shown in
a plurality of adders 1032 to 1034 and 1030, and a plurality
FIG. 9 and only uses one gold code generator, masking
of delays 1022 to 1024 and 1020. The first shift register
10 sections 1000 to 1005 and adders 1022 to 1034.
memory 1040 stores a predetermined register initial value
Now, a description will be given to an operation of the
"ao" and the second shift register memory 1045 stores a
present invention as constructed above.
predetermined register initial value "bo’. The shift register
Once an initial value for the primary scrambling code is
memory 1040 and 1045 can store 18 binary values (bits or
applied to the first and second shift register memories 1040
symbols) "ai" and "hi" (0=<i=<17). The two m-sequence
15 and 1045 each having 18 registers, the 0-th register values
generators 1050 and 1060 generate respective serial output
of the first and second shift register memories 1040 and 1045
sequence bits according to each generation polynomials at
are fed into the adder 1030 and the 18 register values "a~" of
every period of the input clock (not shown). The second
the shift register memory 1040 are fed into the first to N-th
embodiment of the present invention uses a gold code length
masking sections 1000 to 1005 in order to generate 1 to N
of 38400 symbols to generate scrambling codes. Thus, the
cyclically shifted sequences of the first m-sequence. Then,
shift register memories 1040 and 1045 may be reset to the 20 the first masking section 1000 masks the input value(a~)
initial value when each of the register memories 1040 and
from the first (upper) shift register memory 1040 with a
mask function k~i for generating the first secondary scram1045 outputs a sequence having a length of 38400 symbols.
bling codes (i.e., Y(kl~xa~)) and outputs the masked value(ai)
The first m-sequence generator 1050 generates the first
to the adder 1032. The N-th masking
m-sequence using the register memory 1040 and the adder 25 input value(a~) from the first (upper)section 1005 masks the
shift register memory
1010 which is a binary adder that adds the binary values
1040 with a mask function k:V~ for generating the N-th
from the registers 0 and 7 of the register memory 1040 and
secondary scrambling codes (i.e., E(k:V~xa~)) and outputs the
outputs the sum into the register 17. The register 0 of the
masked values to the adder 1034. At the same time, the adder
register memory 1040 sequentially outputs binary values
1030 sums the output bits from the 0-th registers of the first
that form the first m-sequence during every period of the
input clock. The masking sections 1000 to 1005 store mask 3o and second shift register memories 1040 and 1045. The
generated output signals are immediately delayed at the
code values (kl~ to k~) for generating cyclical shifts of the
delay 1020. The adder 1032 sums the output bits from the
first m-sequence by a predetermined number of chips. The
first masking section 1000 and the 0-th shift register of the
cyclical shifts are achieved by multiplying the mask code
second shift register memory 1045. The output signals are
values by the register value "a~" of the first shift register
memory 1040, as expressed in the following equation: 35 immediately fed into the delay 1022. Thereafter, the 0-th and
seventh register values of the shift register memory 1040 are
Z(KL~xa~). The resulting values are provided to the adders
added at the adder 1010 and the adder 1010 outputs the sum
1032 to 1034, respectively. In the preferred embodiments of
to the seventeenth register, as the left-sided values are
the present invention, each of the mask code values (kli to
shifted to the right side by one and the utmost left-sided
k:V,.) creates a new sequence which is a first m-sequence
register is newly filled with the output value of the adder
cyclically shifted 1 to N times. Thus, each of the mask code 4o 1010. The 0-th, fifth, seventh and tenth register values of the
values is determined by the desired number of cyclical
shift register memory 1045 are added at the adder 1015, and
shifting.
the adder inputs the sum into the seventeenth register of the
The adder 1030 adds the 0-th register values of the first
register memory 1045 as the left-sided values are shifted to
and second shift register memories 1040 and 1045 to genthe right side by one to fill the utmost left-sided register (i.e.,
erate a scrambling code, which becomes a primary scram- 45 the seventeenth register) with the output value of the adder
bling code. The adders 1032 to 1034 each adds one bit
1015. This procedure is repeated to generate multiple scramgenerated from the masking sections 1000 to 1005 to one bit
bling codes.
generated from the second shift register memory 1045,
FIG. 11 is a diagram showing a scrambling code generator
respectively, to generate I-channel scrambling code signals.
of a receiver for concurrently generating one primary scramHere, the output from the adder 1030 is used as the primary
scrambling code and the scrambling codes output from the 50 bling code and one secondary scrambling code. The embodiments shown in FIGS. 10 and 11 can be used either in a
adders 1032 to 1034 can be used as secondary scrambling
transmitter or a receiver.
codes that corresponds to the primary scrambling code. The
The receiver according to the second embodiment of the
following is an example of possible mask values (k~ to K"~):
present invention has only to use one secondary scrambling
k~ (000000000000000010), k2~ (000000000000000100),
k3i (0000000000000001000) . . . By controlling the mask 55 code and thus needs only one masking section 1100.
Referring to FIG. 11, once an initial value for the primary
values, other primary and secondary codes can be generated.
scrambling code is applied to a first shift register memory
The following example shows how to obtain a necessary
mask code to cyclically shift a m-sequence -n- times. In
1140 having 18 registers and a second shift register memory
general, divide x" by the generation polynomial for the 1145 with 18 registers-, the 0-th register values of the first
m-sequence (i.e., x"/l(x)) and take the remainder of the and second shift register memories 1140 and 1145 are fed
60
division to form the mask code. For example, if a mask code
into an adder 1120. The 18 register values "ai" of the first
that cyclically shifts 31 times is desired, take x and divide shift register memory 1140 are fed into the masking section
it by f(x)~x 18. 7x +1 the generation polynomial and find the
to
1100 in order to generate a cyclically shifted m-sequence.
remainder which cannot be divided further. The final
Then, the masking section 1100 masks the input values(a,)
remainder is xl3+Xg+X2 as shown by the following:
65 from the register memory 1140 with a mask values k~ for
generating the first secondary scrambling codes (i.e., Y(k,x
a,)) and outputs the masked values to an adder 1125. The

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adder 1120 sums the output bits from the 0-th registers of the
4. The method of claim 1, wherein 1 <L<M, where M is a
first and second shift register memories 1140 and 1145. The
total number of secondary scrambling codes per primary
output signals of the adder 1120 are immediately delayed at
scrambling code.
a delay 1130. Meanwhile, the adder 1125 sums the output
5. The method of claim 1, wherein the masking step is
bits from the masking section 1100 and the 0-th shift register 5 expressed by Z(k~xa~).
of the second shift register memory 1145 and outputs the
6. The method of claim 1, further comprising:
sum to a delay 1135 immediately. Then, the 0-th and seventh
masking the first shift register values a~ with a second set
register values of the first shift register memory 1140 are
of mask values Kj to generate a fourth m-sequence,
added at the adder 1110, in which case the left-sided values
whereinj 0 to c-l; and
are shifted to the right side by one and the utmost left-sided 10 adding the fourth m-sequence and the second m-sequence
register is newly filled with the output value of the summer
to generate an Nt~’ secondary scrambling code associ1110. The 0-th, fifth, seventh and tenth register values of the
ated with the primary scrambling code;
second shift register memory 1145 are added at the adder
wherein, the masking step shifts the first m-sequence
1115, shifting the left-sided values to the right side by one
cyclically by N chips to generate an N~’ secondary
and newly filling the utmost left-sided register with the 15
scrambling code.
output value of the adder 1115. The mask values can be
7. The method of claim 6, wherein I<N<M, where M is
controlled by a controller_(not shown) when the receiver
a total number of secondary scrambling codes per primary
needs to generate other scrambling codes.
scrambling code.
The scrambling code generator of the second embodiment
2o 8. The method of claim 1, further comprising the step of
needs mask values stored in the masking section in order to
delaying at least one of the primary scrambling code and
generate the secondary scrambling code, i.e., it uses N mask
secondary scrambling code to produce a Q-channel compovalues to generate N scrambling codes. Accordingly, the
nent, wherein the primary scrmnbling code m~d secondary
structure of primary and secondary scrambling codes shown
scrambling code are I-channel components.
in FIG. 9 enables implementation of the scrambling code
9. A scrambling code generator, comprising:
generator of the transceiver structure shown in FIGS. 10 and 25
a first m-sequence generator to generate a first m-se11, which further includes only N mask functions with a
quence by using a plurality of first registers with first
quite little hardware complexity to generate multiple scramshift register values a~, wherein i 0 to c-1 and where c
bling codes.
is the total number of the first registers;
While the invention has been shown and described with
reference to a certain preferred embodiment thereof, it will 3o
a second m-sequence generator to generate a second
be understood by those skilled in the art that various changes
m-sequence by using a plurality of second registers
in form and details may be made therein without departing
with second shift register values bg, wherein j 0 to c-1
from the spirit and scope of the invention as defined by the
and where c is the total number of second registers;
appended claims.
a masking section to mask the first shift register values ai
35
with a first set of mask values K~ to generate a third
What is claimed is:
m-sequence, wherein i 0 to c-1 to generate a third
1. A method for generating a primary scrambling code, the
m-sequence;
method comprising the steps of:
a first adder to add the first m-sequence and the second
generating a first m-sequence from a first m-sequence
m-sequence
generator including first shift registers having first shift 4o a second adder toto generate a primary scrambling code; and
add the third m-sequence and the second
register values ai, wherein i 0 to c-1 and where c is the
m-sequence to generate a secondary, scrambling code,
total number of the registers;
wherein the masking section shifts the first m-sequence
generating a second m-sequence from a second m-secyclically by L chips to generate an L**’ secondary
quence generator including second shift registers havscrambling
ing values bj, wherein j 0 to c-l, and where c is the 45 bling code. code associated with the primary scramtotal number of the registers;
10. The scrambling code generator of claim 9, wherein the
masking the first shift register values ai with a first set or
primar,v scrambling code is one of a plurality of primary
mask values Ki, wherein i 0 to c-1 to generate a third
scrambling codes and a K**’ primary scrambling code is a
m-sequence;
5o ((K-1)*M+K)*~’ gold code, where M is a total number of
adding the first m-sequence with the second m-sequence
secondary scrambling codes per primar,v scrambling code
to generate a primary scrambling code; and
and 1<K<512.
adding the third m-sequence and the second m-sequence
11. The scrambling code generator of claim 10, wherein
to generate a secondary scrambling code;
the secondary scrambling codes associated with the K
wherein, the masking step shifts the first m-sequence
t~’ to (K’M+
primar,v codes.
cyclically by L chips to generate an Lt~’ secondary55 K)~, gold scrambling code are ((K-1)*M+K+I)
scrambling code associated with the primary scram12. The scrambling code generator of claim 9, further
bling code.
comprising:
2. The method of claim 1, wherein the primary scrambling
a second masking section to mask the first shift register
code is one of a plurality primary scrambling codes and a Kt~’
primary scrambling code is a ((K-1)*M+K)~’ gold code, 60
values a~, with a second set of mask values K~, wherein
j 0 to c-l, to generate a fourth m-sequence; and
where M is a total number of secondary scrambling codes
per primary scrambling code and 1<K<512.
a third adder to add the fourth m-sequence and the second
m-sequence to generate an N-th secondary scrambling
3. The method of claim 1, wherein the secondary scramcode associated with the primary scrambling code,
bling codes associated with a K~’ primary scrambling code
are from ((K-1)*M+K+I)~’ to (K*M+K)~’ gold codes, 65
wherein the second masking section shifts the first m-sewhere M is a total number of secondary scrambling codes
quence cyclically by N chips to generate the N
per primary scrambling code and 1<K<512.
secondary scrambling code.

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13. The scrambling code generator of claim 9, wherein the
a first m-sequence generator to generate a first m-semasking section shifts the first m-sequence cyclically by
quence;
masking the first shift register values ai in accordance with
a second m-sequence generator to generate a second
Z(K, xa,).
m-sequence; and
14. The scrambling code generator of claim 9, wherein the 5
at least one adder for generating a ((K-1)*M+K)**’ Gold
first m-sequence generator cyclically shifts the first shift
code as a K*~’ primary scrambling code by adding a
register values and the second m-sequence generator cycli(((K-1)*M+K)-l)-times shifted first m-sequence and
cally shifts the second shift register values.
the second m-sequence,
15. The scrambling code generator of claim 9, wherein the
wherein K is a natural number and M is a total number of
first m-sequence generator adds predetermined shift register 10
secondary scrambling codes per one primary scramvalues of the first shift registers based on a first generating
bling code.
polynomial of the first m-sequence, right shifts the first shift
register values a, of lhe first shift registers, and replaces the
26. The apparatus of claim 25, wherein the secondary
first register value ac_1 with the result of the addition of the
scrambling codes of the Kt~’ primary scrambling codes are
predetermined register values.
15 the ((K-1)*M+K+I)t~’ through (K*M+K)~’ Gold codes.
16. The scrambling code generator of claim 9, wherein the
27. The apparatus as claimed in claim 26, wherein K is a
first m-sequence generator adds a first shift register value ao
primary scrambling code number and < <
1 =K=512.
with a first shift register av to form a next first shift register
28. The apparatus as claimed in claim 25, wherein the first
ac_l.
17. The scrambling code generator of claim 9, wherein the m-sequence generator comprises a plurality of first registers
second m-sequence generator adds predetermined shift reg- 2o with first shift register values a,, wherein i=0 to c-1 and
where c is the total number of the first shift registers, and the
ister values of the second shift registers based on a second
scrambling code generator further comprising at least one
generating polynomial of the second m-sequence, right
masking section for generating the n-times shifted first
shifts the second shift register values bj of the second shift
registers, and replaces the second register value b~_ 1 with the
m-sequence by masking the first shift register values a, with
result of the addition of the predetermined register values. 25 mask values Ki, where i=0 to c-1.
lg. The scrambling code generator of claim 9, wherein the
29. The apparatus as claimed in claim 28, wherein the
second m-sequence generator adds a second shift register
masking is performed according to: Z(Kixa,).
value bo with a second shift register value bs, b> and a
30. The apparatus as claimed in claim 25, wherein the
second shift register value b~o to form a next second shift
primary scrambling code and secondary scrambling code are
register value b~_~.
30
19. The apparatus of claim 9, further comprising a means I-channel components and the apparatus further comprises a
means for delaying at least one of the primary scrambling
for delaying at least one of the primary scrambling code and
codes and secondary scrambling code to produce Q-channel
the secondary scrambling code to produce Q-channel comcomponents.
ponent, wherein the primary scrambling code and the sec31. A method for generating scrambling codes in mobile
ondary scrambling code are I-channel components.
35
20. A method for generating scrambling codes in mobile communication system having a scrambling code generator,
comprising the steps of:
communication system having a scrambling code generator,
generating a first m-sequence;
the method comprising the steps of:
generating a ((K-1)*M+K)**’ gold code as a K**’ primary
generating a second m-sequence; and
scrambling code, where K is a natural number and M 4o generating a ((K-1)*M+K)~’ Gold code as a K~’ primary
is a total number of secondary scrambling codes per
scrambling code by adding a (((K-1)*M+K)-l)-times
one primary scrambling code; and
shifted first m-sequence and the second m-sequence,
generating ((K-1)*M+K+I)**’ through (K*M+K)**’ gold
wherein K is a natural number and M is a total number of
codes as secondary scrambling codes associated with
secondary scrambling codes per one primary scramthe K**’ primary scrambling code,
bling code.
45
wherein an L*~’ Gold code is generated by adding an
32. The method as claimed in claim 31, further compris(L-1)-times shifted first m-sequence and a second
ing generating ((K-l) M+K+I) to (K*M+K)*~’ Gold codes
m-sequence.
as secondary scrambling codes corresponding to the K~*’
21. The method as claimed in claim 20, wherein K is a primary scrambling code.
primary scrambling code number and 1-<K-<512.
5o 33. The method as claimed in claim 31, wherein K is a
22. The method as claimed in claim 21, wherein the first primary scrambling code number and < <
1 =K=512.
m-sequence is generated from a first shift register memory
34. The method as claimed in claim 31, wherein the first
having a plurality of first shift registers with first shift
register values a,, wherein i 0 to c-1 and where c is the total m-sequence is generated from a first shift register memory
number of the first registers and the (L-1)-times shifted first having a plurality of first shift registers with first shift
m-sequence is generated by masking the first shift register 55 register values a,, wherein i=0 to c-1 and where c is the total
number of the first registers and the n-times shifted first
values a, with mask values K,, where i 0 to c-1.
23. The method as claimed in claim 22, wherein the m-sequence is generated by masking the first shift register
values a, with mask values K,, where i=0 to c-1.
masking is performed according to:
35. The method as claimed in claim 34, wherein the
24. The method as claimed in claim 20, wherein the
generated primary scrambling code and secondary scram- 60 masking is perlbrmed according to: Y(Kixai).
36. The method as claimed in claim 31, wherein each
bling code are I-channel components and the method further
scrambling code is used as an I-channel component and a
comprises delaying at least one of the primary scrambling
Q-channel component, corresponding to the I-channel comcode and secondary scrambling code to produce Q-channel
ponent, is generated by delaying the I-channel component
components.
25. An apparatus for generating scrambling codes in 65 for a predetermined time.
mobile communication system having a scrambling code
generator, comprising:

APLNDC-WH-A 0000018133