Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 2

EXHIBIT C

Dockets.Justia.com

14.

afnu

I
Serial NO. 08/179,926
PART 111: DETAXL OF ACTION

1.

The applicants are reminded to indicate all related co-pending

applications in the cross-references to related applications section of the specification. It appears in the PTO-1449 cited by the applicants and received at the office on May 9, 1994 that a related co-pending application serial no. 08/180,023 indicated earlier in this application. 2. Claims 2-13 are rejected under 35 U.S.C. was not

5 112, second

paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. The following language lacks of proper antecedent basis: In claim 2, line 5, "the next instruction". It is not clear what particular next instruction the claim refers to.

In claim 3, line 2, "the instruction". It is not clear what
particular instruction the claim refers to. In claim 6, line 3, "the execution unit". Other dependent claims not specifically cited above are also rejected because of the deficiency of their respective parent claims. The examiner further suggests the applicants to include line. numbers for each claim instead of for the whole page because errors

Serial NO. 08/179,926 and corrections can be located much easier especially in the long claims. The examiner further suggests changing '*the" to --said-whenever possible for more clearly identifying the referenced object elements in the claims. For example: in claim 1, line 2, "the CPUtf, line 4 , "the first", line 6, "the second", "the first", line 7, "the second", line 8, "the first", "the second", line 9, "the decoded", "the first", line 10, "the second", line 11, "the select", line 12, "the first", "the second", line 13, "the CPU". The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
3.

A person shall be entitled to a patent unless

--

(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this Country, more than one year prior to the date of application or patent in the United States.
4.

Claims 1-4 are rejected under 35 U . S .C.

§

102 (b) as being

clearly anticipated by Ueda et a1 (hereafter Ueda), U.S. pat. no.
4,821,187. 5.

Ue'da teaches the claimed invention, a system capable of In
'

executing two different instruction sets (see abstract).

particularly, the system comprises two separate decoders for decoding first and second set of instructions respectively,
3

Serial No. 08/179,926 execution units for executing the decoded first and second instructions, control units for controlling switching execution of first and second instruction sets (see summary).
6. The following is a quotation of 35 U.S.C. 5 103 which forms the basis for all obviousness rejections set forth in this Office action:
A

patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.

Subject matter developed by another person, which qualifies as prior art only under subsection (f) or (g) of section 102 of this title, shall not preclude patentability under this section where the subject matter and the claimed invention were, at the time the invention was made, owned by the same person or subject to an obligation of assignment to the same person. This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 5 103, the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 C.F.R. § 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of potential 35 U.S.C. 5 102(f) or (9) prior art under 35 U.S.C. 5 103.
7.

8.

Claims 1-20 are rejected under 35 U.S.C. 5 103 as being

unpatentable over de Nicolas et a1 (hereafter Nicolas), U.S. pat.

no. 5,167,023.
4

Serial NO. 08/179, 926

9.

As to claims 1-4, Nicolas teaches a system substantially as

claimed for emulating the execution of second set of instructions (target instructions) which are not directly executable by the host system (see abstract). In particularly, the system is capable of directly executing native RISC instructions in a normal mode and executing CISC target instructions in an emulation mode. Nicolas describes a number of prior art systems, one of which was implemented the instruction execution emulation with hardware (see background). It would have been obvious to one of ordinary skill in the art at the time of the invention that such hardware emulation would have included a second decoder for decoding target instructions, and other control units for controlling the emulation mode for executing target instructions.

10. As to claims 5-10, Nicolas particularly teaches emulating the
execution of CISC instructions using software where each CISC instruction execution is emulated by executing a routine comprising a plurality of individual RISC instructions, and where the emulation background) mode

.

is

initiated by

an

interrupt

signal

(see

Nicolas further teaches using a translation look-

aside buffer (TLB) for providing dynamic address conversion for executed instructions (see summary). normal and emulation modes.

It is noted that the TLB

would be utilized in executing native RISC instruction in both. Nicolas does not particularly teach
5

incorporating both hardware and software emulation in the same machine as claimed, It would have been obvious to one of ordinary skill in the art at the time of the invention to realize such software and hardware combination because it would bring the advantages of both techniques into the system, e.g. the inexpensive and flexibility of the software emulation and the speed of the hardware emulation. 11. As to claim 11, it would have been obvious to one skilled in the art to modify the TLB when additional instructions are added to the emulation instruction sets so that the TLB could operate properly.

12. As to claims 12-13, it would have been obvious to one skilled
in the art to switch from the normal mode to the emulation mode in response to signal from the host execution unit or from a reset signal.
13.

Claims 14-20 are rejected for the same rationales set forth

above for claims 1-13.
140

All Pending claims are rejected in this office action,

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Serial No. 08/179,926
15.

The following references are cited by the examiner as of Wilburn et all U.S. pat. no. 4,633,417: Kashiwagi, U.S. pat. no. 4,780,819: emulator for non-fixed

general interest. a.
b.

instruction set VLSI devices. emulator system utilizing a program counter and a latch coupled to an emulator memory for reducing fetch time of instructions stored in the emulation memory. c. d. e. Simpson, U.S. pat. no, 4,794,522: Adachi, U.S. pat. no. 4,812,975: method for detecting modified object code in an emulator. emulation method. extended floating source instruction Mitchell et all U.S. pat. no. 4,841,476:

point operations supporting emulation of execution. f. g. Nakayama, U.S. pat. no. 4,942,519:

coprocessor capable of emulator assist unit

checking address mapping. Cooper et a l , U.S. pat. no. 5,077,657: which forms addresses of user instruction operands in response to emulator assist unit commands from host processor.

h.

Bresford et a l l U.S. pat. no. 5,230,069:

apparatus and method

for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system. i. Jen et all U.S. pat. no. 5,291,586: hardware implementation of complex data transfer instruction.

7

Serial No. 08/179,926 16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to V. Vu whose telephone number is [phone]. Any inquiry oE a general nature or relating to the status of this application should be directedto the Group receptionist whose telephone number is [phone].

V. vu Art Unit 2315 6/15/94

8

U.
EXRMINER

DATE

* A copy of this reference i s not being furnished

with this office action. (See Manual of Patent Examining Procedure, section 707.05 (a).)