Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 4

EXHIBIT E

Dockets.Justia.com

UNITED STATES DEPARTMENT OF COMMERCE Petent and Trademark Office
Address : COMMISSIONER OF PATENTS AN0 TRADEMARKS Washington. D.C. 20231

la8/ 179,926

0 / 1 1 /94 1

RLOMGREN

STIJART T. AiJVINEN 42'3 2 C I H AVE. SANTA C:RiJZ, CA 35062
DATE MAILED:

11/16'g@

This eppllcation has besn m k w d

Re6pmstve to mmuntcatcationllled on

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Eiaelon la made flnal. -I

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c] Notice of Art Cited by Applicant, PT0-1449. c] infonnstmon How to Effeot Dr&ng Chaw-, PTO-1474.

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Notlce re Patent Drawlno, PTO-848. Notice of Informal Patant ApPllCatlOn, Form PTO-152.

are pending In the appilcatlon.
Of the above, ckima are w i t h d r m from consideration. have been cancelled.

CLtllma
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are allowed. are r e w e d . are objected to. are sublect to reatrtctlon or B(BCt1on requirement. filed with Informaldrslwtngs under 37 C.F.R. 1.85 which are acceptablefor examlnatlon purposes,

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o ~ e of wbatitute drawings hnve been, recplved on d Under 37 C.F.R. 1.84 thwe drawings .tcsplRMe. c] not occsptable(aw exptanation or Notlca re Patent Drawing, PTO-848).
has (have) bsen

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examiner. c] diupprowd by the sxMlfnw (saeexplanation).
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approved.

dieapproved (we exphation).

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A d n o w m a n t is made of the claim fof prlwlty under U.S.C.119. The certlflad copy has

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c] been filed In parent wplkatlon, wrlal no.
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Sinca this appllceth @pearsto be in condition for allowance except for formal matters, prosecutionas to the merits IS closed in -dance with the under Ex parte (luayie, 1835 C.D. 11; 453 O.G. 213.

EXAMINER'S ACTION

/
Serial No. 08/179,926
PART i n : DETAXL OF ACTION

1.

This office action responds to applicants' amendment filed on

September, 20, 1994. Claims 1 - 2 0 remain pending.
2.

Claims 1-4, 14 and 18-20 are rejected under 35 W.S.C.

5 112,

first paragraph, as the disclosure is enabling only for claims limited to decoder capable of directly decoding a subset and not the entire non-native instruction set, See M.P.E.P. and 7 0 6 . 0 3 ( 2 ) .
3.
S S 706.03(n)

The specification clearly shows that only some and not all of

the non-native instructions can be directly decoded and executed by the decoder unit and the execution unit. While it is not clear how to design a decoder unit and an execution unit capable of executing both entire native and non-native instruction sets as claimed based on the disclosure of the invention, it is submitted that the design

of such decoder and execution units is not obvious to one skilled
in the art without further requiring undue experimentation because increas.e significantly. Thus, the complexity of the processor for performing such functions would the disclosure of the present invention is not

commensurate in scopes with claims 1-4, 14 and 18-20 because claims . 1-4, 14 and 18-20 fail to explicitly recite the limitation that

2

Serial No. 08/179,926 only a subset of the non-native instructions can be directly decoded by the decoder unit.
4.

The text of 35 U.S.C.

§

1 0 3 not cited here can be found in the

first office action.
5.
U.S.

Claims 1-5, 14-16 and 58-20 are rejected under 35 U.S.C.

§

103

as being unpatentable over Portanova et a1 (hereafter portanova), pat. no. 4,992,934 in view of Onishi, U.S. pat. no. 3,164,988.
As

6,

to claims 1-2,

Portanova teaches a system capable of In

executing both RISC and CISC instructions (see abstract).

particularly, the system comprises a core structure of a RISC computer, and an emulation unit using RISC routine for emulating the execution of CISC instruction (see summary). 29, line 60 The CISC emulation can be implemented with hardwired or firmware (see col

-

eo1 30,

line 12 and figures 9-10]. It is noted that

the hardware implementation of the CISC emulation would have required a modification to the RISC processor for providing the additional capability to decode and execute CISC instructions. Portanova does not specifically teaches using two separate decoder units for decoding RISC and CISC instructions respectively. The use of multiple decoder units for decoding different types of instructions is however well-known in the art. The use of multiple
3

Serial No. 08/179,926 decoders, each designated to decode certain type of instructions, is desirable because it allows a simple and efficient design of the instruction decoder, instructions and Onishi teaches a processor comprising two second decoder
or

instruction decoders, the first decoder for decoding normal the decoding branch instructions (see abstract). reduced (see summary). decoders. Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Portanova's system to utilize two instruction decoders as taught by Onishi for decoding RISC and CISC instructions respectively. This is because the use of separate instruction decoder units for RISC and CISC instructions allows more simple and efficient design of the decoder units. 7. By using the second instruction

decoder, the decoding sequence of a branch instruction can be It is noted that a selector is obviously needed to select decoded instructions from the first and second

As to claims 3-4, it would have been obvious to one skilled in

the art to utilize an execution mode register for indicating the execution of native and non-native instructions.
8.

As to claim 5,

Po'rtanova further teaches that the CISC

emulation unit can also be implemented by using.both hardware and
4

Serial NO. 08/179,926 software in which some CISC instructions would be directly decoded and executed by the execution unit and the execution of the rest of CISC instructions is emulated by using RISC routines (see col 30, lines 13-28 and figure 11). Thus, it would have been an obvious engineering design choice to one of ordinary skill in the art at the time of the invention to utilize both software and hardware implementation to emulate CISC instructions on a R I S C computer. The implementation of both software and hardware approaches could have been motivated because of the combined advantages' of both techniques, i.e. the simpleness and flexibility of the software emulation approach and the speed of the hardware emulation approach.
9.

Claims 14-16 and 18-20 are rejected for the same rationales

set forth above for claims 1-5 10. Claims 6-13 and 17 are rejected under 35 U.S.C. 5 103 as being unpatentable over Portanova and Onishi as set forth above for claims 1-5, 14-16 and 18-20 further in view of Bullions, I11 et al, (hereafter Bullions) U.S. pat. no. 4,456,954.
11. As to claims 6-7, 9-10 and 17, neither Portanova nor Onishi

teach using a translation look aside buffer

(TLB).

Bullions

,

teaches using a TLB for translating a virtual address to a physical 5

Serial No. 08/179,926 address for both host and guest instructions (see abstract). In

particularly, a TLB is utilized to address emulation host routine for a guest instruction. Bullions further teaches that a miss in
TLB also triggers a change of execution modes, i.e. from host to

guest (see summary. and claims).
12. As to claim 8, Bullions also teaches switching the execution

mode in response to an interrupt (see col 13, line 18-62}.
13. As to claim 11, Bullions further teaches using a special

instruction to initiate the software routine emulation and reload the TLB (see col 12, lines 63-67).
14. As to claims 12-13, it would have been obvious to one skilled

in the art to reset the system execution mode to a normal operation in response to a system reset signal.
15. All pending claims are rejected in this office action.

Applicants' arguments filed on September 23, 1994 have been fully considered but are moot in view o f new grounds of rejection.
16. As to the remarks, applicants argue that none of the cited

teach or suggest the two instruction decoder and the selecting. means f o r selecting the decoded instruction from the two decoders. 6

Serial No. 08/179,926 It is submitted that the newly cited art, Onishi, now clearly suggests the implementation of two instruction decoders in the processor. The applicants further assert that the hardware implementation
of prior art to emulate the guest instructions only suggests the

use of a "co-processortt for executing the guest instructions and not the claimed invention which utilizes the same execution unit for executing both host and guest instructions. The examiner disagrees. It is submitted that the use of either software or hardware approach or the combination of both to implement instruction emulation is well-known in the art (see Portanova). To the extent of the hardware implementation, whether the whole or part of the emulation unit is designed t o be integrated to or separated from the host processor is merely a design o f choice in which each design approach can be viewed as a tradeoff and balance among factors such as speed, cost and flexibility. Onishi is a clear evidence of a system employing It is partly duplicated hardware resources where a separate instruction decoder is provided to decode only branch instructions. noted that some prior art systems even go a step further to provide a complete branch instruction execution unit for decoding and executing only branch instructions to further reduce execution delay of a branch instruction.

7

Serial No. 08/179,926 Thus, the inlplementation of two instruction decoders or decoding RISC and CISC instructions respectively and the selecting means as claimed would have been obvious to one skilled in the art in light of the cited arts' teachings and discussions above.
17.

The following references are cited by the examiner as of Tanenbaum, "Structured Computer Organization", Prentice-Hall

general interest. a. Inc. 1984, p. 10-12.
18, Any inquiry concerning this communication or earlier communications from the examiner should be directed to V. Vu whose telephone number is [phone].
Any inquiry of a general nature or relating to the status of this application should be directed to the Group receptionist whose telephone number is ( 7 0 3 ) 305-9600,

Art Unit 2315 11/8/94

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NOTICE OF DRAFTSPERSOWSPATENT DRAWING REVIEW

n o Draftpersons review all orighaHy Neddrawingsregardless of wbetber they are deaignated as formal or informal. Additionally,

patent Examinerswill review the &wings for compliance with the regulations. Direct telephone inquiries concerning this review IO the Drawing Review Branch, 703-305-8404.
Modirrcdrams. 37 CFR 1.84@)(5) __ M d f e forma ofconsouclion m s bc shown in scpararc vicws. oiid ut

below. Thc Extuntax will raRlht aubmWmdocar.e

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8. ARRANG&WXT OF VIEWS. 37 CT-R 1.84(1) View placed upon anoiher view 01 within 0 u U i of another.

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__ Words do 1w1 appcar in a hcrlmlal, 1cft-m-rightfashion when

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poge is either upright or c m d so that IUtop becomes the right uc I side, cxcept for graphs. FigW

9. SCALE. 37 CFR 1.84(k) %IC, largc cnough to show mcchanlsrn withour crowding not when drawing is rcduccd in s i x to two-thirds in reproduction

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P not pcrmittcd. Ag(r) ElcmcnU of samc vicw not in proponion (0cach oha. Fig@)

10. CHARACTER OF LINES. NUMBERS,& LETTERS. 37 CFR 1.84(1) Lines, nurntsrs & letters not unifwmly thick and wcll defined. c i m . dmblc, and b i d (cxocpl for color drawings). Rg(S)

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I I. SHADWG. 37 CFR 1.84(m) Shading used fm &a than shqx of aphalcal, cylindrical, and arnical elcmcnts of an object. or fw (lac pans.

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Solid hlack shading afeas not permitted. Fig@)

12. NUMBERS. LITERS. & REFERENCE CHARACTERS. 37 CFR

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bnckccrs. invmcd conmas, or cncloscd within ouUinw, 37 CFR 1.84(p)o) Fig(s) __ Numhen and rcfcnnn CharaCtCrs not odcnccd in same diraion as chc v i w . 37 CFR 1.84@)(1) Fig@) English dphakt ntx used. 37 CFR 1.84[~X2) Fig(s)-Nunibcrn. lctlcn. md rcfcrrncc cliar&ccn do not mcaswc at least .32cnr (1/8 inch) in hcipbr. 37 CFRfp)(S) FigW
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Numhcrs aid rcfcrcncc r h 8 i - x ~ ~ plain and legiblc. 37 CFR not 1.84(pt(l) Figts)

13. LEAD LINES. 37 CFR 1.11410) , __ Lcaj l i s c m s cach other. Fig@) ._ k d lines ndwing. Fipts) a __ Lcad lhc9 not as short as possibic. Fig($)

sufficiently. Fi@) __ Hatching ti(N ul substantial anglc In sumlullding&<CI lincs. Figw

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not rpxaf
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TO SEPARATE. HOLD TOP AND BOTTOM EDGES, SNAP-APART A N 0 DISCARO CARBON

NOTICE OF R E F E R E N C E S CITED

KAMINER

DATE

4- $y g-.

A copy of this reference is not being furnished with this office action. (See Manual of Patent Examining Procedure, section 707.05 (a).)