Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 7

EXHIBIT H

Dockets.Justia.com

OFFICE

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In re application of
BIomgren et al.
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Serial No. 08/179,926 Filed: 1/11/94 For: Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode

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Examiner: V. VU Group Art Unit: 2315

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Hon. Commissioner of Patents and Trademarks Washingron, DC 20231
Sir:

ER 37 C.F.R. 5 1.16 111

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In response to the third office action mailed 4/5/95, Applicant requests that this amendment be entered to place the application in a condition for allowance or a better form for appeal:
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Inthedaims:

G--- Please amend claim L as follows: 8

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18. (three times amended) A microprocessor for executing instructions belonging to a

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reduced instruction set computer (RISC) instruction set and for executing instructions

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belonging to a complex instruction set computer (CISC) instruction set, said microprocessor comprising: RISC instruction decode means, for decoding instnrctions belonging to said

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RISC instruction set; CISC instruction decode means, for decoding only a subset of instructions
belonging to said CISC instruction set; mode register means for indicating a current operating mode of said microprocessor; enable means, coupled to said RISC instruction decode means and said CISC

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instruction decode means, for enabling said decoding of instructions belonging to said RISC instruction set or belonging to said CISC instruction set, said enable means responsive to said current operating mode of said microprocessor; and an execution unit, coupled to said [fist] BISC. instruction decode means and said [second] CSG instruction decode means, for executing instructions belonging to

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said [fist] BISL: instruction set and instructions belonging to said [second] instruction set, whereby instructions from said RISC instruction set and instructions from said CISC instruction set can be executed by said execution unit,

- ---c .,

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Under 35 USC 0 103,claims 1-5, 14-16, 18-20were rejected as obvious over and

Portanova a al (US Pat. No. 4,992,934)in view of

(U.S. Patent No. 3,764,988). Claims 6-13and 17 were rejected under 35 USC 0 103 as obvious over

portanoVa in view of anishi as set forth for claims 1-5, and further in view of V W.S. Patent No. 4,456,954). claims were thus rejected. All
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Claim 18 has been amended to remove an antecedent problem found by Applicant.

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New Prior Art Cited
Two new references have been cited in the f i f action. These references were used as showing the background level of skill in the arl. The Examiner has not raised the issue 5 of the background skill level until the fml action. Thus the background skill level is a new issue for the final rejection. Applicant believes that these new references are improperly being introduced at the final rejection under the new argument of "background skill ievel" since the primafy references clearly do not teach hardware execution of two instruction sets, or part of a second instruction set.
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Applicant requests that the f n laction be withdrawn as being premature due to the ia introduction of two new references and the introduction of the new issue of background skill level.
Explicit Teaching
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Suggesffon Lacking fmm

The references clearly do not teach hardware execution of two different instruction
sets. The Examiner agrees that hardware execution of two instruction sets is not

@age 7, fist paragraph of action) but is However, Applicant is unable to f i d any language in the cited page (col29 col30) of the
I

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reference containing this suggestion. In the prior amendment, Applicant discussed each of "prior-art" Figures 9, 10, 11, and 12 in the cited page, and was not able to find any such suggestion or teaching that a hardware pipeline could execute two native instruction sets. Instead these can be used to show how ' RISC processor a CISC instruction set for several well-known CISC architectures, such as 68000,VAX, 23370.

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Portanova Teaches Away Design RiSC Ist, then code CiSC

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Portamvaclearly Le&&uwy from hardware execution of both RlSC and CISC when
he teaches a two-step process:

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hinted 5122/95

1.)

The RISC hardware is frrst built

for CISC.

2.) Then the software emulator is written for any of the CISC architectures of Figures 9-12 (col30, l i e s 39-64>.

Hardware execution would R E Q U that CISC be considered when the hardware is ~
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designed. Designing CISC hardware with RISC hardware would slow down the design process, and nullify I3zm.u~ ' advantage stated at col30.

Request for ~ ~ e n ~ of Basis for S ~ $ ~ e s ~ i o ~ c~~on
If such language suggesting hardware execution of fwo instruction sets exist, Applicant
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requests that Examiner explicitly point out

and y&JAm it occurs in,

rather than broadly referring to a page with four prior-art figures. This will help define the issues for appeal and ensure that Applicant and Examiner are not "discussing two completely different cases" (PTO Day 1994, pages 357-9). Something in the Prior art must suggest the desirability of making the combination (Uniroyal,Inc. v. R a i n 15

Wiley Cotp., 837 F.2d at 1050-51,5 USPQ2d at 1438). The claimed invention must not be used as a blueprint.

Examiner objected to Applicant's thorough and specific analysis of the references,

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stating that

"Applicants attempt to show non-obviousness by piecemeal analysis of the

references. Applicants are reminded that one cannot show non-obviousness by attacking references individually where, as here, the rejections are based on combinations of references." @age 6).

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Applicant strongly disagrees. When the &aminer cites a portion of a reference as

teaching a claim efemnt, the Applicant can show that such reliance is in error. For example, if an Examiner states that reference P teaches X while reference Q teaches Y, then Applicant can properly argue that reference P does not, in fact, teach X.

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priated 5/22/95

In the present case,Examiner has relied on Portanovafor a suggestion of hardware
execution of two instruction sets. Examiner states that "Partanova,however, clearly suggests that hardware implementationof CISC emulation could have been done as an alternative approach (see col29, line 60 - col 30, line X2)." Applicant can properly

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show that Examiner's reliance on the cited portion of the reference to be in error. Applicant has done this by a through analysis of this cited portion of lb&kx!a. Applicant may also show that it is improper to combine references, such as when a secondary reference solves a different problem (Zn Re Clay, 23 USPQ 2d 1058). Since

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Onishi solves the problem of branch decoding by splitting a decoder into two parts,

Applicant has pointed out that the branch decoder does not solve the problem of decoding two entirely different instruction sets, such as CISC and MSC. Both of

onishi's decoders merely decode different parts of a single instruction set.
Strained Co~bination R ~ f e ~ ~ c e ~ of

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fails to provide any detail of CISC hardware implementation, since only emulates CISC instructions with KISC instructions. Examiner has attempted to rely on brief prior-art descriptions in of well-known CISC architectures for CISC hardware execution. This attempt fails because

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teaches away by showing that the RISC hardware can be used to emulate ANY of these different CISC architectures by first designing generic RfSC hardware without regard

to CISC, and then writing CISC emulation code containing RISC instructions. This
speeds up his design time.

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Examiner also cannot rely on these brief prior-art descriptions because they fa2 to disclose the structure recited in Appliwt's claims. For example, having two instructions decoders (RISC and CISC) but only one execution unit is claimed by the elements of claim 18. However, Portanova does not disclose a CISC instruction decoder nor an execution unit capable of executing both RISC and CISC instructions.

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Printed $122195

is brought in as showing two instruction decoders, but this fails because

onishi's second decoder is merely a branch decoder, and not a decoder for a second
(CISC) instruction set.
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snishi, like

m, completely lacks any teaching or suggestion of an

"execution unit, coupled to said E,EC instruction decode means and said W instruction decode means, for executing instructions belonging to said E,EC instruction instruction set, set and instructions belonging to said whereby instructions from said RISC instruction set and instructions from said
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CISC instruction set can be executed by said execution unit." (claim 18, emphasis added).

., and have been added to further strain the Now combination of references. Examiner is using to suggest that software or
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hardware is merely a design choice. The two newly-cited references are used as "dirrther evidences of hardware ~ p l e m ~ nas opposed~lo sokware ~~io implementation". However, neither reference teaches or suggests the hardware claimei by Applicant, such as the execute unit receiving decoded RISC and decoded CISC instructions. A "design choice" is another way saying "obvious to try".
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Applicant has reviewed the two newly-cited references. is clearly directed to an extension of a single instruction set rather than a separate spspnd instruction set. b eLiL teach an "assist" that is attached to the main processor via a set of busses (col2, lines 40-45). Thus the 'assist" appears to be the co-processor embodiment with a new name. Co-processors execute in hardware extensions of a single instruction set.

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also teach a single instruction set that is partitioned into two or more
subsets, each possibly implemented in a different chip or emulated by software. His Figure 3 again shows a co-processor embodiment connected to a bus.

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In contrast, Applicant's claim 1 recites "two separate instruction sets", and claim 18
recites a RISC and a CISC instruction set, Claim 1 clearly disallows a mere extension of a single instruction set by stating: "said fvst encoding of instructions independent from said second encoding of instructions". Mere extensions of instruction sets must have dependent enccdings since otherwise one opcode could be used for two

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instructions. However, two separate instruction sets, such as RISC and CISC, will have one opcode with two different instructions. (Specification, page 25, lines 2-6.) Examiner a p p r s to be using these three new references to show that Portanova's RISC hardware can be modified to execute native CISC instructions. However, these

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newlycited references only show

g& that would have % m

. Also, these references show mere extensions to a single instruction set,
such as for floating point instructions. Thus, even if these references were used as secondary references in a non-final action, these references do not teach or suggest a single execute unit that executa both RISC and CISC instructions.

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Applicant believes that both parties agree that &maw does not aq&&m& hardware execution of both RTSC and CBC instruction sets. Portanovaemulates all CISC instructions with routina of RISC instructions. Examiner acknowledges that

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''brfxgi explicitly teaches an exemplary system that employs software
implementation of CISC emulation in which each guest CISC instruction is emulated by

a series of host RISC instructions." (page 4,lines 3-5, third action) Applicant
understands this statement to mean that Portanova explicitly teaches only RISC hardware execution and only CISC software emulation.

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ldenti~~affon Points of ~ i s a g for Appeal ~ ~ of ~~e

Examiner believes that

suggests hardware execution of CISC instructions in

an otherwise RISC processor. This

appears somewhere in col29-30.

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Applicant has been unable to find this suggestion and has requested that the Examiner specifically point out what he is relying on. Applicant asserts that the CISC embodiments labeled "prior-art" for Figures 9-12 are nothing more than old processors that can only decode and execute just one instruction set.

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' It is not reasonable that a prior-art VAX combined with i3Sma%$NSC emulating
CISC would suggest a single execute unit executing both RISC and CISC. Instead

Portanova clearly teaches software emulalion of CISC by RISC,so the CISC VAX
would b
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. Simple statements that software and

hardware are equivallent belittle microprocessor design and fail to teach or suggest a single RISC aad CISC execute unit. Examiner also asserts (page 4)that AppIicant's argument that Figures 9-12

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apply only to a single instruction set fails because context is a duatinstruction set processor. However, defintion of dual-instruction-set processor is one that CISC by executing RISC. Applicant's delinition of dual-

CISC and RISC. Thus the mere use of the t r "dual-instruction-set processor" does not change what Portasova teaches or em
suggests, unless AppIicant's d e f ~ t i o n dual-instruction-set processor is used as a of

instruction-set processor is one that

blueprint,

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Examiner believes that it is within the ordinary skill level to have a single execute unit execute both RISC and CISC instructions. Examiner also believes that it is within the ordinary skill level to modify onishi'sbranch decoder to decode a second instruction

o set, such as adding a CISC instruction decoder t a RISC processor. These beliefs are

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not reasonable.

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Examiner's motivation for using Qnisbi's two decoders is that it "allows the system to decode instructions more efficiently because decoding of a branch instruction usually takes longer than that of a normal instruction." Applicant asserts that the fact that
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branch instructions may take longer to decode is not a relevant motivation to having separate RISC and CISC decoders, since both would decode branch instructions. Thus the motivation provided for combining with is irrelevant and not reasonable. The cited motivation shows anishi to be directed to a different problem.

Scope of the C l a h s
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Examiner admits that the detail of hardware implementation was not specified by either reference, However, "to the extent of the scope of the claims to design a processor capable of executing dual instructions sets where a subset of second instruction set is implemented partly with hardware, the teachings and suggestions from the applied

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) references suffrciently meet the claim limitations.* (page 5.
Applicant disagrees that Applicant is merely claiming a "processor capable of executing dual instructions sets'', regardless of whether the second instruction set is wholly or partially implemented in hardware, That is not what the claims state. The claims recite

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at least a RISC and a CISC instruction decoder, a d an execute unit that receives n decoded RISC and decoded CISC instructions and executes both RISC and CISC

a instructions. Putting a PowerPCN M c and a 486 PC on a desk would ailow execution
of both a RISC and a CISC instruction set, but would not meet claim limitations of having the RISC and CISC decoders feed a single execute unit. Likewise putting
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EDrtanovas NSC CPU emulating CISC with a CISC VAX does not teach claim '
limitaions. Also a CPU die that has a RlSC pipeline in one corner and a CISC pipeline

in another corner would not meet the claim limitations since decoded RISC instructions

are sent to the RISC execute pipeline while decoded CISC instructions are sent to the
CISC execute pipeline,

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Eortanova, while appearing to "execute" dual instruction sets, also fails to teach or
suggest claim limitations of a RlSC and a CISC decoder which feed decoded discusses prior-art CISC instructions to an execution unit. The fact that
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architectures such as VAX and 68000 dces not mean that he suggests executing both RISC and CISC decoded instructions on the same execute unit ! Portanova specifically teaches that these prior-art CISC architectures can be emulated with his RISC processor. As the official action notes, emulation means replacing a CISC instruction with a plurality of RISC instructions.

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The official action on page 5 has thus broadened the scope of Applicant's claims. Even without the limitation of only a subset of the second instruction set being executed by the execute unit, the scope of the claims is narrower than merely executing dual instruction sets. The structure of two instruction-set decoders using a single execute
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unit is claimed but not taught or suggested by any cited reference. Indeed, Applicants believe that they have significantly advanced the state of the art by their invention which efficiently uses a single execute pipeline but two instruction decoders. Others will waste precious CPU die area by having two separate complete CISC a d RISC n execute pipelines. Applicant's invention is efficient and the public would benefit by its

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disclosure.
f Obvious & Show

re Detail of l ~ p ~ ~ ~ ~ n t 8 t i o ~

Some elements of dependent claims have not been shown in any of the references. For example, claim 3 claims a "mode register means, coupled to the select means, for

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indicating an instruction set to be decoded and executed." Examiner has not cited m y reference with such a mode register. Further details of this mode register and control

are presented in claims 4-5, 8, 13. Claims 18-19 recite that the mode register means
indicates RISC mode, CISC mode, or an emulation mode. Nowhere has the Examiner

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shown a teaching or suggestion for such a mode register indicating one of RISC, CISC,

or emulation modes.
These claims were summarily rejected with no attempt at an element-by-element

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analysis. If these features are truly conventional, then the Examiner is obliged to cite references for these features or submit an affidavit. M.P.E.P. $ 706.02(a). Clearly the scope and subject of these claims differ from the scope of other claims, and the Applicant deserves to have these claims examined too. M.P.E.P. $0 904, 904.02. Applicant requests that all claims be given a complete examination.

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X view of the above, it is submitted that claims 1-20, as amended, are in a position for n
allowance. Applicant requests that the requirement for formal drawings be held in abeyance until allowance. Applicant believes that a full and complete response to the

office action has been made. Reconsideration and re-examination is respectfully

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requested. Allowance of the claims at an early date is solicited.

If the Examiner believes that a telephone interview would expedite prosecution of this application, he is invited to telephone the undersigned at [phone].
Stuart T. Auvinen 429 2 t Avenue 6h Santa CNZ, CA 95062

Respectfullv Submitted.

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[phone] [phone] Fax

Stuart T. Auvinen Agent for Applicant Reg. No. 36,435