Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 5

EXHIBIT F

Dockets.Justia.com

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IN TILE UNITED STATES PATENT AWD TRADEMART( OFFICE
In re appfication of
BIomgren et al. Serial No. 081179,926 Filed: 2/11/94 For: Dual-I~truction-S~t Architecture CPU with Hidden Software Emulation M d oe
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Examiner: V. VU Group Art Unit: 2315

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R 37 C3.R. 0 1.111
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Hon. Commissioner of Patents and Trademarks Washington, Dc 20231
Sir:

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In response to the office action mailed 11/16/94, please amend the above-identified application as follows:

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In the claims:
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Please amend claims 1. 14, and 18 as follows:
1, (twice amended) A central processing unit (CPU) for processing instructions from

two separate instruction sets, said CPU comprising:
first instruction decode means for decoding instructions from a first instruction 25 set, said first instruction set having a first encoding of instructions;

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second inswction decade means for decoding a & & s k U & instructions from a second instruction set, said second instruction set having a second encoding of instructions, said fvst encoding of instructions independent from said second encoding of instructions;

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select mans, coupled to said first instruction decode means and said second instruction decode means, for selecting said decoded instruction from either said first instruction decode means or from said second instruction decode means; and execute means for executing decoded instructions selected by said select means, whereby instructions from both said first instruction set and said second

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instruction set are executed by said CPU.
14. (mice amended) A method for processing instruCtiOnS from two separate

instruction sets on a centxd processing unit (CPU), said method comprising: decoding instructions from a first instruction set with a first instruction decoder,
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said first instruction set having a first encoding of instructions;
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instructions from a second instruction set with a

second instruction decoder, said second instruction set having a secondincoding of instructions, said f i s t encoding of insmctions independent from said second encoding of instructions; selecting said decoded instruction from either said first instruction decoder or from said second instruction decoder; and executing said decoded instruction that was selected, whereby instructions from both said first instruction set and said second instruction set are executed by said CPU.

A microprocessor for executing instructions belonging to a
computer WSC) instruction set and for executing instructions instruction set computer (CXSC) instruction set, said microprocessor vrnprising:

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means, for decoding instructions belonging to said NSC instruction set; means, for decoding cmLu&S&insofctions ing a current operating mode of said microprocessor;
SC instruction decode means and said CISC

aid decoding of instructions belonging to said CISC instruction set, said enable means of said microprocessor; and rst instruction decode means and said instructions belonging to said first

Claims 1-4, 14, and 18-20 were rejected under 35 USC Q 112 as being indefinite and not commensurate in scope with the disclosure. Under 35 USC $ 103, claims 1-5, 1416, and 18-20 were rejected as obvious over )2ortanova d al (US Pat. No. 4,992,934)
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in view of Sltnishi (U.S. Patent No. 3,764,988). Claims 6-13 and 17 were rejected under 35 USC Q 103 as obvious over portanova in view of Sltnishi as set forth for

n claims 1-5, and further i view of
claims were thus rejected. 25

(U.S. Patent No. 4,456,954). All

Claims 1, 14, and 18 were amended to add a limitation to make the scope of the claims commensurate with the disclosure as noted by the Examiner. Applicant submits that with these amendments and the discussion below that claims 1-20 are allowable over

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the cited references. Reexamination and reconsideration of the claims, as amended, is hereby requested.
Summery of Independent Claims I, 44, 45,78

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Claim 1 recites a first and a second instruction decoder for decoding instructions from

a first and a second instruction set. A select means selects either the decoded
instruction from the first decoder or from the second decoder. An execute means executes the decoded instruction selected by the select means. Thus the execute means

can execute both first and second instructions provided by the select means.
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Independent claim 14 i s directed to a method for processing instructions from two separate instruction sets. Independent claim 15 is directed to a method for processing ~n~tructions a CISC and a RISC instruction set in which a11 CISC instructions are from executable, either directly by the execute unit or by emulation with RlSC instructions.
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Independent claim 18 is directed to a microprocessor for executing RISC and CISC hstructions us& both RISC and CISC instruction decoders and an enable means to enable one of the instruction decoders.

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Claims 1-4, 14, and 18-20 were rejected under 35 USC 0 112, first paragraph, as the
disclosure is enabling oniy for claims limited to decoder capable of directly decoding a subset and not the entire non-native instruction set.
A limitation that only a subset of the non-native instruction set is decoded was added to

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indepettdent claims 1, 14, and 18. Claim 1 was amended to recite a "second instruction decode means for decoding -instructions the CISC instruction set is decoded. from a second instruction set." Likewise, claims 14 and 18 were amended to recite that only a subset of the second or

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Thus with these amendments the claims recite a limitation that only a subset of the second instruction set is decoded, making the claims commensurate in scope with the specification. Thus the 35 USC 5 112,first paragraph rejection has been overcome.

0 PRIOR ART RETECTIONS - 35 USC 5 1 3 PORTANQVA IN VIEW OF ONISHI.
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Under 35 USC

103,claims 1-5, 14-16, 18-20were rejected as obvious over and

a a (US Pat. No, 4,992,934) view of ih&hi (U.S. NO. in Patent
teaches a system capable of executing both 3,764,988).For claims 1-2, RISC and CISC instructions. In particulariy, the system comprises a core structure of a RlSC computer, and an emulation unit using RISC routine for emulating the execution
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of CISC instruction. The CISC emulation can be implemented with hardwired or firmware, It is noted that the hardware implementation of the CISC emulation would have required a modification to the RlSC processor for providing the additional capability to decode and execute CISC instructions.

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does not specifically teaches using two separate decoder Units for decoding

nt RlSC and CISC instructions respectively. The use of multiple decoder uis for
decoding different types of instructions is however well-known in the art. The use of multiple decoders, each designated to decode certain type of instructions, is desirabie because it allows a simple and efficient design of the instruction decoder. anishi
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teaches a processor comprising two instruction decoders, the first decoder for decoding normal instructions and the second decoder for decoding branch instructions (see abstract). By using the second instruction decoder, the decoding sequence of a branch instruction can be reduced (see summary). It is noted that a selector is obviously needed to select decoded instructions from the first and second decoders.

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Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Portanova's system to utilize two instruction decoders as taught by

anishi for decoding RISC and CISC instructions respectively. This is because the use

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of separate instruction decoder uis for RISC and CISC instructions allows more nt simple and efficient design of the decoder units. Applicant respectfully disagrees.

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teaches a system that emulates CISC instructions witb routines of RISC instructions. CISC instructions are never directly executed on Portanova's hardware, such as his ALU 104. CISC instructions must be replaced by RISC instructionsto be

n executed. Only NSC instructions are ever directly executed i Portanova's hardware.
10 It was stated in the rejection (page 6, 1st paragraph) that "The CISC emulation can be line implemented with hardwired or firmware. (see ~0129, 60 - col30, lines 12 and figures 9-10}. It is noted that the hardware implementation of the CISC emulation would have required a modification to the RISC processor for providing the additional capability to decode and execute CISC instructions."
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Applicant notes that no details of a hardware implementation of CISC instructions in a

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RISC processor are provided in does teach hardware . If indeed As execution of CISC,then more disclosure is required of w. the Examiner notes in his 35 USC Q 112, first paragraph rejection, "the design of such a decoder and nt" execution u i s [capable of both RISC and CISC],"if possible, is not clearly obvious
to one skilled in the art without further requiring undue experimentation because the
complexity of the system with such ability would increase significantly." Certainly

Portanova does not provide an enabling disclosure for a combined RISC and CISC
execution unit or decoder.
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A close examination of the cited Figure 11 and the context at cols, 29-30 reveals that

n the discussion i Portanova centers on prior-art CISC systems, not on a combined

RISC and CISC processor. Indeed, Figure 11 is cledrly labeled "PRIOR ART". At col
29-30, Portanava discusses the third aspect of his invention, a design methodology for

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implementing a CISC (col 29, line 59-62). He then discusses current, prior-art design methods for existing CISC systems. Figure 9 is a prior-art 28000 CISC, which is a

0 hardwired CISC architecture. Figure 1 is a Motorola 68000 CISC, which uses
firmware rather than direct hardwired control. Figure 11 is a MicroVAX (col30, line

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28). The MicroVAX uses software emulation of complex CISC instructions, but

firmware of simpler CISC instructions. Figure 12 is an IBM S/370, (COI 30, line 37) which uses software emulation to implement CISC instructions 326 on RISC hardware 334 *
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It should be noted that the 28000, Motorola 68000, MicroVAX, and System/370 are
all well-known CISC architectures. The hardware that actually executes instructions i n

Portanova's Figures 9-11, (302, 310, and 324) are CISC execute units that do not
execute RISC instructions. Figure 12's hardwired unit 334 is a RISC unit that emulates CISC using software emulation 330, similar to Portanova's RISC that emulates CISC.

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Thus no hardware unit in Portanova'sFigures 9-12 teach hardware that can execute both RISC and CISC.
`s design methodology apparently could emulate all these CISC architectures:

28000,68000,VAX, S/370, implemented on his RISC processor. The RlSC processor
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is first designed and optimized, then the CISC emulation code is written (col30, lines
39-64). These can be two separate steps because the RISC hardware does not directly

execute any CISC instructions. The fact that the RISC hardware is first designed, optimized, and fabricated before the CISC emulator is written -r m fo
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the

invention, which executes some CISC instructions on a RISC processor. If the RISC hardwaxe is modified for CISC hardware emulation, then CISC must be taken into account during the design of the RISC processor.

Portanova'sRISC processor never executes CISC instructions, but merely emulates the
CISC instruction-set architecture by replacing CISC instsuctions with routines of RISC

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instructions. Nowhere does Portanova teach or suggest that any CISC instructions are CISC instruction is emulated (col30, line 45, executed on the WSC execute unit. also col7, lines 10-25).
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thus does not teach or suggest hardware implementation of the CISC
emulation. It is me that hardware execution of CISC would require a modification to the RIsC processor to provide &e additional capability of decoding and execution of CISC instructions. Nowhere does disclose such a modification or suggest that both CISC and RISC instructions can be executed on the same hardware. The fact

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that such a modification is necessary, and that j3xtam does not teach or suggest such

a modification is evidence that the present invention is not obvious. Certainly
does not teach or suggest that a syhset of the CISC instructions can be

executed on the RISC hardware while the other CISC instructions are emuIated.

~~ffciencies of
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does not specifically teach using two separate decoder units for decoding

RISC and CISC instructions respectively. Q&&ia processor comprising two teaches instruction decoders, the first decoder for decoding normal instructions and the second decoder for decoding branch instructions.
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Qnisbjteaches a decoder for a single instruction set. He partitions or divides this
decoder into one decoder for branch instructions, and the other decoder for all other types of instructions. This is done to reduce the decoding sequence for branch instructions, which are among the most speed-critical instructions. This makes the
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cornput& operate at higher efficiency (coi I, line 20).

Onishl Solves B Different Problem, for a Different Motivation
In contrast, the present invention uses two decoders because two separate instruction
sets must be decoded: The computer does not operate at higher efficiency due to the

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two decoders, and indeed may be slower because two decoders are needed rather than just one decoder. The motivation for using two decoders is to execute two instruction sets rather thanjust one instruction set. Thus flexibility rather than speed is the problem solved by the present invention. Solving a different problem is an indication of
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non-obviousness.

With two instruction decoders for two different instruction sets, the same bit pattern or opcode can be decoded into two different instructions, one for RlSC and the other for

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CISC.Both outputs can be valid operations. Thus the present invention can output valid decoded instructions from both of the decoders, and one must be selected.
Applicant's specification explains how the same opcode, 03 hex, can be two valid operations

- CISC addition or IUSC trap-word-immediate:

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This same opcode, 03 hex, corresponds to a completely different instmction i the RfSC n instiuction set. In CISC 03 hex is an addition operation, while i RISC 03 hex is TWI - trap n word impxdiate, a control transfer instruction. Thus two separate decode blocks are necessary for the two separate instruction sets. (Spec on page 25, lines 2-6)

partitions a single decoder for a single instruction set into two decoders for 20 different types of instructions (branches) within that one instruction set. With snishi,

one of the decoder's outputs will always be invalid. The present invention uses two
decoders because two separate instruction sets are decoded. Thus Qnishidoes not teach

or suggest that a decoder for a RISC instruction set be used with a second decoder for a

CISC instruction set.
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As to claims 3-4, it would have been obvious to one skilled in the art to utilize an
execution mode register for indicating the execution of native and non-native instructions. As to claim 5, Portanovafurther teaches that the CISC emulation unit can also be implemented by using both hardware and sofrware in which some CISC
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instructions would be directly decoded and executed by the execution unit and the

IC execution of the rest of CISC instructions is emulated by using R S routines (see col
30, lines 13-28 and figure 11). Thus, it would have been an obvious engineering

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design choice to one of ordinary skill in the art at the time of the invention to utilize both software and hardware implementation to emulate CISC instructions on a EUSC computer. The implementation o f both software and hardware approaches could have

been motivated because of the combined advantages of both techniques, Le. the
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simpleness and flexibility of the software emulation approach and the speed of the hardware emulation approach. Applicant respectfully disagrees. As noted above for c1ai.m.s 1-4, &&wya emulates all CISC instructions, Portanova nowhere teaches or suggests that any CISC instructions be directly executed. Indeed,
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teaches away from hardware execution of any CISC instructions because design methodology is to fvst build a pure RISC processor hardware, without regard to ?he CISC architecture, be it VAX, 28OO0, or 68K,and then write the CISC emulation code. As discussed above, the cited figures and cols 29-30 of

PortanovaclearIy are discussing prior-art CISC systems that can be EMULATED on
his RISC hardware. The rationale that such a major modification to the RISC hardware to support CISC hardware execution is merely an "obvious engineering design choice" indicates that undue experimentation is necessary. As the Examiner notes in his 35 USC $ 112, first

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paragraph rejection, "the design of such a decoder and execution units" [capable of both RISC and CISC], "if possible, is not clearly obvious to one skilled in the art without further requiring undue experimentation because the complexity of the system with such ability would increase significantly. Certainly Poaanovadoes not provide an enabling disclosure for a combined RISC and CISC execution unit or decoder.

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Further, nowhere does Portanova suggest or teach that only a subset of the CISC instruction set is executed in hardware.

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Invention as B Whole Not Obvious from the Combination
The references are deficient because none teach or suggest decoding and dEectly executing two instruction sets, Beyond these deficiencies, a strained combination of 5 references has to be made, as anishi does not pertain to dual-instruction set processors, The present invention solves the problem of flexibility by decoding two separate instruction sets, while anishi solves the different problem of speed of decoding branch instructions in a single instruction set.
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No suggestions or motivations in these prior-art references have been cited to justify
such a combination. Other combinations are possible, and this undue experimentation

has been cloaked as an "engineering design choice." Something in the prior art must
suggest the desirability of making the combination. Uniroyal,Znc. v. Rudkin-Wiley

Cop., 837 F.2d 1044, 5 USPQZd 1434, 1438 (CAFC 1988). If the prior art provides
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no teaching, suggestion, or incentive suKporting the combination proposed by the n Examiner, then the rejection is i error and must be reversed. In Re Bond, 910 F.2d
831, 15 USPQ2d 1566 (CAFC 1990). The claimed invention must not be used as a blueprint,

PRIOR ART REJECTIONS - 35 USC 3 103 - -NOVA.

ONISHX.

BULLIONS

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Claims 6-13 and 17 were rejected under 35 U.S.C. Q 103 as being unpatentable over and Q&hj as set forth above for claims 1-5, 14-16 and 18-20fbrther in view of Bullions, III et al, (hereafter Bullions) U.S. pat. no. 4,456,954.

As to claims 6-7, 9-10 and 17, neither Portanova nor W teach using a translation
25 look aside buffer (TLB)

BulIions teaches using a TLB for translating a virtual address

to a physical address for both host and guest instructions (see abstract). In particularly,

a Tu3 is utilized to address emulation host routine for a guest instruction, Bullions

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further teaches that a miss in TLB also triggers a change of execution modes, Le. from host to guest (see summary and claims). Applicant respectfully disagrees. The arguments presented above apply with equal force and effect to dependent claims

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6-7, 9-10 and 17.

Bullions teaches a CISC system that emulates guest architectures on a native
architecture. Each level of architecture is capable of using virtual addressing with dynamic address translation. (col 1, lines 8-25). AIL operating systems described by

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Bullions are well-known CISC architectures (col 1, lines 29, 50). Thus Builionsdoes
not teach processing both RISC and CISC instructions, but merely teaches emulating "guest" CISC architectures on a native CISC machine.

Butlions uses the word "architecture" to mean something other that "instruction set".
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His summ&ryand claims refer to guest `programs" but not to guest "instructions" from

a different "instruction set". A guest program does not necessarily use a different
instruction set. Indeed,the "plural levels of architecture" referred to "involve plural levels of address translation." (cot 5 , lines 24-29). These plural architectures refer to
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architectures, not to instruction set architectures. Bullions clearly

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states that "different architectures may use different size addresses, e.g. one architecture may use 24 bit addresses while another architecture may use 31 bit addresses." However, all operating systems described by Bullions use the same instruction set.

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Thus the execute unit that is coupled to the TLB does not execute instructions from two instruction sets, but merely executes CISC instructions. Claim 6's limitation of a TLB coupled to te execute means" is not taught by Bullions because Bullions executes h single instruction set, but merely uses different address translation architectures for native and guest programs.

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Further, claim 6 recites that the TLB provide "an indication to said mode control means to change said instruction set decoded to said first instruction set when no translation is found in said TLB" .
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does not teach that another instruction set is

decoded.

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teaches that the architecture "mode" is changed on a TLB miss,

causing a native program rather than a guest program to execute. It is thus improper to replace ~&&QIx&
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architecture or program with the word

instxuction" , as his programs and architectures refer to different address transIation architectures and not to different instruction sets. Bullions teaches guest programs and guest architectures, but not guest instructions from a different instruction set. Claim 17 recites translating memory references generated by CISC instructions that are directly executed, where the translation of memory references is controlled by a
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software translator routine comprised of RISC instructions. Bullions fails to teach that

RISC instructions are used in a software translator routine while some ClSC
instructions are directly executed. Thus claim 17 cannot be obvious in view of Bullions and the other references.

~ d d i ~ i oRemarks n~l
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The remarks in paragraph 16 of the second office action referring to Porranova as teaching using either software or hardware is assumed to be referring to cols 29-30,

' design methodology first builds a WSC hardware without regard to the CISC instruction set to

which were shown above to teach away from the invention as

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be emulated, and then writes the CISC emulation software. Portanova achieves faster

time to market by ignoring the CISC aspects of the design until the hardware is designed.

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These remarks to refer to W ' s two decoders as "clear evidence of a system employing partially duplicated hardware resources", It was also stated that whether the emulation unit is integrated or separate is a design of choice. Applicant's invention

allows both instruction sets to be executed on a single execution unit, eliminating

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duplicated hardware for execution, Thus duplicated hardware resources are not needed for the execute unit, but only for the decoders. This approach is not suggested in any of the cited references and is not merely a design choice of separating units, as in a coprocessor, or integrating units.

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In view of the above, it is submitted that claims 1-20, as amended, are in a position for allowance. Applicant requests that the requirement for formal drawings be held in abeyance until allowance. Applicant believes that a fult and complete response to the office action has been made. Reconsideration and re-examination is respectfutly requested. Allowance of the claims at an early date is solicited.

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If the Examiner believes that a telephone interview would expedite prosecution of this application, he is invited to telephone the undersigned at [phone].

Stuart T. Auvinen 429 26th Avenue S a m Cruz, CA 95062
[phone] [phone] Fax

Respectfully Submitted,

Stuart T. Auvinen Agent for Applicant Reg. No. 36,435

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PATENT

Honorable Commissioner of Patents and Trademarks Washington, DC 20231

2$\ Small entity status of this application under 37 C.F.R.
statement previously submitted. No additional fee is required.
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1.27 has been e

The fee has.been calculated as shown below: Add'] Fee

+ $230
U A check in the amount of $
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to cover these fees is enclosed. for these fees. A

$ ,

Please charge my deposit account No. 01-2950 in the amount of $ duplicate copy of this sheet is enclosed.

The commissioner is hereby authorized to charge payment of the following fees associated with this communication or credit any overpayment to deposit account No. 01-2950. is -cd. Any additional filing fees required under 37 C.F.R. g 1.16. Any patent application processing fees under 37 C.F.R. g 1.17.

Reg. No. 36,435 Agent for Applicant

[phone]

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