Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 3

EXHIBIT D

Dockets.Justia.com

PATENT
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RM- 1

In re application of
Blomgren Serial No. 081179,926 Filed: 1/11/94

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Examiner: V. Vu Group Art Unit: 23 15

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For: Rual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode

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Ron. Commissioner of Patents and Trademarks Washington,DC 20231
Sir:

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In response to the office action m i e 6/27/94, please amend the above-identified ald

application as follows: In the specification:

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On page 2, line 8, before "BACKGROUNDOF THE INVENTION" please insert
--BACKGROUND OF THE INVENTION

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- RELATED APPLICATIONS

This application is related to co-pending application for a "Pipeline with Temporal ReUnits for Dual-Instruction-Set CPU", filed 1/11/94. U S , Arrangement of FunCti0~1

Ser. No. 08/179,926
Artunit: 2315

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Printed 9/19/94

Serial No. 08/180,023, now Patent No.

5$42, 039 . This application is further
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related to copending application for "Emulating Operating System Calls in an Alternate Instruction Set Using a Modified Code Segment Descriptor", filed 7/20/94, U.S. SeriaI

No. 08/277,905, now Patent No. c/45?/,X84

. This application is further related

to copending application for "Shared Register Architecture for a Dual-Instruction-Set

CPU" ", Cled 7120194, U.S. Serial No, 08/277,962, now Patent No,
assigned to the same assignee as the present application. -e

< 48' k43 . /,,

These related applications have a common inventor and are

arate instruction sets, [the] said CPU comprising:
first instruction decode means for decoding instructions from
set, [the] said first instruction set having a first encoding of ins
second instruction decode means for decoding instru

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instructions, Ethel sgkl first encoding of instru encoding of instructions; select means,coupled to [

ndent from [ h ] said second te decode means and [the] said ecoded instruction from

1 said second instruction
25 decudemeans;and

2, (amended) The CPU of claim 1 further Comprising:

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an instruction fetch buffer, containing instructions to be decoded, coupled to
[the] said first instruction decode means and [the] said second instruction decode means; and instruction pointer means, coupled to [the] said instruction fetch buffer, for

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indicating [the] an address of [the] a next instruction to be decoded.
3. (amended) The CPU of claim 1 further comprising:

mode register means, coupled to [the] said select means, for indicating [the] rn instruction set to be decoded and executed.
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4. (amended) The CPU of claim 3 further comprising:

mode control means, coupled to [the] said mode register means, for changing [the] said instruction set to be decoded.
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5. (amended) The CPU of claim 4 wherein
the second instruction decode means decodes only a portion of [the] said second instruction set, and [the] second instruction decode means indicating to [the] said mode control means when an instruction is not in [the] sitid decoded portion of [the]

said second instruction set;
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[the]

the mode control means changing [the] said instruction set to be decoded to

said first instruction set when an indication is received that an instruction is not in [the] said decoded portion of [the] said second instruction set.
6.(amended) The CPU of claim 5 further comprising
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coupled to [the] Saul execute means, [the] a tmsIxtion-Iookaside buffer (TLB)

said TLB having address transiation entries for translating a virtual address from [the] said execute [unit] m e a ~ to a physical address for accessing a main memory, [the] sitid s TLB providing an indication to [the] said mode control means to change [the] said instruction set to be decoded to [the] said first instruction set when no translation is

Art Unit: 2315

Ser. No. 08/179,926

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Printed 9/19/94

found in [the] said TLB corresponding to [the] d virtual address from [the] said execute [unit) means.

7. (amended) The CPU of claim 6 wherein a handIer routine comprised of instructions

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means.

first instruction set is fetched from main memory and executed when
mode control is signaled by [the] said TLB or by [the] said second instruction decode

8. (amended) The CPU of claim 7 wherein [the] said execute unit provides an
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indication to [the] said mode control means when an exception occurs in [the] said mode control means changing [the] said instruction set to be decoded to [thel Saiici first instruction set when [the] s i indication is received. ad

9. (amended) The CPU of claim 6 wherein all references to main memory generated

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by instructions in [the]

second instruction set are translated by [the]

TLB,

10. (amended) The CPU of claim 6 wherein [thel Sairi address translation entries in
[the] atid TLB are loaded only by instructions decoded by [the] @ first instruction

decode means.

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11. (amended) The CPU of claim 1 wherein [the] d first instruction decode means 0

decodes instructions from [thel said first instruction set and extended instructions added

to [thel said first instruction set, and wherein [the] said address translation entries in
[the] said TLB are modified only by [the] said extended instructions.
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12.(amended) The CPU of claim 11 wherein [the] izd fist instruction decode means

is selected to decode instructions immediately following a reset of [the] said CPU.

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/-.
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2,.
1

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hinted 9/19/94

13. (amended) The CPU of claim 11 wherein [the] iw,I extended instructions are decoded by [the] Said first instruction decode means only when [the] & mode control means is signaled to change [the] said instruction set to be decoded or immediately following a reset.
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decoding instructions from a first instruction set [the]
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fist instruction set having a first encoding
decoding instructions from a second with a second instruction second encoding of instructions, ent from [the] aid second encoding of

decoder, [the] said second instruction set [the] said first encoding of instru instructions;

m either [the] said fist instruction
that was selected, [the] Sairt decoded ereby instructions from both [the] said first instruction set and {the] saridi instruction set are executed by [the] said CPU.
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15. (amended) A method for processing instructions from a complex instruction set

computer (CISC) instruction set on a reduced instruction set computer (RISC) Central Processing Unit (CPU), [the] said method comprising:
attempting to decode an instruction with a CISC instruction decode unit that

does not decode all instructions in [the] saica CISC instruction set;
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directly executing [the] said instruction in an execute unit if [the] silid CISC instruction decode unit is able to decode [the] said instruction; entering an emulation mode if [the] said CISC instruction decode unit is not able

to fully decode [the] Said instruction, indicating that [the] W execute unit cannot
directly execute [the] said instruction;

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disabling [the] said CISC instruction decode unit and enabling a RISC instruction decode unit when entering emulation mode; loading an instruction pointer with an address of a software emulation routine for emulating [the] said undecodable instruction, [the] ai,d routine comprising
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instructions from a separate RISC instmction set; decoding RISC instructions with [the] & RISC instruction decode unit as [the]

said software routine is executed; RISC instructions in [the] ai,d execute unit; and executing [the]
exiting emulation mode, disabling [the] said RXSC instruction decode unit and
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CISC instruction decode unit when [the]
software emulation routine is reached,

end of [the] gi id

whereby all instructions from [the] said ClSC instruction set are executed, either directly by [the] said execute unit or by emulation with a software emulation routine comprised of RISC instructions.
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16. t & d The method of claim 15 wherein m e) the software emulation routine is comprised of RISC instructions and extended instructions, [the] said extended instructions using undefined opcodes in [the] said
RISC instruction set;

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the method further comprising decoding and executing extended instructions While [the] said software emulation routine is being executed.
17. (amended) The method of claim 16 further comprising:

translating memory references generated by [the] said CISC instructions that are
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directly executed, [the] said translation of memory references controlled by a sofnTrare &anslator routine comprised of RISC instructions and extended instructions, [the] said translator routine loading [the] said resulting translations into a translation-lookaside buffer.

Ser. No. 081179,926 &Unit: 2315

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Printed 9119/94

A microprocessor for executing instructions belonging
ction set computer (RISC) instruction set and for executing to a complex instruction set computer (CISC) instmction set, comprising:
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RISC instruction decode means, for d

said RISC instruction set;
CISC instruction decode means, for

& CISC instruction set;
mode register means for indicating

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microprocessor; enable means, coupled to [the SC instruction decode means and [the]

& CISC instruction decode belonging to [the] &ai$ RIS
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r enabling [the] said decoding of instructions
belonging to [the] said CISC instruction

said current operating mode of fthe]

said microprocessor.
frrst instruction decode means and [the] executing instructions belonging to [the] set and htructions belonging to [the] said second instruction set, by instructions from Ithe] said RISC instruction set and instructions from

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CISC instruction set can be executed by [the]

execution unit.

19. (amended) The microprocessor of claim 18 wherein [the] said mode register means

indicates CISC mode, RISC mode, or an emulation mode, wherein a portion of [the]

said CISC instruction set is decoded by [the]
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instructions are emulated by emulation mode.

CISC instruction decode means when

[the] said mode register means indicates CISC mode, and wherein undecoded CISC

20. (amended) The microprocessor of claim 19 wherein emulation mode is entered
.when [the] said CISC instruction decode means signals an undecoded instruction, [the]

_--.

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fl % u "
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said mode register means changing from CISC mode to emulation mode when an
undecoded instruction is signaled.

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Claims 2-13 were rejected under 35 USC $ 112 as being indefinite. Under 35 USC $ 5 102(b), claims 1-4 were rejected as anticipated by 3k et a1 (US Pat, No. 4,821,187). .b Claims 1-20 were also rejected under 35 USC $ 103 as obvious over & H k s h (US Pat. No. 5,167,023). All claims were thus rejected.

Claims 1-20 have been amended to use the article "said" in place of "the" as requested
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by the Examiner. Claims 2, 3, and 6 were amended to fix the antecedent problems

noted by the Examiner. Applicant submits that with the discussion below that claims 120 are allowable over the cited references. Reexamination and reconsideration of the

claims, as mended, is hereby requested. 15 The specification has been amended to indicate cross-references to related co-pending applications. Related co-pending application seriaI no. 08/180,023 was not earlier mentioned because it was filed on the same date as the present application.
Summary of /ndep~nden~ Claims I, I

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Claim 1 recites a first and a second instruction decoder for decoding instructions from

a fist and a second instruction set. A select means selects either the decoded
instruction from the first decoder or from the second decoder. An execute means executes the decoded instruction selected by the select means. Thus the execute means
can execute both first and second instructions provided by the select means.

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25 Independent claim 14 is directed to a method for processing instructions from two separate instruction sets. Independent claim 15 is directed to a method for processing instructions from a CISC and a RISC instruction set in which all CISC instructions are

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Ser. No. 081179,926 A ~ IUnit: 2315

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Printed 9/19/94

executable, either directly by the execute unit or by emulation with RISC instructions. Independent claim 18 is directed to a microprocessor for executing RISC and CISC instructions using both RISC and CISC instruction decoders and an enable means to enable one of the instruction decoders.
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35 USC

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Claims 2, 3, and 6 have been amended to overcome the 35 USC definite, overcoming the 35 USC

0 112 rejection by

providing a proper antecedent. Applicant submits that the claims are now clear and

0 112 rejections to the claims.

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PRIOR ART REIECTIONS I@@) IN VIEW OF yEI24 Claims 1 4 were rejected as anticipated by et a1 CVS Pat. No. 4,821,187).
is

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cited as a system capable of executing two different instruction sets. The system comprises two separate decoders for decoding first and second set of instructions respectively, execution units for executing the decoded first and second instructions,
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control units for controlling switching execution of Erst and second instruction sets. Applicant respectfully disagrees and with the following argument overcomes the rejection.

LMa teaches a parallel processor for simultaneously executing two programs. In the
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Multi-program mode, "high-speed processing i s attained by parallel run of the two independent programs." (coI 2 Iine 13) The present invention does not require two independent programs, nor does it require parallel processing. U is from a different field and attempts to solve a different problem than the present invention, which solves the problem of executing instructions from two different instruction sets.

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L a teaches two instruction decoders for two different microinstructions. The first M
microinstruction controls the first operation unit, while the second microinstruction controls the second operation unit. It is not clear from yedit if these microinstructions

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Ser. No. 081179,926 Art Unit: 2315

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Printed 9/19/94

are generated from two different instruction sets, or are merely generated in response to programs written in a single instruction set.

Structural ~ ~ e ~ with c e s ~
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As && is directed to a different field, parallel processing, it is not surprising that significant structural differences exist between LWa and the present invention. The diagram below compares the structure of claim 1 (on the left) to W (on the right). The diagram for LWa below is simplified from his Figures 1 and 7. The select means
recited in claim 1selects either the decoded instruction from the fist instruction decode
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means or from the second instruction decode means. YpLdii neither teaches nor suggests the select means. Instead, sends first microinstructions to the first operation unit, also neither teaches and second microinstructions to the second operation unit.

nor suggests execute means that can execute decoded instructions f o the select rm

means, as recited by claim 1. Since the select means recited in claim I can select either
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a first or a stxond decoded instruction, the recited execute means of claim 1 can execute either a first or a second decoded instruction.

Present20
yedals first operation unit can only execute first microinstructions, whiIe & & i

second operation unit can only execute second microinstructions. yr;da thus neither teaches nor suggests an execute means that can execute both first and second

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instructions.

also neither teaches nor suggests the select means recited in claim 1,

as W has no need for a select means.

I.kda3 fvst control means, shown in the top center of the diagram, decodes both first
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di and second microinstructions. & & second control means, on the top fat right,
decodes only second microinstructions. UxjiCs first control means decodes a compound micro-instruction word that can have fields for both first and second microinstructions, as shown in his Figwe 2A.The second operation field is sent to the second operation unit, while the first operation field is sent to the f m t operation unit. When multi-

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program mode is used, the second control means decodes a microinstruction as in
y_e$als Figure 38, sending the control field to the second execution unit. In multi-

looks like two independent processors. In contrast, the presenx invention funnels both first and second instructions to the same execute maas.

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Dependent claims 2, 3, 4 depend upon claim 1, which is allowable for the above-stated reasons. Thus claims 2,3, 4 are also allowable for the above-stated reasons. Claim 2 recites an instruction fetch buffer that is coupled to both the first and the second instruction decoders. lleda teaches two separate program memories (col3 line 5),

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supplying two decoders (see his Figure 1, elements 3, 4 . ) Claim 3 recites a mode register means that indicates to the select means the instruction set to be decoded and executed. Claim 4 recites a mode control means for changing the instruction set to be decoded. W does not teach a mode register to indicate the

2 5

instruction set. Indeed, yl;da is directed to parallel processing, and can execute both first and second microinstructions simultaneously in the two separate operation units,
Yepa does not teach a mode where only second microinstructions are executed, unlike

the present invention, which can execute either first or second instructions.

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munit: 2315

In summafy, ?. &is absent any teaching or suggestion of the select means recited in .k
sends first microinstructions to a first operation unit and second microinstructions to a second operation unit. The present invention uses the select means recited in claim I to send either first instructions or second instructions to the 5 neither teaches nor suggests an execute means capable of executing both first and second instructions, as selected by a select means. cannot render claim 1 anticipated, nor obvious. .uc;da also neither teaches nor suggests an instruction fetch buffer coupled to the first and the second instruction decoders, as recited in claim 2, and the mode register means and control recited in claims 3 and 4.
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PRIOR ART RETECTIONS - 35 USC 9 103

- 1zE

ET AL.

C a m 1-20 were rejected under 35 WSC 8 103 as obvious over Be Nicolas WS Pat. lis No. 5,167,023) hereinafter Nicolas. As to claims 1-4, E m h i is cited as a system for
emulating the execution of second set of instructions which are not directly executable
by the host system. The system is capable of directly executing native RlSC

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instructions in a normal mode and executing CISC target instructions in an emulation mode. Nicholas describes a number of prior-art systems, one of which was implemented the instruction emulation with hardware. It would have been obvious that such hardware emulation would have included a second decoder for decoding target instructions, and other control units for controlling the emulation mode for executing

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target instructions. Applicant respectfully disagrees,
Coprocessor Does Not Render the Invention Obvious

Nicoias teaches a system that emulates instructions in a second instruction set using a
plurality of instructions in a first instruction set. Nicolas neither teaches nor suggests a
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processor that can execute both CISC and lUSC instructions in hardware except for briefly mentioning in the background section using a coprocessor. A coprocessor is a

second entire processor with a separate execute unit. The present invention recites a
select means to supply an execute means with decoded instructions from either of two

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instruction sets. A system with a coprocessor has two separate execute units,one unit for executing first instructions and a second unit for executing second instructions. However, neither unit can execute both first and second instructions. Such a system would lack an execute means that executes "decoded instructions selected by the select
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means", which include both first and second decoded instructions. A coprocessor-based system would aIso lack the select means of claim 1. A coprocessor does not render the recited invention obvious.
A coprocessor is similar to the multi-program mode of Uxh, and the structural

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differems discussed above i reference to n

also apply here. There would be no

connection for decoded second instructions from a second decoder in the coprocessor to
the execute means in the main processor. In contrast, the recited invention uses a select
meafls to

route decoded second instructions to the execute means. Thus the coprocessor does not teach or even suggest using a select means or an execute

discussion in
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means for executing both first and second instructions. Coprocessors teach away from the present invention because a separate execute unit is
used for the second instructions. The present invention has the new result of having a

single execute unit that can execute instructions from two separate instruction sets,
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eliminathg the need for and cost of a second (co-) processor to execute second instructions. This new result, lower cost from eliminating an expensive component (the co-processor) argues against obviousness since there was strong financial motive for others to use the present invention, yet the prior art does not teach or suggest the present invention. Therefore a coprocessor does not render the present invention

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obvious and indeed its very existence argues against obviousness.
Emulation Does Not Render the Invention Obvious

Nicolas teaches emulating second (simulated) instructions by replacing them with a
plurality of first (host machine) &ructions. Nicolas is directed to the problem of

Ser. No. 081179,926
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reducing the number of fust instructions needed to emulate a second instruction, from

50-100 down to'4 (col4 l i e s 12-26). The present invention solves JY&&&

problem

by directly executing some or all of the second instructions. The present invention thus effectively reduces the "plurality of fist instructions" down to one second instruction.

5

This is a great speed advantage over

and yet he does not even suggest directly

executing second instructions, except with a separate coprocessor, which he says is too limiting (col2 lines 47-55).Instead, Xkdas emulates second instructions. kk&%

certainly does not teach or suggest a combination of emulation and direct execution of
second instructions, despite the great advantage that such a system would have.
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There is nothing i emulation of a second instruction set to suggest the select means or n rhe execute means recited in claim 1, because the select means and the execute means receive decoded instructions from both the first and the second instruction sets, whereas emulation can only replace second instructions with first instructions. Thus
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any emulation system would provide only decoded fust instructions to the execute unit.
There would be no use for a select means, since there is nothing to select - only decoded fxst instructions are sent to the execute unit.

An emulation system thus neither teaches nor suggests the select means and the second
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decode means recited in claim 1, The execute means of such an emulation system would not execute both first and second instructions, as recited in claim 1 by the connection to the select means.Thus elements in claim 1 are missing and are not even suggested by 25

. As no second decode means is present or suggested, claim 2's

instruction fetch buffer coupled to the first and second instruction decode means is also not suggested or obvious. Likewise claim 3's mode register means is not needed since Only fmt instructions are ever executed by an emulation system. Second instructions

cannot be directly executed, so no mode register is needed.

Ser. No. 081179,926 Art Unit: 2315

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Printed 9/19/94

Emulation does not render claims 1-4 obvious, and recited claim elements, such as the select means,are not taught or even suggested by render claims 1-4 obvious.
CIaims 5-10 Not O&ViOUS

m. Nicolas does not Thus

5

As to claims 5-10, Nicolas is cited as teaching emulating the execution of CISC
instructions using software where each CISC instruction execution is emulated by executing a routine comprising a plurality of individual RISC instructions, and where the emulation mode is initiated by an interrupt signal. Nicolas further teaches using a

0 translation-lookaside buffer (TLB) for providing dynamic address conversion for
executed instructions. Nicolas does not particularly teach incorporating both hardware and software emulation in the same machine as claimed. It would have been obvious to realize such a hardware and software combination because it would bring the advantages of both techniques into the system, e.g. the inexpensive and flexibility of
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the software emulation with the speed of the hardware emulation. Applicant respectfully disagrees,

As claims 5-10 are dependent upon independent claim 1, the above-mentioned reasons
as stated in reference to claim I apply with equal force and effect to claims 5-10.

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Himla emulates all second instructions. There is no suggestion that only a portion of
the second instruction set is emulated while another portion of the second instruction set is decoded and directly executed. Claim 5 recites that the second decode means decodes only a portion of the second instruction set. Nicolas does not teach or suggest
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a second .decode means, nor does Nicolas teach or suggest that a second decode means would only decode a portion of the second instruction set. Only by hindsight using the claims of the present invention as a blueprint can it be suggested that Nicolas teaches what is recited in the claims.

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Claim 5 further recites that the second decode means indicates to the mode control

meam when an instruction is not in the decoded portion of the second instruction set,

thus changing to the first instruction set to allow for emulation or other handling by the
first instruction set. Applicant was unable to find any reference in the background

5

section of Nicolas to using an interrupt to initiate emulation mode, and certainly such a

m. claim 5 cannot be obvious in view of k&x,b. Thus
10

signal would not be generated by a second instruction decoder as none exists in

Claim 6 recites that the mode control means be signaled to switch to the first instruction set when no translation is found in the TLB.Again, nothing in NicDlas would suggest or imply that such a signal be generated or necessary, as k&%h only executes f i s t instruction and has no mode control. Likewise having an exception in the execute means signaling a switch to the first instruction set is nowhere suggested in

l%x?laS.
15

Although the present invention has the advantages cited by the Examiner as the reason
that it would be obvious to realize such a software and hardware combination, the low

cost and flexibility of software emulation and the speed of hardware, and despite the amount of inventive activity in emuiation, no cited reference teaches the invention.

20

These advantages and the failure of others to teach the invention argue in favor of nonobviousness. Thus claims 5-10 are not obvious in view of W, As per claims 11-13, it is cited as being obvious to use additional instructions to modify the TLB or to switch to emulation mode in response to a signal from the

25

execution unit or a reset. Nowhere is this taught or suggested in Nicolas. Hindsight should not be used to reconstruct the claimed invention using the blueprint drawn by the inventor. Indeed, claimed elements of the present application are not even suggested by the cited references. Therefore the claimed invention cannot be obvious

ih unless hindsight is used w t the claimed invention as a blueprint, supplying the

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Printed 9119194

missing elements. Along with the reasons set forth above, these claims are not obvious
in view of Ntcolas. Claims 14-20are likewise not obvious in light of the argument presented above.

5

o rm Independent claim 14 is directed t a method for processing instructions f o two
separate instruction sets, Independent claim 15 is directed to a method for processing instructions from a CISC and a RISC instruction set in which all CISC instructions are executable, either directly by the execute unit or by emulation with RlSC instructions.

10

Indtpendent claim 1 is directed to a microprocessor for executing RISC and CISC 8 instructions using both RISC and GlSC instruction decoders and an enabIe means to enable one of the instruction decoders Emulation mode is entered if a CISC instruction
I

decode unit is not able to fully decode a ClSC instruction, but the microprocessor directly executes the ClSC instruction if it is decodable. Emulation mode uses a RISC
15

instruction decode unit. Nowhere in the cited references is this combination taught or even suggested.

In view of the above, it is submitted that claims 1-20, as amended, are in a position for
allowance. Applicant requests that the requirement for formal drawings be held in
20

abeyance until allowance. Applicant believes that a full and complete response to the

officeaction has been made. Reconsideration and re-examination is respectfully
requested. Allowance of the claims at an earIy date is solicited.

If the Examiner believes that a telephone interview would expedite prosecution o f this
25
application, he is invited to telephone the undersigned at [phone].

Stuart T. Auvinen 429 2 t Avenue 6h Santa C w , CA 95062

[phone] [phone] Fax

Stuart T,Auvinen Agent for Applicant Reg. No. 36,435

r
Serial No: 08/179,926 Fit& Date: 1/11/94 Examiner:

Docket

v, VU

GAU: 2315

I

statement previously submitted.
NO

additionat fee is required. Add'l Fee remain. Amendment prev. paid for
Minus MinW

Cl

The fee has bean calculated ax shown below: Rate Add'l Fee

Totai Indepen
dent

First Presentation of Multiple Dep. Claim

I

x $37
4- $115
~

Total

iI

A check in the amount of $

to cover these fees is enclosed
for these fees. A

1 Please charge my deposit account No. 01-2950 in the amount of $ 1 duplicate copy of this sheet is enclosed.
4 )!

The commissioner is hereby authorized to charge payment of the following fees associated with this commudlcationor credit any overpayment to deposit account No. 01-2950. A duplicate copy of this sheet is enclosed. b Any additional Nn fces required under 37 C.F.R. 8 1.16. ig Any patent application processing fees under 37 C.F.R. $ 1.17.

$

Respectfully Submitted,

Reg. No. 36,435 Agent for Applicant