Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 9

Dockets.Justia.com

..

RM-1
5

Filed: 1111/94 For: Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode
10

1 1
) ) )

15

Hon. Commissioner of Patents and Trademarks

Box AF
Sir:

Washington, DC 20231

20

This is in reply to the Examiner's Answer of 11/9/95.

Several new points of argument were raised in the Examiner's Answer, and two new references were cited as background skill level.

'/

2

'PORTNOVA IS NOT A SIMULATOR' e response section of the Examber's answer, page 6, last 2 paragraphs', Examiner

as a new point of argument2 that "portanova is NOT a simulator":
'Appellants dege that Portanova dots not teach the claimed invention because Poaanava is a simulator and does a t execute CISC lastruction~, o Tbe exemincr disagrees. Tbe fact tbat Powva'a's system can execute CISC gtmu&m~, w e h r by software emulation or hardware emulation, and produce real results hte clearly shows that Poaaoova is NOT a simulator."

10

However,

states "The designer then writes the CISC instruction $Zd&?X

using RISC instructions, as described in the example above." (col. 30, lines 55-57, over and over again uses various forms of the word emphasis added)

fie "emulate". Webster's New World Compact School and Ofc Dictionary (1989)
defines "emulate" as "to hitate" while "simulate" is defined as "to look or act like",

15

"to feign". Appellant finds very tittle difference in meaning between "emulator" and himself calls his own system an "emulatof"' It is absurd to "simulator". Portan~&2 state that EQ&uQ!& is an "emulator" but not a "simulator".
The fact that "real results" are produced by a simulator, emulator, or computer is

20

irrelevant, What "real results" does

's system, or any other computer system

produGe 1 Binary Numbers. A person could write a BASIC computer program and produce the same binary numbers that Bortanovg's emulator, or DEC's VAX produces. I'roducing 'real results' does not mean that Portsnovi! is NOT a simulator or emulator.
25

The fact that pprtanova is an emulator drives to the heart of this appeal: the complete,

total absence of prior art showing both RISC and CISC hardware execution, Some

computers, such as the 'prior art' CISC systems cited in portanova, have hardware which executes ONLY CISC instructions, Other computers execute ONLY RISC
instructions. portanova is an example of a RISC computer that can 'emulate' CISC
30

instructions by first
I

them to RISC instructions, portanoq is a RISC

Locatiom arc approximate sinrX no line numbers were provided on the Examiner's Answer

3

computer.

ONLY executes RISC instructions. Some of these RISC

instructions may have been ?tanslated from CISC instructions, but they are still only RISC instructions. JWRTANO EXECUTES ONLY RISC MSTRUCTIQNS. Vt$
5

The Examiner uses the term "hardware emulation' in a way not recognized by artisans. Hardware emulation refers to IC design tools such as hardware accelerators, made by
%OS and Quicktun, for simulating complex logic on a hardware accelerator which is

normally simulated by software. Indeed, "hardware emulation" is a contradiction: emulation is something which is done by software, not by hardware. When hardware

IO

exists, there is no emulation. Thus "hardware" is the antithesis o f "emulation". Combining these two words together as the Examiner does is improper and deceptive as the t r "hardware emulation' does not appear in the cited prior art. em discusses Prior-Art CISC computers, Portanova E a i e believes that since xmnr is suggesting that his `preferred' embodiments' be modified to directly execute in hardware CISC instructions on his RISC processor. However Portanova emulates CISC instructions 88 clearly disclosed in his preferred embodiments. Of course, all of I s discussion about writing software emulation routines of RTSC instructions is then irrelevant if the Examiner's modification is made. Why hire a b u c h of software programmers to write emulation code when you canjust execute those CISC instructions 7 Another new pint of argument4was raised in the fmt paragraph of page 7.of the

15

20

E a i e ' aaswer: xmnrs
2s

feachins in Portanova which suggests hardware execution of CISC instrucrions."
This refers to page 8, lines 19-24 of the appeal brief

`Appellants also allege,

i the identification of points of disagreement, that appellauts fail to find n

* Examiner has not before BdocTtcd that Portanova is not a Simulator. The argument that real results
d & a simulator le also new. e The argument that Rortanova'spreferred embadhrents do not contain the suggestion appears new. `This partial qwation from the Appeal`Brief is used for a new argument.

s o -

,

-.
I

4
mggexts bardware execution of CISC fnstructioos i an n Excuniner bclie~rs that appears somnvhere incol29-30. Appellant has twn &envise RTSC proamor. ?his unable to fmd this suggestion aod ha8 nquested that the Examiner specifically point out w a he ht is dying on.

C
J

The appellant's brief has been partially quoted in a misleading way. Portanovg does suggest hardware execution of CISC instructions in a CISC urocessor. Portanova does not suggest hardware execution of CISC instructions in an otherwise RISC Drocessor. Certainly old prior-art CISC computer suggest and indeed are examples of hardware
10

execution of CISC instructions. But these old CISC computers do not execute those CISC instructions in an 0therwise RISC Drocessor
Irtdeed, Examiner has never pointed out a specific line in Portanova which suggests that

15

software emulator be replaced with CISC hardware execution i n portanovg's RISC computer. &xtanova does suggest that his software emulator could
-s

replace these prior-art CISC architectures. Indeed, portanov3 claims that he can emulate in software on his RISC computer any number of CISC architectures, such as

Z8000,68000, VAX, and S y s W 3 7 d .
20
The des@ method disc1oscd herein applies t any number of CXSC iastruction.sets including o MMTD-1750, VAX, NEBULA,etc. The approach i to first build a singie-level control s @ardwireb) usbig RISC design philosophy. In so doing, the designer attempts to maximize execution of the RISC (bardwired) instructionset. (~0130, 48-54emphasis added) lines

Of course,
25

does not have 4 CISC instruction decoders as well as his RISC

instruction decoder. Egrtanovg does not even have 1 CISC instruction decoder. But

can write 4 dHerent C SC emulation routines and run any of these 4 I software emulators on his single NSC bardware. Since the 4 CISC emulators translate all CISC instructions into RISC instructions, only one RISC decoder is needed. Adding 4 CISC hardware decoders is not `SpeCuIation' any more t a adding 1 CISC hardware hn
30

decoder is `speculation'. Examiner is correct that it is untrue that Portanova teaches 4
CISC decoders on his RISC computer. It is also untrue that Portanova teaches 1 CISC decoder on his RISC computer.

The argument that i t i speculaion that 4 CISC decoders are needed is new. s

5

`THIS IS NOT THE ONLY WAY'
bother new point6 is raised at the b t o of page 8 and top of page 9 of the otm Examiner's Answer.
5
Portma epecifically chooses the design that employs software emulation by using native RISC btructiom to execace CISC instrucdons as set forth inhis third embodiment to m e his design et goat. However, this ls NOT &e ONLY way. Poaaoova clearly suggests other alternatives design approaches t implement CISC architectme lanown in the prior art (see figures 9-13). o

10

portanova discloses 2 ways to process CISC instructions: Use a Prior-Art CISC computer (coi 29-30, Figures 9-13). 1. Use his RISC computer with a software program that emulates CISC 2. instructions by replacing them with IUSC instructions.
does NOT disclose a third way:

15

3.

Add CXSC hardware to a RISC computer and execute either CISC or RISC

instntctions. Appellant's specificationdiscloses this third approach. Examiner has used improper

hindsight to choose the Wtd way from appellant's disclosure over the other two ways

20

fairly disclosed by the prior art. Examiner has brought out furtber points of argument to dispute the clear statements in

portanaVa that teach away. F t it is now asserted that appellants do not properly i
construe'

(&miner's answer, page 9).

25
Such

A p p e W ap~ar wggta that since the proposed modification contradicts Portanova's third to embodimtn,such modificatfon Coutd not be made.
I .

are evidence that the reference &aches awav firom the proposed

modifiiation.
30

'"he argument that appellants improperly conztrue Portanova and do not consider every word and figure
is new.

Thc argument that Portanova's teaching i s not the only way is new.

6
b

When a proposed modification destroys the intended purpose of the reference, that modification is in error and cannot be made. The intended purpose of faster design time
is destroyed by adding CISC hardware to portanovg's RISC computer. The software

routines to emulate CISC instructions decrease design time compared to hardware CISC
5

execution because it is faster t write software than it is to design hardware. Thus a o modification to add CISC hardware increases design time and destroys the purpose of Portanov8. The modification cannot be fairly made.

I

It is also insinuated that appellants considered ody the preferred embodiments and not
10

"every single word and figure of the reference.' Appellants have asked the Examiner to point out what `word' contains the suggestion to use CISC hardware execution on a 1 .

RIS$p_essor. The Examiner has not found such words in the reference.
d

It is finally asserted that appellants have not considered the level of ski11 in the art. To
15

bolster this argument, two new references were cited'. The newly-cited IBM disclosure again shows CISC instructions being `decoded and translated' to RISC instructions. The

RISC instruCtioos are then decoded and executed. The new

reference shows microcode program selected based on `architecture modes'. However, then: is still NO

TEACHING WHATSOEVER in cited prior art of CISC hardwarrx-F-tion on a RISC __. --20

computer. The level of skill in the art for c o m b m g RISC and CISC hardware is

ZERO.This is an entirely new area.
Why can Por$xlova emulate any of the Prior-& CISC architectures ? Why can portanova cut his Design Time ? 25 The answer is that &rtamva emulates in software CISC instructions. fairly teaches. never n executes i hardware CISC instructions on a RISC processor. That is what P o r n o v a

-

c

a These referencur are new.

7

For the foregoing reasons, Appellant submits that the rejection of claims 1-20 is i n error and should be reversed on appeal.

5

Stuart T. A u v h n

429 26th Avenue Santa C m , CA 95062 [phone] [phone] Fax

Stuart T. Auvinen Agent for AppelIant Reg. No. 36,435