Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 6

EXHIBIT G

Dockets.Justia.com

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Serial No. 00/179,926
PART III: DETAIL OF ACTLON

1.

This office action responds to applicants' amendment filed on

February 16, 1995. Claims 1-20 remain pending. 2. The text of 35 U.S.C. S 103 cited in the first office action

is hereby incorporated by reference.

3.

The rejection of claims 1-5, 14-16 and 18-20 under 3.5 U.S.C. (hereafter

5 1 0 3 as being unpatentable over .Portanova et a1

Portanova), U.S. pat. no. 4,992,934 in view of Onishi, U.S. pat. no. 3, 764,988 set forth in the previous office action mailed November 16, 1994 is hereby incorporated by reference. 4. The rejection of claims 6-13 and 17 under 35 U.S.C. 5 1 0 3 as

being unpatentable over Portanova and Onishi and further in view of Bullions, I11 et a1 (hereafter Bullions), U.S. pat. no. 4,456,954 set forth in the previous office action mailed November 16, 1994 is
*

hereby incorporated by reference.
5.

All pending claims are rejected in this office action.

Applicants' arguments filed on February 16, 1995 have been fully considered but they are not deemed to be persuasive.

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Serial No. 08/179,926

6.

As to the remarks, applicants argue that the claimed invention

is not obvious over the applied arts of record for the following reasons: a) Portanova's disclosure is not enabling because Portanova teaches only software implementation to emulate CISC capability in a RISC-core processor and that Portanova fails to teach the detailed hardware implementation of CISC emulation. b) Onishi's teaching is directed to a different problem. c) there is no reason to combine Portanova and Onishi. d) Bullions' teachings cannot be combined with other references to render the claimed invention obvious. Regarding point a, it is submitted that applicants' argument that Portanova's disclosure is not enabling is without merit because the reference does not have to be enabling its entire contents in order for the reference to be used. Indeed, any piece of teaching or suggestion in the reference can be very well applied against the present claimed invention provided that such teaching or suggestion is within the level of ordinary skill in the art. Applicants are reminded that 35 U.S.C 112 first paragraph is to be applied to the claims and not to the reference. There is absolutely no precedent case law to support the allegation that the reference must meet 35 U.S.C 112 first paragraph to the extent as applicants asserted before it can be applied against the claims. Indeed, like the present application, the reference obligates to
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Serial No. 08/379,926 provide enabling disclosure only to what being claimed, not to what not being claimed. Returning to the Portanova reference, Portanova explicitly teaches an exemplary system that employs software implementation of
C I S C emulation in which each guest CISC instruction is emulated by

a series of host RLSC instructions. Portanova, however, clearly suggests that hardware implementation of CISC emulation could have been done as an alternative approach (see col 29, line 60 line 12). art.

-

col 30,

The question now is whether or not such alternative

approach can be done regarding the level of ordinary skill in the Portanova clearly shows different well-known approaches to implement the CISC (see figures 9-12). Applicants assert that such approaches are applied only to single instruction set, i.e. CISC, and not to processor supporting both RISC and CISC. This argument fails because Portanova suggests the implementation of CISC in the context of dual-instruction-set processor and not singleinstruction-set processor, i.e., such approaches are suggested to implement the CISC part of the processor. Moreover, to the extent of employing hardware implementation to execute a sub-set of instructions, Onishi teaches a system that employs two instruction decoders, one for normal instructions and one or branch instructions. The use of two decoders as opposed to one decoder in a conventional processor allows the system to decode instructions more efficiently because decoding of a branch instruction usually
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Serial No. 08/179,926 takes longer than that of a normal instruction. Tanenbaum further teaches that considering either hardware or software implementation is a matter

of design choice since hardware and software

implementations are indeed interchangeable. Further evidences of hardware implementation as opposed to software implementation can also be seen in two newly cited references, Lee et a 1 and Agnew et al. Both references clearly teach that the execution of a sub-set of instructions can be implemented with either hardware or software (see abstracts in Lee et a1 and Agnew et al). Thus, in light of level of ordinary skill in the art as evidenced by the above cited arts, it is again submitted that employing wholly or partly hardware implementation to execute the guest instructions (CISC) in Portanova could have been done and such hardware implementation approach would have been obvious to one skilled in the art at the time the invention was made. Here, although the detail of hardware implementation for executing CISC was not specified by either reference, to the extent of the scope
_ I I _

of the claims

to design

aprocessor capable

o executing dual f

instruction sets where a subset of second instruction set is implemented partly with hardware, the 'teachings and suggestions from the applied references sufficiently meet the claim limitations. It is further noted that although these teachings of the applied refxenCes may no longer be sufficient in considering further detail of the implementation of the CISC emulation in a
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#

Serial No. 08/179,926 dual-instruction-set processor, applicants however have failed to point out the details in the claims that define the invention over the prior art. Regarding point b, the examiner submits that applicants attempt to show non-obviousness by using piecemeal analysis of the references. Applicants are reminded that one cannot show nonobviousness by attacking references individually where, as here, the rejections are based on combinations of references. Regarding point c, it is submitted that the combination o f the reference is clearly motivated by the explicit suggestion from Portanova to implement CISC emulation wholly or partly with hardware (see Portanova, col 29, line 60 9-12)

.

- col 30, line 12, figures

Regarding point d, the examiner again submits that applicants attempt to show non-obviousness by applying piecemeal analysis of the references in which applicants construe each reference narrowly to a specific application. In contrary to applicants' assertion, it is submitted that Bullions' teaching of using a translation look-aside buffer to address emulated instructions is not to be applied exclusively to CISC type processor. It would have obvious that Bullions' teachings can also be applied to other processors including the dual-instruction-set processor taught by Portanova. In summary, it is submitted that applicants' rationale of nonobviousness was made by improperly ignoring skill level in the art.
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Serial No. 08/179,926 Applicants have made arguments of non-obviousness based solely on what was explicitly taught in the references and what was not explicitly taught in the references.

In the contrary, it is

submitted that the claimed invention was clearly rendered obvious by the teachings and suggestions of the applied art of record as set forth in the previous office action and the above discussion.
7.

The following references are cited by the examiner as of Agnew et al, U.S, pat. no. 4,514,803: methods f o r partitioning

general interest. a. mainframe instruction sets to implement microprocessor based emulation thereof. b. Lee et al, U.S. pat. no. 4,763,242: computer providing flexible processor extension, flexible instruction set extension and implicit emulation for upward software compatibility.
8.
THIS ACTION IS MADE FINAL.

Applicant is reminded of the

extension of time policy as set forth in 37 C.F.R. 5 1.136(a).

A SHORTENED STATUTORY PERIOD FORRESPONSE TO THIS FINAL ACTION IS SET TO EXPIRE THREE MONTHS FROM THE DATE OF THIS ACTION. IN THE EVENT A.FIRST RESPONSE IS FILED WITHIN TWO MONTHS OF THE MAILING DATE OF THIS FINAL ACTION AND THE ADVISORY ACTION IS NOT MAILED UNTIL AFTER THE END OF THE THREE-MONTH SHORTENED STATUTORY PERIOD, THEN THE SHORTENED STATUTORY PERIOD WILL EXPIRE ON THE DATE THE ADVISORY ACTION IS MAILED, AND ANY EXTENSION FEE PURSUANT TO 37 C.F.R. § 1.136(a) WILL BE CALCULATED FROM THE MAILING DATE OF THE ADVISORY ACTION. 'IN NO EVENT WILL THE STATUTORY PERIOD FOR
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Serial No. 08/179,926
RESPONSE EXPIRE LATER THAN S I X MONTHS FROM THE DATE OF THIS FINAL ACTION.

9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to V. Vu whose telephone number is [phone].
I
Any inquiry of a general nature or relating to the status of this application should be directed to the Group receptionist whose telephone number is [phone].

v. vu

Art Unit 2315 3/31/95

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TO SEPARATE. NOLO TOP AN0 BOTTOM EDGES, SNAP-APART AND D'FCARO CARBON

N T A N 0 TRAOEMARK OFFICE

NOTICE OF REFERENCES CITED

* A COPY of this reference is nothing furnished with this office action.
(see Manual of Patent Examining Procedure, section 707.05 (a).)