Goodard v. Google, Inc.

Filing 157

Goodard v. Google, Inc.

Doc. 157 Att. 8

Dockets.Justia.com

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IN THE UNITED STATES PATENT @D TRADEMA= OFFICE I ) BEFORE THE BOARD OF PATENT APPEALS AND I N ~ ~ ~ N C \ E §
In re application of Blomgren et al. Serial No. 08/179,926

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Examiner: V. Vu
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Group Art Unit: 2315

Filed: 1/11/94
For: Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode
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1
) ) ) )

R 37 C.F.R. 8 1.192
15 Hon. Commissioner of Patents and Trademarks Box AF Washington, DC 20231
Sir:

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This is 8n appeal from Examiner's final rejection of claims 1-20, contained in the third
office action mailed 4/5/95. notice of appeal was filed, together with an The

authorization to charge the fee to my deposit account, on 7/3/95.

070 DF 09/06/93 08179926

1 220

140.00 CK

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This appeal brief is being filed within 2 months of the notice of appeal. Attached is a check for the fee under 37 C.F.R. application. 5
The commissioner is hereby authorized to charge payment of any patent application processing fees ih under 37 C.F.R. 4 1.17 associated wt this communication or credit any overpayment to deposit account No. 01-2950.

1.17(0, (fee code 220) for filing the Brief on

Appeal of $ 140.00. Small entity status has previously been established in this

STATUS OF THE CLAIMS
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Claims 1-20 are pending and on appeal. STATUS OF AMENDMENTS AFTER FINAL REJECTION
An amendment after final rejection was fied on 5/22/95 and was entered by the

Examiner as noted in his Advisory Action of 6/6/95, The Examiner indicated that the amendment did not overcome the rejections. 15

SUMMARY OF THE INVENTION
The invention is a dual-instruction-set processor (CPV). A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC" RISC (reduced instruction set computer) code. (abstract) While current CPUs typically execute just one instruction set, the invention allows execution of two instruction sets.

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Additional hardware is minimized by sharing a single execution unit but having two instruction decoders. Hardware cost and complexity is fbrther minimized as onIy a
subset of the x86 instruction set is decoded while the entire PowerPC" instruction set

is decoded.

Claim I Summary
25 Claim 1 recites a fust and a second instruction decoder (36) for decoding instructions

f o a first and a second instruction set. Only a subset of instructions from the second rm

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instruction set is decoded. A select means (46) selects either the decoded instruction from the first decoder or from the second deeoder. An execute means (48) executes the decoded instruction selected by the select means. Thus the execute means can execute both first and second instructions provided by the select means.
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Technology Tutorial - Figure 2, Appendix 2
Appellant 's Figure 2 (reproduced in Appendix 2) shows that instructions are fetched and supplied to a RISC instruction decoder (RISC ID 36) and a CISC instruction decoder (CISCID 36). Either the decoded RISC instruction or the decoded ClSC

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instruction is selected by mux 46 and output to execute unit 48. Note that both RISC and CISC instructions are executed by the execute unit 48. While the entire RISC instruction set i s decoded and executed, only a subset of the CISC instruction set are decoded and executed.

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A mode register 38 contains a RISClCISC bit (WC) which causes mux 46 to select
either the decoded RISC instruction or the decoded CISC instruction. A miss from translation-lmkaside buffer (TLB) 52 or an undecodable/unknown CISC instruction 40

can cause mode control 42 to switch mode register 38 to RISC mode from CISC mode.
Subject of ~ % p e n d % n ~ 2-13 CIBims
20 Claim 2 recites that the single instruction fetch buffer 32 feeds instructions to both the

RISC and CISC decoders 36. Rather than duplicate the entire pipeline, the instruction ny fetcher, execute unit, and TLB are shared among both instruction sets. O l the CISC decode logic is added. The mode register is claimed in ctaim 3; the mode control in
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claim 4. An undecodable instruction switching the mode register is the subject of claim

5. A TLB miss switching the mode control and thus the instruction set decoded is the
subject of claim 6 , In claim 7 a handler routine of ftfst instructions is executed when the mode control is signaled by an undecodable second instruction or a TLB miss.

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In Claim 8 an exception from the execute unit causes the mode control to change to decoding the first instruction set. Claim 9 recites that all references to main memory from the second instruction set are translated by the TLB, but claim 10 reveals that only first instructions can load the TLB. In claim 11 extended first instructions modify

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TLB entries. In claim 12 first instructions are decoded following a reset, while claim
12 recites that extended instructions are decoded only when the mode control is signaled to change to the first instruction decoding, or immediately following a reset.

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Since two separate instruction sets are used, a fetched instruction word could output

two different but seemingly valid decoded instructions, The RTSC decoder and the
CISC decoder could each output a seemingly valid decoded instruction. This is not true for a single instruction set or extensions to a single instruction set. The 386 and 486 instruction sets do not meet claim limitations for separate instruction sets since the 486
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set is a mere extension of the 386 set, having most opcodes in common.

Independent claim 14 is directed to a method for processing instructions from two
separate instruction sets. Independent claim 15 is directed to a method for processing

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rm instructions f o a CISC and a FUSC instruction set in which all CISC instructions are
executable, either directly by the execute unit or by emulation mode with NSC instructions. Claim 16 adds that the emulation routine uses RISC instructions and extended

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instructions, while claim 17 recites that memory references generated by the CISC instructions are translated under control of a translator routine of NSC instructions which load a TLB.

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Apparatus Claims f8-20 Summary

Independent claim 18 is directed to a microprocessor for executing RISC and CISC instructions using both RISC and CISC instruction decoders and an enable means to

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enable one of the instruction decoders.. While the entire RISC instruction set is decoded, only a subset of the more complex

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CISC instruction set is decoded, Dependent claim 19 recites that the undecoded CISC instructions are emulated by an emulation mode, while the mode register indicates RISC, CISC, or emulation mode.
ISSUES The issue is whether the obviousness rejections are proper. In particular, the reference was cited by the Examiner as `suggesting' but `not explicitly teaching' claim limitations. Appellant has shown that this `suggestion'does not exist, and cannot

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possibly exist, because the `suggestion', Any modification of

reference explicitly teaches away from such a using this `suggestion' destroys the

purpose explicitly stated by Portanova. Under 35 USC 20

9 103, claims 1-5, 14-16, and 18-20 were rejected as obvious over

Portanova et & (US Pat. No. 4,992,934) in view of anishi (U.S. Patent No. 3,764,988). Claims 6-13 and 17 were rejected under 35 VSC 0 103 as obvious over

Portanova

in view of

as set forth for claims 1-5, and further in view of

V (U.S. Patent No. 4,456,954).
GROUPING OF CLAIMS
25 The claims do not stand or fall together.

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Although the claims each differ in scope From one another, Appellant has grouped several claims together for administrative effciency . All claims rely on the basic argument present below for independent claims 1, 14, 15,

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and 18. Additional arguments are presented for dependent claims 6-13 and 17 which further include a TLB. Other specific arguments are presented at the end of the argument section for other claims. Thus the claims are grouped as:
A,)

Claims 1, 2, 14 (with additional arguments for claim 2) Claims 3, 4, 18, 19 (with additional arguments for claim 19) Claims 6 , 7-13, 17 (with additional arguments for several of claims 7-13) Claims 5, 15, 16, 20 (with additional arguments for claim 16)

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B.)
C.)

D.)

Group A claims the basic structure of the dual-instruction-set decoders and select for
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the single execute unit, with only a subset of the CISC instruction set decodable. Group

B M e r contains the mode register with the instruction-set-indicatingbit. Group C
further includes the TLB.Group D specifies that undecodable CISC instructions cause the instruction set decoded to switch.

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All claims were rejected using the

reference as showing both RISC and

CISC hardware execution. The other references, anishi and Bullions, execute only one instruction set and are used as secondary references,

Portanova is a RISC processor that emulates or simulates CISC instnictions by
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replacing each CISC instruction with a routine of several RlSC instructions. The claimed invention is not an emulator but directly executes in hardware both RISC and CISC instructions
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Portanovais a CISC emulator while the invention is not an emulator but instead
executes a subset of CISC instructions directly in hardware. This major difference is brushed aside with such statements as usoftware and hardware implementations are indeed interchangeable."(third action, page 5, lines 3-4) The new term "hardware

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emulation" has been coined by the Examiner (second action, page 5, line 11) to further blur the distinction between hardware execution and software emulation. Simple statements that software and hardware are interchangeable belittle the complex art of microprocessor design. Such simple statements fail to teach or suggest the claimed structure of a single RISC and CXSC execute unit but separate decoders.

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~ ~ r n uvs, ~ ~ o ~ l Actual

a Execution - an~ ~ Analogya

~

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An analogy highlights the absurdity of this position: Airplane pilots learn how to fly a

plane in trainers called aircraft simulators. These are large boxes with realisticappearing controls that the pilot operates. The box may be supported by hydraulics to
~

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simulate rocking movements of the airplane. The pilot appears to be flying the real

s airplane. However, there i one big difference

- if the pilot crashes the simulator, he

opens the door and walks out. IF he crashes the airplane, he's dead.

Portanovais a simulator. The invention is not a simulator. Portanovamay appear
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similar to the invention, even being called a `dual-instruction-setprocessor', but

Portanovadoesn't execute CISC instructions. He emulates them much as the ffight
simulator emulates aircraft flight though the rocking motion of the box. The invention actually executes instructions much as an actual airplane moves through the air.
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The invention actually executes in hardware two entirely independent instruction sets. The inventors have realized that only frequently-used instructions from the second instruction set need to be decoded and executed in hardware since the less-frequentlyused second instructions can be emulated if needed. Thus only a subset of the second

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instructions need to be hardware-executed while all of the first instructions are hardware-executed.

Portanova teaches a RISC processor used to emulate any one of several existing CISC
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architectures. of the CISC instructions are hardware-executed. A CISC design methodology i s disclosed whereby a RISC i s designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication. (Abstract)

i d e n ~ c ~ t i o nPoints of Agreement of
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Appellant believes that both parties agree that Portanovadoes not

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emulates all hardware execution of both RISC and CISC instruction sets. l?Q&m?U CISC instructions with routines of RISC instructions. Examiner acknowledges that explicitly teaches an exemplary system that employs software
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implementation of CISC emulation in which each guest CISC instruction is emulated by a series of host RISC instructions." @age4, lines 3-5, third action) Appellant understands this statement to mean that Portanova explicitly teaches only RISC hardware execution and only CISC software emulation.

Identification of Points of Disagreemenf
20 Examiner believes that Portanova suggests hardware execution of CISC instructions in

an otherwise RISC processor. T i Sueeestipn appears somewhere in col29-30. hs
Appellant has been unable to find this suggestion and has requested that the Examiner specifically point out what he is relying on. 25

Portanova Cannot Suggest CBC ffanfware Execution on His W/SC CPW
Appellant asserts that the CISC embodiments of col; 29-30 are n o m more than prior-art CISC-only architectures that can emulate. Indeed, these CISC architectures are labeled "prior-art" on the corresponding Figures 9-12 because they

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are nothing more than old processors decoding and executing just one instruction set. clearly is discussing prior-art design approaches: 5
"Using current methods, the designing of a CISC could take several different forms. A first approach would be to implement all instructions using single level control." (col. 29, lines 6265)

"Using current methods" is a clear statement that what FQ W M is discussing is prior !X E has invented a new method or art, a "current" method or methodology.

.

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methodology is a "third aspect" of his invention (col methodology. Indeed,this 29, line 60).He fmt discusses current (prior-art for ) methods or design approaches that have been used for Zilog's 28000, Motorola`s 68000, DEC's VAX, and R3M's S/370 (col29, line 64 to col 30, line 38). He finishes by discussing BM's

S/370, which he states is a 'prior art design using an approach..." (col 30, line 29-30).
Then he leaves these prior-art methodologies and discusses the ``third aspect" of his
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invention, a new "design method" (eo1 30, line 39-40, 48).
Cited Section Simply Describes Old CISC Processors

These well-known CISC architectures are presented in the "Design Methodology"

section at the end of the
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reference to show that Port;tnava'sRISC processor

can be used to implement any of these well-known CISC architectures:
The design method disclosed herein applies to any number of CISC Instruction sets including MIGSTD-1750, VAX, NEBULA, etc. The approach is to first build a single-level control (hardwired) wing RISC design philosophy. In so doing, the designer attempts to maximize execution of the RISC (hardwired) instruction set. (col 30, lines 48-54 emphasis added)

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The fact that one RISC processor can implement so many different CISC architectures indicates that CISC-specific hardware is not used. If CISC hardware was used on

Eortanova's processor, then this CISC hardware has to be different for each of the
CISC architectures. A CISC VAX cannot execute Motorola 68000 CISC instructions 30 since they are entirely different instruction sets, with different encoding of opcodes. An instruction decoder for the VAX instruction set could not decode 68000 instructions.

Each CISC architecture requires a diflerent instruction decoder. This decoder is part of
the hardware on the processor.

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have four different CISC decoders for each of the 28000, 68000, De os VAX, and Systed370 CISC instruction sets ? Of course not. Each CISC instruction set is decoded by selecting software emulation routines. These routines can be re-

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written for each of the different CISC instruction sets. Since these routines are software, and not hardware, the design time is reduced.
Portanova's Advantage is Faster Design Time Than Prior-Art ClSC

Indeed,
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asserts that it is faster to use his methodology than to build a CISC-

only processor. His methodology is to first design a RISC-only processor, then to write emulation code to implement the CISC architecture. Since writing computer Code is faster than designing and fabricating hardware, Partanova's design methodology is faster that designing a CISC processor:
The

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h e . For axaarple, it is known i the art that the Fairchild F9450,M 3 8 took n I21 longer than three y a w to develop. Using the present approach, the MIL-STD-1750 RISC emulator took 1 than one year with only o trip to the silicon factory needed to achieve w

CIS

for taking this approach is the RISC design time is much, much less than the

certification. (~0130, s 5 8 6 4 , emphasis added) lk

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$ ~ c & t ~Destroys Portanova's Purpose on
If ParZanovaadded one or more CISC decoders to his RISC-only hardware, then his design time increases. This destroys the rationale for his design approach that he explicitly states as quoted above at coI. 30, line 58. A modification to a reference

'

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cannot be made if that modification destroys the intended function or purpose of the reference.

l?mWma requires the modification of adding a CISC hardware decode unit at a bare
minimum. Adding this CISC hardware decoder and its control logic significantiy 30 increases design time. I f the design time for the CISC decoder were onIy 1/3 o f the

total design time, then adding just the CISC decoder adds one year to the design time

- doubling the desigri time from one year for RISC-only, to two years.

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Not only does design time increase, but adding the CISC decoder also destroys
-'s
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purpose of a design method that applies to any number of CISC instruction

sets. Once the CISC decoder is added to the RISC hardware, then the hardware is specific to just one CISC instruction set. lik&mxa's processor would no longer be able to emulate any number of ClSC instruction sets. Thus adding a CISC decoder to
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destroys his purpose of reduced design time

and also his purpose of emulating any number of CISC instruction sets. The Federal Circuit has consistently held that when a

0 103 rejection is based upon a

modification of a reference that destroys the intent, purpose or function of the invention disclosed in the reference, such a proposed modification cannot be properly made. In

Re ffordon, 733, F.2d 900, 221 USPQ 1125 (Fed. Cir. 1984). portanova's intent is
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clearly stated as reducing design time (col. 4, lines 3-13, c01. 7, Iines 37-65). Another intent is to emulate any number of CISC instruction sets (col30, lines 48-50). Both intents are destroyed by the modification of adding a CISC hardware decoder as proposed in the rejections.
Explicit Teaching & Suggestion Lacking from Partanova

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The references clearly do not teach hardware execution of two different instruction sets. The Examiner agrees that hardware execution of two instruction sets is not

..

@age 7, first paragraph of action) but is

However,

Appellant is unable to find any language in the cited page (col29 - col30) of the

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reference containing this suggestion. In Appendix 3, Appellant discusses each of "prior-art" Figures 9, 10, 11, and 12 in the cited page, and is not able to find any such suggestion or teaching that a hardware pipeline could execute two native instruction sets. Instead these Drior-artfimtres are simply prior art. They show existing CISC
' architectures that can be emulated in software. &aamyu RISC processor can be used

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to

these CISC instruction sets for several well-known CISC

architectures, such as 68000,V U , S1370. It is not reasonable that a prior-art VAX combined with
5 ' RISC emulating

CISC suggests a single execute unit executing both RISC and CISC. Instead clearly teaches software emulation of CISC by RISC, so the CISC VAX i s

~ e a c ~ ~ s w Design RlSC fst, then code ClSC e ~y
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-

clearly he teaches a two-step process:
1.)

from hardware execution of both RTSC and CISC when

2.) of Figures 9-12 (col30, lines 39-64, abstract).
15 clearly states this sequence:

for CISC. The RISC hardware is frrst built Thfn the software emulator is written for any of the CISC architectures

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"the designer attempts to maximike execution of the RISC (hardwired) instruction set. Once the RlsC is hardware deal@& it can be sent to the factory for reduction to silicon. The designer then wrttes the CISC instruction emulator using RISC instructions, as described in the example above. (~0130.l n s 52-57, emphasis added) ie

Hardware execution REQUIRES that CISC be considered when the hardware is designed, before being sent to the factory. Designing CISC hardware with RISC hardware requires the process of :
1.)

The RISC hardware is first built y&h CISC hardware.

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2.)

A software emulator is written or instructions not in the decodable

subset of CISC insmctions. This method slows down the design process since step 1 is now much more complicated. I all CISC instructions (not just a subset) are executed in hardware, then step 2 is not necessary at ail. Clearly this process is not what Portanova teaches or

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suggests.

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Identification of Basis forSuggestion Requested If such language suggesting hardware execution of two instruction sets exist, Appellant has requested that Examiner explicitly point out and y&g&g it occurs in,

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rather than broadly referring to a page with four prior-art figures. This helps defrne the issues for appeal and ensures that Appellant and Examiner are not "discussing two completely different cases" (PTO Day 1994, pages 357-9). Something in the Prior art must suggest the desirability of making the combination

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(Uniroyal, Inc. v. Rudkin-Wiley Gorp., 837 F.2d at 1050-51, 5 USPQ2d at 1438). The
claimed invention must not be used as a blueprint. Since the suggestion dws not appear in the reference as cited in the rejection, the suggestion must come from another source. Appellant Is claims are apparently that source. If no suggestion can be pointed out in Portanova,then the rejection is in error and should be overturned.

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SPECIFIC RESPONSES TO STATEMENTS IN THIRD OFFICE ACTION For completeness, the following are specific responses to specific statements made in the rejections in the third official action. `Duel-lnstruction-Set Processor' Has DCfferenf

aning fo Portanova

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Examiner asserts (third action, page 4) that Appellant `s argument that Portanova's Figures 9-12 apply only to a single instruction set fails because Bxmwi~~ ' context is a dual-instruction set processor. However,

' definition of dual-instruction-set

processor is one that anula&s CISC by executing IUSC. Appellant 's definition of dual-instruction-set processor is one that executes hnth CISC and RISC. Thus the mere

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use of the term "dual-instruction-set processor" does not change what Portanova
teaches or suggests, unless Appellant 's definition of dual-instruction-set processor is

used as a blueprint.

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Examiner believes that it is within the ordinary skill level to have a single execute unit execute both RISC and CISC instructions. Examiner also believes that it is within the ordinary skill level to modify &&&i2i branch decoder to decode a second instruction set, such as adding a ClSC instruction decoder to a RISC processor. These beliefs are

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not reasonable.
Nowhere does portanova state that any CISC instructions can be directly executed in hardware by his RISC processor. exclusively describes CISC emulation by replacing a CISC instruction with a group of RISC instructions. Appellant asks where such a suggestion exists. Examiner to cite a page and line number in Cited Motivaffon Mot Relevant, Shows a Different Problem, and Points to ~On-O~vio~sn~~~ Examiner's motivation for using OnisM's two decoders is that it "allows the system to

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decode instructions more efficiently because decoding of a branch instruction usually takes longer than that of a normal instruction." (third action, page 4-5)Appellant asserts that branch instructions taking longer to decode is not a relevant motivation to having separate RISC and CISC decoders, since both decode branch instructions. RISC instructions are not decoded more efficiently because of the presence of the CISC

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decoder; indeed RISC instruction decoding may be less Mcient and slower because of the additional CISC decoder tapping in to the instruction fetcher. Thus the motivation provided for combining snishi with portanoVa is irrelevant and not reasonable. The cited motivation shows SWhi to be directed to a different problem.

Onishi Merely Partitions a Decoder for B Single Instruction Set
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With two instruction decoders for two different instruction sets, the same bit pattern or
opcode can be decoded into two different instructions, one for RISC and the other for CISC. Both outputs can be valid operations. Thus the present invention can output

rm valid decoded instructions f o both of the decoders, and one must be selected.

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Appellant `s specification explains how the same opcode, 03 hex, can be two valid operations - CISC addition or RJSC trap-word-immediate:
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This same opcode, 03 hex, corresponds to a completely different instruction i the RfSC n instruction set, In CISC 03 hex is an addition operation, while in RISC 03 hex is TWI trap word immediate, a control transfer instruction, Thus two separate decode blocks are necessary for the two separate insuuction sets. (Spec on page 25, lines 2-6)

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Q&hi partitions a single decoder for a single instruction set into two decoders for
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different types of instructions (branches) within that one instruction set. With Qdi&.i, one of the decoder's outputs is always invalid. The present invention uses two decoders because two separate instruction sets are decoded. Thus Qnhbj does not teach or suggest that a decoder for a RISC instruction set be used with a second decoder for a CISC insteuction set. Certainly anishi nowhere teaches that only a subset of a second,

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independent instruction set is decoded in a CISC decoder.
Scope of the CIaims
-Stated by Examiner

Examiner admits that the detail of hardware implementation was not specified by either reference. However, "to the extent of the scope of the claims to design a processor 20 capable of executing dual instructions sets where a subset of second instruction set is implemented partly with hardware, the teachings and suggestions from the applied references sufficiently meet the claim limitations." (third action, page 5. ) Appellant disagrees that Appellant is merely claiming a "processor capable of
'

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executing dual instructions sets", regardless of whether the second instruction set is wholly or partially implemented in hardware. That is not what the claims state. The claims recite at least a WSC and a CISC instruction decoder, and an execute unit that receives' decoded RISC and decoded CISC instructions and executes both RISC and CISC instructions. Putting a PowerPC"' Mac and a 486 PC on a desk allows execution

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of both a RISC and a CISC instruction set, but does not meet claim limitations of
having the RISC and CISC decoders feed a singre execute unit. Likewise putting

IW~QY& CP.U emulating CISC with a CISC VAX does not teach claim RISC

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limitations. Also a CPU die that has a RISC pipeline in one comer and a CISC pipeline

i another comer does not meet the claim limitations since decoded RISC instructions n
are sent to the RISC execute pipeline while decoded CISC instructions are sent to the CISC execute pipeline.
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, while appearing to uexecute" dual instruction sets, also fails to teach or

suggest claim limitations of a RZSC and a CISC decoder which feed decoded discusses prior-art CISC instructions to an execution unit. The fact that architectures such 8s VAX and 68000 does not mean that he suggests executing both
'

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RISC and CISC decoded instructions on the same execute unit ! specifically teaches that these prior-art CISC architectures can be emulated with his RISC processor. As the official action notes, emulation means replacing a CISC instruction with a plurality of RlSC instructions. Emulation does not mean direct

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execution by hardware. The third official action on page 5 has thus misstated Appellant `s claims. Even without
the limitation of only a subset of the second instruction set being executed by the

execute unit, the scope of the claims is narrower than merely executing dual instruction
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sets. The structure of two instruction-set decoders using a single execute unit is claimed
but not taught or suggested by any cited reference.

`Piecemeal' Attack of References Proper

Examiner objected to Appellant 's analysis of the references, stating that "Appellant s
25

attempt to show non-obviousness by Piecemeal analysis of the references. Appellant s are reminded that one cannot show non-obviousness by attacking references individually where, as here, the rejections are based on combinations of references." (third action, page 6).

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Appellant strongly disagrees. When the Examiner cites a portion of a reference as teaching a claim element, the Appellant can show that such reliance is in error. For example, if an Examiner states that reference P teaches X while reference Q teaches Y, then Appellant can properly argue that reference P does not, in fact, teach X.

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In the present case, Examiner has relied on &&a&mi for a suggestion of hardware
execution of two instruction sets. Examiner states that

``Portanova, however, clearly

suggests that hardware implementation of CISC emulation could have been done as an alternative approach (see col29, line 60 - col30, line 12)." Appellant can properly
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show that Examiner's reliance on the cited portion of the reference to be in error. Appellant has done this by a through analysis of this cited portion of Portanova. Appellant may also show that it is improper to combine references, such as when a secondary reference solves a different problem (laRe Clay, 23 USPQ 2d 1058). Since

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solves the problem of branch decoding by splitting a decoder into two parts, Appellant has pointed out that the branch decoder does not solve the problem of decoding two entirely different instruction sets, such as CISC and RISC. Both of

Qnishi's decoders merely decode different parts of a single instruction set.
Strained Combination of References

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Poaanova fails to provide any detail of CISC hardware implementation, since
i3samya only emulates CISC instructions with RlSC instructions. Examiner has
attempted to rely on brief prior-art descriptions in Portanova of well-known CISC architectures for CISC hardware execution. This attempt fails because Eortanova

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teaches away by showing that the RISC hardware can be used to emulate ANY

NUMBER of these different CISC architectures by first designing generic RISC
hardware without regard to CISC, and then writing CISC emulation code containing RISC instructions. This speeds up his design time.

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References Lack Claim Elements Examiner also cannot rely on these brief prior-art descriptions because they fail to disclose the structure recited in Appellant 's claims. For example, having two

5

instructions decoders (RISC and CISC) but only one execution unit is claimed by the elements of claim 18. &aamya does not disclose a CISC instruction decoder nor an execution unit capable of executing both MSC and CISC instructions. Q&hi is brought in as showing two iasmction decoders, but this fails because Onishi's decoder is merely a branch decoder, and Dot a decoder for a second (CISC) instruction set. anishi

10

simply partitions or divides a single decoder for a singte instructions set into a branch decoder portion and a non-branch decoder portion.

W,l i e
15

,completeIy lacks any teaching or suggestion of an "execution unit, coupIed to said EEG instruction decode means and said W instruction decode means,for executing instructions belonging to said l3EC instruction
set and instructions belonging to said L X instruction set, Xl

whereby instructions from said RISC instruction set and instructions from said CISC instruction set can be executed by said execution unit." (claim 18, emphasis added),
20

'Design Choice' I Repackaged 'Obvious To Try' Standard s

Tanenbaum,Leeetal., and &&w

et Q were added in the third action to further

strain the combination of references. Examiner is using Tanenbaum to suggest that software or hardware is merely a design choice. The two newly-cited references are
25

used as "further evidences of hardware implementation as opposed to software implementation". However, neither reference teaches or suggests the hardware claimed by Appellant , such as the execute unit receiving decoded RISC and decoded CISC instructions. A "design choice" is another way saying "obvious to try". "Design Choice" or "Obvious to Try" is not prima facie obviousness.

30

Ser. No.

081179,926

1 9

Printed 8/29/95

Artunit: 2315

`Design choice' is the cited motivation on page 5, line 3 of the third action, and again

in the second office action on page 7, line 15 and page 5, line 5:
Thus,it would have been an obvious engineering design choice to one of ordinary skill in the

5

art at the time of the invention to utilize both software and hardware implementation to emulate

CISC insmtions on a RISC computer. (emphasis added)

Design choice is another way of stating `obvious to try'. The designer has the `choice'. What i s the `choice' ? It is experimentation. When several alternative approaches exist, the Examiaer is not free to choose the more obscure choices when the prior art
.

10

clearly points toward another `choice'. In this case, the prior art as a whole and

in particular clearly teach software emulation, not the invention. Certainly
the structure of the invention - dual instruction-set decoders using a shared execution unit

- is nowhere taught or suggested in the prior art.

at are the `~bvious' e s i g n ~ Choices 7

15

The `obvious' way to execute both RlSC and CISC instruction sets is to duplicate the processor core. One core executes RISC, while the other core executes CISC. Each core has its own instruction fetcher, decoder, execute unit, and TLB. This is similar to having a co-processor for the second instruction set.

20

In contrast to this `obvious' way, the invention does not duplicate the entire core.
Rather than duplicate the entire core, the instruction fetcher, execute unit, and TLB are shared among both instruction sets. Only the CISC decode logic needs to be added.

25

Another approach used commercially is to emulate the CISC instruction set by replacing or translating CISC instructions into WSC instructions. This is what the

Portanovareference does. This approach can require little or no additional hardware,
although the performance is poor, as each CISC instruction is replaced by dozens or
hundreds of RISC instructions. In contrast, the invention can directly decode and

30

execute the simpler CISC instructions, although more complex CISC instructions are emulated by replacing them with groups or routines of WSC instructions.

Ser. No. 081179,926 ~ r t U N t :2315

20

Printed 8/29/95

The invention taught by the Appellant differs from both of these more obvious approaches by directly executing both RISC and CISC instructions in a shared execute
Unit. The Appellant 's disclosure is being used as a blueprint to reject his own claims.
5

What the prior art as a whole fairly teaches and suggests is to use a co-processor and
duplicate all of the hardware, or to emulate the entire CZSC instruction set.
The prior art itself in no way suggests adding just the second decoder but not the rest

of the core. The prior art nowhere suggests executing some of the CISC instructions 10 but not all of them on a RISClCISC processor. The Examiner has impermissibly used the hindsight gained from Appellant 's disclosure to make major, unsuggested modifications to the prior art to reject Appellant 's claims. The prior art as a whole fairly teaches and suggests either of the two approaches 15 described above. No actual suggestion in the prior art references exists pointing toward the claimed invention. Other combinations are possible, and this undue experimentation has been cloaked as an "engineering design choice," Something in the prior art must suggest the desirability of making the combination. Uniroyal, Znc. v. Rudkin-Wiley

Cop., 837 F.2d 1044, 5 USPQ2d 1434, 1438 (CAFC 1988). If the prior art provides
20 no teaching, suggestion, or incentive supporting the combination proposed by the Examiner, then the rejection is in error and must be reversed. In Re Bond,910 F.2d 831, 15 USPQ2d 1566 (CAFC 1990). The claimed invention must not be used as a blueprint.
lnvenffon does not merely Duplicate Hardware

25

- On/y Decoders

The remarks in paragraph 16 of the second office action refer to W ' s two decoders

as "clear evidence of a system employing partially duplicated hardware resources". It
was also stated that whether the emulation unit is integrated or separate is a design of choice.

Art Unit: 2315

Ser. No. 081179,926

21

Printed 8/29/95

Appellant 's invention allows both instruction sets to be executed on a single execution unit, eliminating duplicated hardware for execution. Thus dupficated hardware resources are not needed for the execute unit, but only for the decoders. This approach

5

is not suggested in any of the cited references and is not merely a design choice of separating units, as in a coprocessor, or integrating units. ~ewly-~i~ed References Show Extensions of One Instruction Set Appellant has reviewed the two newly-cited references. L&gsLaL is clearly directed to

10

ancxtenslM of a singie instruction set rather than a separate gsmd instruction set. '
&& teach an "assist" that is attached to the main processor via a set of busses (col 2,
lines 40-45). Thus the "assist" appears to be the co-processor embodiment with a new name.

15

Co-processors execute in hardware extensions of a single instruction set. A co-

processor is a separate (2nd) execution facility which supports a subset of a
instruction set, while the invention is a single execution facility which supports a
~

of instruction sets.

20

also teach a single instruction set that is partitioned into two or more
subsets,each possibly implemented in a different chip or emulated by software. His
Figure 3 again shows a co-processor embodiment connected to a bus.

In contrast, Appellant 's claim 1 recites "two separate instruction sets", and claim 18
25

recites a RISC and a CISC instruction set. Claim 1 clearly disallows a mere extension

of a single instruction set by stating: "said first encoding of instructions independent

from said second encoding of instructions". Mere extensions of instruction sets must
have dependent Fcodings since otherwise one opcode could be used for two

%I.

&tu&: 2315

No. 081179,926

22

Printed 8129195

instructions. However, two separate instruction sets, such as RlSC and CISC, have one opcode with two different instructions. (Specification, page 25, lines 2-6.) Examiner appears to be using these three new references to show that &&iaa&
5

RISC hardware can be modified to execute native CKSC instructions. However, these that would have sqa,ix& newly-cited references only show
u. -n s ti

Also, these references show mere extensions to a single instruction set,

such as for floating point instructions. Thus, even if these references were used as
10

secondary references in a non-final action, these references do not teach or suggest a single execute unit that executes both RlSC and CISC instructions. OTHER CLAIMS NOT OBVIOUS & RECITE ADDITIONAL ELEMENTS Claim 2 recites that the single instruction fetch buffer (32 of Figure 2, Appendix 2) feeds instructions to both the RISC and CISC decoders 36. Rather than duplicate the entire pipeline, the instruction fetcher, execute unit, and TLB are shared among both

15

instruction sets. Only the CISC decode logic needs to be added. It is not obvious that just the decoder be duplicated while the instruction fetch buffer and execution units not
be duplicated. The obvious approach is to duplicate the entire pipeline.

No R e ~ e ~ n Cited H ~ v i ~ $ ce

with RISC-cisc bit

20

Some elements of dependent claims have not been shown in any of the references. For example, claim 3 claims a "mode register means, coupled to the select means, for indicating an instruction set to be decoded and executed. Examiner has not cited any reference with such a mode register. Independent claim 18 likewise recites a "mode register .means for indicating a current operating mode of said microprocessor",

25 Instead, claims 3 and 4 were rejected as "obvious to one skilled in the art to utilize an

execution mode register for indicating the execution of native and non-native instructions. (second,action, page 4) No prior art was cited for the mode register with

Ser. No. 081179,926 &Unit: 2315

23

Printed 8/29/95

the bit indicating the instruction set, nor was any motivation given other than

) `obvious'. Claim 18 was rejected `for the same rationales' (second action, page 5.
Claim 19 recites that the mode register means indicates NSC mode, CISC mode, or an
5

emulation mode. Nowhere has the Examiner shown a teaching or suggestion for such a mode register indicating one of RISC, CISC, or emulation modes. Claims 5, 15 and 20 indicate that the instruction set is changed when an undecodable instruction is signaled by the second instruction set (CISC) decoder. Since some, but

1 0

not all, CISC instructions are decoded by the CISC decoder, the CISC decoder signals

the mode control to change to emulation mode (claims 15, 20) or first-instruction-set

) OUSC) mode when an undecodable CISC instruction is encountered (claim 5.
does not teach changing from CISC mode to WSC mode or emulation mode.

15

Apparently his RISC processor is always emulating CISC instructions with RISC instructions and thus has no need to change to decoding CISC instructions. Indeed, never executes or decodes CISC instructions but merely emulates them. There is simply no teaching in Portanova as relied on by the rejection of claim 5 (second action, page 4-5).

20

Bullions Terminology Dfffers from Standard Usage Claims 6-43, 77

-

Since portanova and anishi do not teach a TLB, the Bullions reference is cited for claims 6-13, 17 for teaching a TLB having translations for both host and guest insmctions, and for teaching that a miss in the TLB also triggers a change of execution
25
mode.

Bullions teaches a CISC system that emulates guest architectures on a native
architecture. Each level of architecture is capable of using virtual addressing with dynamic address translation. (col 1, lines 8-25). All operating systems described by

Ser. No. 081179,926
Artunit:

24

Printed 8/29/95

2315

Buliions are well-known CISC architectures (col 1, lines 29, 50). Thus Buliions does
not teach processing both RISC and CISC instructions, but merely teaches emulating "guest" CISC architectures on a native CISC machine.

5

Bullions uses the word "architecture" to mean something other than "instruction set".
His summary and claims refer to guest "programs" but not to guest "instructions" from
a different "instruction set", A guest program does not necessarily use a different instruction set. Indeed, the "plural levels of architecture" referred to "invoke piural levels of address translation." (col 5, lines 24-29). These plural architectures refer to architectures, to . BvlIians clearly states that "different architectures may use different size addresses, e,g. one architecture may use 24 bit addresses while another architecture may use 3 1 bit addresses." However, all operating systems described by Builions use the same instruction set.

1 0

15

For example, the 286 microprocessor uses 24-bit addressing while the 386 uses 32-bit addressing. Yet both the 286 and 386 execute the same CISC x86 instruction set. Claim 6 recites that the TLB provide "an indication to said mode control means to 20 change said instruction set decoded to said first instruction set when no translation i s found in said TLB". Bullions does not teach that another instruction set is decoded.

Bullions teaches that the architecture "mode" is changed on a TLB miss, causing a native program rather than a guest program to execute. However, these programs are
from the same instruction set, not different instruction sets, 25 It is thus improper to replace Bullions architecture or program w t the word ih "instruction", as his programs and architectures refer to different address translation architectures and not to different instruction sets. Bullions teaches guest programs and guest architectures, but not guest instructions from a different instruction set.

Sex.

No. 08/179,926 ArtUnit: 2315

25

Printed 8129195

Claim 17 recites translating memory references generated by CISC instructions that are directly executed, where the translation of memory references is controlled by a software translator routine comprised of RISC instructions. Bullions fails to teach that

5

RISC instructions are used in a software translator routine while some CISC instructions are directly executed. Thus claim 17 cannot be obvious in view of

and the other references. Subject of Dependent Claims 743,76 Not Cited or Obvious
10

In claim 7 a handler routine offirst instructions is executed when the mode control is
signaled by an undecodable second instruction or a TLB miss. No reference teaches or suggests that a handler routine of instructions from a first instruction set be fetched

from main memory and executed when a signal is received from a decoder for a second
instruction set or from a TLB. No handler routine has even been cited in the
15

references. Certainly a handler routine from one instruction set being called by a decoder for another instruction set is not obvious.

In Claim 8 an exception from the execute unit causes the mode control to change to
decoding the fvst instruction set. Bullions was cited for teaching switching the
20

execution mode in response to an interrupt at col. 13, lines 18-62. This cited text simply teaches calling a control program (CP) when an interrupt is received. No instruction set switch occurs. Claim 9 recites that all references to main memory from the second instruction set are

25

translated by the TLB, but claim 10 reveals that onlyfirst instructions can load the TLB. No specific rejection for claims 9-10 have been given by the Examiner. The cited references fail to teach or suggest that a f i m instruction set is used to loud a TLB which translates main memory references generated by a second instruction set. This is

Ser. No, 08/179,926 Artunit: 2315

26

P i t d 8/29/95 rne

not obvious nor trivial. Examiner should cite all claimed elements or allow the claim if unable to do so.

5

In claim 11 extended first insmtctions modify TLB entries. .&&hns is cited as teaching "a special instruction to initiate software routine emulation and reload the TLB (see
col. 12, lines 63-67)." The cited text teaches a "start interpretive execution (SIE) instructip. This instruction simply initiates guest virtual machine (VM) operation. Nothing is said here about reloading the TLB. Claim 11 recites that the "address translation entries in said TLB are modified only by said extended instructions."

10

In claim 12 first instructions are decoded following a reset, while Claim 13 further recites that these extended instructions are decoded only when the mode control is signaled to change instruction sets, or immediately following a reset. Examiner has rejected claims 12-13 as merely "obvious to one skilled in the art to reset the system

15

execution mode to a normal operation in response to a system reset signal. Examiner is obliged to cite references showing these claim limitations. Indeed, the normal mode of operation could be considered the mode the user executes his programs in, which is not used after a reset. Instead of a 'normal' mode, an operating system may be activated after a reset.

20

Claim 16 adds that the emulation routine uses RISC instructions and extended instructions. The extended instructions use undefined opcodes in the RISC instruction set. Examiner has not cited any reference teaching that undefined RISC opcodes be used for extended instructions. Indeed, no rejection was given for claims 14-16, 18-20 25 except for being rejected "for the same rationales".

Many other claims were summarily rejected with no attempt at an element-by-element analysis. If these features are truly conventional, then the Examiner is obliged to cite
references for these features or submit an affidavit. M.P.E.P. $ 706.02(a). Clearly the

Ser. No. 08/179,926 AnUnit: 2315

27

Printed 8/29/95

scope and subject of these claims differ from the scope of other claims, and the Appellant deserves to have these claims examined too. M.P.E.P. CONCLUSION

PI 904,904.02.

Qu The E ~ & ~reference does not explicitly teach hardware execution of both CISC and
5

RISC instruction seis in a single processor. &xGiw~% explicitly teaches emulation of
CISC using RISC instructions. CISC instructions are never directly executed in

`s hardware. No reference teaches that only a subset of a second, independent CISC instruction set is decoded while an entire first gSrSC) instruction set is decoded.
10

No valid `suggestion' of hardware execution of CISC instructions by Ponanova is
possible since explicitly teaches away from CISC hardware being designed with the RlSC hardware, stating:

15

"the designer attempts to maximize execution of the RlSC (hardwired) insaction set. Once the RKSC is hardware des@& it can be sent to the factory for reduction to silicon. The designer &,n writes the CISC htruction emulator using RISC instructions, as described in the example above. (~0130, 52-57, emphasis added) Iines

Portanovadesigns the RISC hardware and sends the design out for silicon fabrication,
lh.m writes CISC emulation code.
20 The purpose of Eortanova is destroyed by any modification for hardware execution of CISC instructions, since additional CISC hardware must be included in the hardware design, increasing the design time that Portanova claims to reduce.
25

hd&, Appellant's believe that they have significantly advanced the state of the art by their invention which efficiently uses a single execute pipeline but two instruction decoders. Only a subset of the second instruction set need be decoded and directly executed. Others will waste precious CPU die area by having two separate, complete

CISC and RISC execute pipelines. Others will decode the entire CISC instruction set.

Ser. No. 081179,926 An Unit: 2315

28

Printed 8/29/95

Some (such as Portanova) will forfeit performance by emulating one instruction set. Appeilant 's invention is efficient and the public would benefit by its disclosure. For &e foregoing reasons, Appellant submits that the rejection of claims 1-20 is in

5

error and should be reversed on appeal.

Sbart T. Auvinen 429 26th Avenue Santa CNZ,CA 95062
[phone] [phone] Fax

Respectfully Submitted,
Stuart T. Auvinen Agent for Appellant Reg. No. 36,435